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Hello Matt DeVillier, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86369?usp=email
to look at the new patch set (#3).
Change subject: drivers/crb: Always generate TPM ACPI Tables
......................................................................
drivers/crb: Always generate TPM ACPI Tables
Commit `fb2c09d5162719a72f0fbc533bec0aa3e8458b93` stopped the SSDT
containing TPM tables if PTT was not active, as at the time, the
table unconditionally reported the device present in the _STA
method.
If the Intel ME is disabled, Linux will still try to probe the TPM,
causing a 1 minute 30 second delay booting.
Commit `d503ce1277b968daf9f96bb2215c8ec0e8a17f8a` made the _STA to
return an accurate state, so now, the tables can always be
generated and Linux will probe correctly without a delay.
Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/crb/tis.c
1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86369/3
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Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Gerrit-Change-Number: 86369
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86142?usp=email )
Change subject: libpayload: Unify selfboot() implementations
......................................................................
libpayload: Unify selfboot() implementations
selfboot() doesn't really need to be architecture dependent. All
architectures are essentially doing the same thing with a normal
function call, only x86_32 needs an extra attribute. arm64 and x86 also
previously haven't been passing the coreboot table pointer, even though
they should. This patch fixes that.
Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86142
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M payloads/libpayload/arch/arm/Makefile.mk
M payloads/libpayload/arch/arm64/Makefile.mk
D payloads/libpayload/arch/arm64/selfboot.c
M payloads/libpayload/arch/x86/Makefile.mk
D payloads/libpayload/arch/x86/selfboot.c
M payloads/libpayload/libc/Makefile.mk
R payloads/libpayload/libc/selfboot.c
7 files changed, 8 insertions(+), 78 deletions(-)
Approvals:
Yu-Ping Wu: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/payloads/libpayload/arch/arm/Makefile.mk b/payloads/libpayload/arch/arm/Makefile.mk
index 47c271b..3308135 100644
--- a/payloads/libpayload/arch/arm/Makefile.mk
+++ b/payloads/libpayload/arch/arm/Makefile.mk
@@ -39,7 +39,6 @@
libc-y += virtual.c
libc-y += exception_asm.S exception.c
libc-y += cache.c cpu.S
-libc-y += selfboot.c
# Will fall back to default_memXXX() in libc/memory.c if GPL not allowed.
libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S
diff --git a/payloads/libpayload/arch/arm64/Makefile.mk b/payloads/libpayload/arch/arm64/Makefile.mk
index d6cc51e..a4fda1d 100644
--- a/payloads/libpayload/arch/arm64/Makefile.mk
+++ b/payloads/libpayload/arch/arm64/Makefile.mk
@@ -36,7 +36,6 @@
libc-y += memcpy.S memset.S memmove.S
libc-y += exception_asm.S exception.c
libc-y += cache.c cpu.S
-libc-y += selfboot.c
libc-y += mmu.c
libgdb-y += gdb.c
diff --git a/payloads/libpayload/arch/arm64/selfboot.c b/payloads/libpayload/arch/arm64/selfboot.c
deleted file mode 100644
index 5c3e445..0000000
--- a/payloads/libpayload/arch/arm64/selfboot.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-
-void selfboot(void *entry)
-{
- void (*entry_func)(void) = entry;
- entry_func();
-}
diff --git a/payloads/libpayload/arch/x86/Makefile.mk b/payloads/libpayload/arch/x86/Makefile.mk
index 35e69cb..b2aaacc 100644
--- a/payloads/libpayload/arch/x86/Makefile.mk
+++ b/payloads/libpayload/arch/x86/Makefile.mk
@@ -40,7 +40,7 @@
libc-y += main.c sysinfo.c
libc-y += timer.c coreboot.c util.S
libc-y += virtual.c
-libc-y += selfboot.c cache.c
+libc-y += cache.c
libc-y += exception.c
libc-y += delay.c
libc-$(CONFIG_LP_ARCH_X86_32) += exec.c
diff --git a/payloads/libpayload/arch/x86/selfboot.c b/payloads/libpayload/arch/x86/selfboot.c
deleted file mode 100644
index 5c3e445..0000000
--- a/payloads/libpayload/arch/x86/selfboot.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-
-void selfboot(void *entry)
-{
- void (*entry_func)(void) = entry;
- entry_func();
-}
diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk
index 3d070eb..063118a 100644
--- a/payloads/libpayload/libc/Makefile.mk
+++ b/payloads/libpayload/libc/Makefile.mk
@@ -38,6 +38,7 @@
libc-$(CONFIG_LP_LIBC) += coreboot.c
libc-$(CONFIG_LP_LIBC) += fmap.c
libc-$(CONFIG_LP_LIBC) += fpmath.c
+libc-$(CONFIG_LP_LIBC) += selfboot.c
ifeq ($(CONFIG_LP_VBOOT_LIB),y)
libc-$(CONFIG_LP_LIBC) += lp_vboot.c
diff --git a/payloads/libpayload/arch/arm/selfboot.c b/payloads/libpayload/libc/selfboot.c
similarity index 89%
rename from payloads/libpayload/arch/arm/selfboot.c
rename to payloads/libpayload/libc/selfboot.c
index 70cc79e..3e226b4 100644
--- a/payloads/libpayload/arch/arm/selfboot.c
+++ b/payloads/libpayload/libc/selfboot.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Google Inc.
+ * Copyright 2025 Google LLC
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,10 +31,9 @@
void selfboot(void *entry)
{
- __asm__ __volatile__(
- "mov r0, %[cb_header_ptr]\n"
- "bx %[entry]\n"
- :: [cb_header_ptr]"r"(cb_header_ptr), [entry]"r"(entry)
- : "r0"
- );
+#if CONFIG(LP_ARCH_X86_32)
+ __attribute__((__regparm__(0)))
+#endif
+ void (*entry_func)(void *arg) = entry;
+ entry_func(cb_header_ptr);
}
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Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86361?usp=email )
Change subject: soc/intel/common: Add low battery shutdown function
......................................................................
Patch Set 3:
(2 comments)
File src/include/reset.h:
https://review.coreboot.org/c/coreboot/+/86361/comment/e273dfa8_6ceca119?us… :
PS3, Line 51: * 2. Introduces a short delay to allow time for logging.
How is the short delay allowing logging ? If this is just for logging why is it arbitrarily 3 seconds ?
File src/soc/intel/common/reset.c:
https://review.coreboot.org/c/coreboot/+/86361/comment/177976e2_418f82aa?us… :
PS3, Line 27: void do_low_battery_shutdown(void)
I would use poweroff instead of shutdown to stay consistent with other functions introduced by this chain of CLs.
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/86336/comment/da9c142d_b18863e5?us… :
PS6, Line 12: #include <ec/google/chromeec/ec.h>
It should not be needed anymore.
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Change subject: drivers/crb: Always generate TPM ACPI Tables
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/86336/comment/c5f5660f_2205a0f8?us… :
PS4, Line 640: printk(BIOS_EMERG, "This platform doesn't know how to power off before ramstage,"
> Could you state in the commit message that "Poweroff failures in ramstage prior to FSP-S are not addressed by this change." ?
done
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