coreboot-gerrit February 2025

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[S] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Paul Menzel has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86422?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 1: (5 comments) Patchset: PS1: Best would be to suppert ACPI S3 properly. Commit Message: https://review.coreboot.org/c/coreboot/+/86422/comment/0a0936d1_0c9e239a?us… : PS1, Line 9: Brya mainboard does not reliably support S3 entry/exit. Why? https://review.coreboot.org/c/coreboot/+/86422/comment/0a3a7bbc_25ca648d?us… : PS1, Line 9: no not https://review.coreboot.org/c/coreboot/+/86422/comment/5e0b20e3_cf33aabf?us… : PS1, Line 10: Also trigger a fail-safe board : reset if the system resumes from S3. Please make this a separate commit. I also do not agree with this. What does this protect against? If a device owner wants to do ACPI S3 resume, not possible with the standard install, let them. https://review.coreboot.org/c/coreboot/+/86422/comment/273deaeb_db56b6e8?us… : PS1, Line 15: asl ASL -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Jayvik Desai, Ronak Kanabar. Paul Menzel has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86297?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00 ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86297/comment/ec6b3ee6_4a7c4546?us… : PS5, Line 2: alokagarwal Please use your full name. $ git config -g user.name "Ronak Kanabar" $ git commit --amend --author="Ronak Kanabar <ronak.kanabar(a)intel.com>" https://review.coreboot.org/c/coreboot/+/86297/comment/0765baf1_e8ec0713?us… : PS5, Line 9: panther Panther https://review.coreboot.org/c/coreboot/+/86297/comment/8ad5b837_0a33c270?us… : PS5, Line 21: alokagarwal Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/86297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212 Gerrit-Change-Number: 86297 Gerrit-PatchSet: 5 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jayvik Desai <jayvik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:29:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Adjust SSD power sequencing
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Paul Menzel has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/86483?usp=email ) Change subject: mb/google/nissa/var/rull: Adjust SSD power sequencing ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86483/comment/f221d301_2407e029?us… : PS2, Line 15: zhou Zhou -- To view, visit https://review.coreboot.org/c/coreboot/+/86483?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Gerrit-Change-Number: 86483 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Adjust SSD power sequencing
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Paul Menzel has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/86483?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/rull: Adjust SSD power sequencing ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86483/comment/ab85ee0b_7174828e?us… : PS2, Line 2: zhourui Please use your full name. https://review.coreboot.org/c/coreboot/+/86483/comment/95618993_c9b827a0?us… : PS2, Line 7: Adjust SSD power sequencing Please be more specific. https://review.coreboot.org/c/coreboot/+/86483/comment/34bf480e_f33a980c?us… : PS2, Line 9: Improve SSD reset time by enabling earlier sequencing. How much reset time is saved? -- To view, visit https://review.coreboot.org/c/coreboot/+/86483?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Gerrit-Change-Number: 86483 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rex/var/kanix: Add Fn key scancode
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Kenneth Chan, Tarun, Tyler Wang. Paul Menzel has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85438?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/kanix: Add Fn key scancode ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85438/comment/5b9c4dbc_cb000a4d?us… : PS5, Line 9: a scancode of 94 the scancode 94 https://review.coreboot.org/c/coreboot/+/85438/comment/830885c9_a8353bab?us… : PS5, Line 12: TEST=Test pass on kanix Please be more specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/85438?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f Gerrit-Change-Number: 85438 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/agah: Separate the AGAH DPTF OEM variant
by Paul Menzel (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tony Huang, Wisley Chen. Paul Menzel has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86493?usp=email ) Change subject: mb/google/brya/var/agah: Separate the AGAH DPTF OEM variant ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86493/comment/e66f1473_b67c72f8?us… : PS2, Line 9: Use DPTF_ENABLE_OEM_VARIABLES_PROJECT_AGAH to : separate variant Agah code, allowing each OEM to adjust : in EC ASL accordingly. Please re-flow for 72 characters per line. It’ll probably fit into two lines. File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86493/comment/e11a4256_fd9861f8?us… : PS2, Line 383: #ifdef DPTF_ENABLE_OEM_VARIABLES_PROJECT_AGAH : Local0 = ToInteger(EOVD) & EC_OEM_VARIABLE_DATA_MASK : \_SB.DPTF.ODUP(0, Local0) : Local0 = \_SB.DPTF.ODGT(0) : \_SB.DPTF.ODVP() : Notify (\_SB.DPTF, INT3400_ODVP_CHANGED) : #endif It’s common code. Please elaborate in the commit message, why the other boards not defining the macro are not impacted in their functionality. -- To view, visit https://review.coreboot.org/c/coreboot/+/86493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8 Gerrit-Change-Number: 86493 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 09:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86402?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... drivers/wifi/generic: Add Methods to control CNVi enable GPIO Add two new methods, CNVS and CNVC, that can check and control the enable GPIO for a CNVi module. These will be used by the common code for RTD3. Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86402/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 16 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Support body detection to DPTF
by John Su (Code Review) 18 Feb '25

18 Feb '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86494?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF ...................................................................... mb/google/trulo/var/uldrenite: Support body detection to DPTF Use DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH to support body detection to DPTF. BUG=b:394177292 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/86494/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 436207c..bae63af 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -196,6 +196,13 @@ \_SB.DPTC() } #endif + +#ifdef DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH + /* Initialize body detection status to DPTF on OS startup */ + \_SB.DPTF.ODUP(0, STTB) + \_SB.DPTF.ODVP() + Notify (\_SB.DPTF, INT3400_ODVP_CHANGED) +#endif } /* Read requested temperature and check against EC error values */ @@ -469,6 +476,12 @@ \_SB.DPTC() } #endif +#ifdef DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH + /* Initialize body detection status to DPTF on OS startup */ + \_SB.DPTF.ODUP(0, STTB) + \_SB.DPTF.ODVP() + Notify (\_SB.DPTF, INT3400_ODVP_CHANGED) +#endif } // Body Detect Change Event diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h index 818cdef..c91c99b 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h @@ -8,4 +8,6 @@ /* Enable DPTF OEM variable */ #define DPTF_ENABLE_OEM_VARIABLES +#define DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Gerrit-Change-Number: 86494 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable Thunderbolt authentication
by Subrata Banik (Code Review) 18 Feb '25

18 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86420?usp=email ) Change subject: soc/intel/pantherlake: Enable Thunderbolt authentication ...................................................................... soc/intel/pantherlake: Enable Thunderbolt authentication This commit enables Thunderbolt authentication for Panther Lake by assigning `ioe_tcss_valid_tbt_auth` to the valid_tbt_auth field in `soc_tcss_ops`. For the SoC's integrated PD solution, AUX BIAS PAD programming is not required and has been removed. TEST=Verified all USB-C ports are functional. With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing: ``` Scope (\_SB.PCI0.TDM0) { Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"), Package (0x01) { Package (0x02) { "IMR_VALID", One } }, ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"), Package (0x01) { Package (0x02) { "WAKE_SUPPORTED", One } } } ``` Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86420 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/pantherlake/tcss.c 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Jayvik Desai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c index 99cbdd2..c66a5c6 100644 --- a/src/soc/intel/pantherlake/tcss.c +++ b/src/soc/intel/pantherlake/tcss.c @@ -2,9 +2,15 @@ #include <intelblocks/tcss.h> #include <soc/soc_chip.h> +#include <static.h> const struct soc_tcss_ops tcss_ops = { -/* TODO: Implement AUX BIAS PAD Programming if required */ .configure_aux_bias_pads = NULL, - .valid_tbt_auth = NULL, + .valid_tbt_auth = ioe_tcss_valid_tbt_auth, }; + +bool ioe_tcss_valid_tbt_auth(void) +{ + const config_t *config = config_of_soc(); + return config->tbt_authentication; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Gerrit-Change-Number: 86420 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable Thunderbolt authentication
by Kapil Porwal (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86420?usp=email ) Change subject: soc/intel/pantherlake: Enable Thunderbolt authentication ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Gerrit-Change-Number: 86420 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 08:03:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025