coreboot-gerrit January 2025

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yidi Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 12:14:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yidi Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 12:12:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the argument type of MT6363
by Yidi Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85839?usp=email ) Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Merge CB:85840 to this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/85839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Gerrit-Change-Number: 85839 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 12:11:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize clkbuf and srclken in romstage
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85843?usp=email ) Change subject: mb/google/rauru: Initialize clkbuf and srclken in romstage ...................................................................... mb/google/rauru: Initialize clkbuf and srclken in romstage BUG=b:317009620 TEST=Build pass. Check boot log: srclken: [INFO ] RG_CENTRAL_CFG1 : 0x104014e5 [INFO ] RG_CENTRAL_CFG2 : 0x1011 [INFO ] RG_CENTRAL_CFG3 : 0x400f [INFO ] RG_CENTRAL_CFG5 : 0x3bfc1761 [INFO ] RG_CENTRAL_CFG6_1 : 0xffffffff [INFO ] RG_CENTRAL_CFG6_2 : 0x110e clkbuf: [INFO ] clk_buf_dump_clkbuf_log: xo_buf_cw(0x79A ~ 0x7A6): [INFO ] 0xb9/0xb9/0x30/0x30/0x30/0x10/0x9/0x10/0x10/0x10/0x10/0x10/0x10 [INFO ] clk_buf_dump_clkbuf_log: xo_buf_vote(0x54C ~ 0x565): [INFO ] 0x1/0x280/0x0/0x0/0x0/0x0/0x2000/0x0/0x0/0x0/0x0/0x0/0x0/ Change-Id: I9a6f93d3ec27944bea72bbadf95a03a54a8a0662 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85843/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index afd12c6..de6baf9 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/clkbuf_ctl.h> #include <soc/emi.h> #include <soc/irq2axi.h> #include <soc/mt6316.h> @@ -11,6 +12,7 @@ #include <soc/pcie.h> #include <soc/pll.h> #include <soc/pmif.h> +#include <soc/srclken_rc.h> static void raise_little_cpu_freq(void) { @@ -32,6 +34,8 @@ raise_little_cpu_freq(); mt6373_init(); mt6685_init(); + srclken_rc_init(); + clk_buf_init(); mtk_dram_init(); if (CONFIG(PCI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a6f93d3ec27944bea72bbadf95a03a54a8a0662 Gerrit-Change-Number: 85843 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... soc/mediatek/mt8196: Add srclken_rc drivers Mt8196 use new RC mode with clk_buf driver, and need srclken_rc to send cmd. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/srclken_rc.h A src/soc/mediatek/mt8196/srclken_rc.c 4 files changed, 797 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85842/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index a079a05..2011b6b 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -43,6 +43,7 @@ romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c +romstage-y += srclken_rc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dpm_v2.c diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 8d0a4bb..209c290 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -148,6 +148,8 @@ SPM_BASE = IO_PHYS + 0x0C004000, SPM_PBUS_BASE = IO_PHYS + 0x0C00D000, RGU_BASE = IO_PHYS + 0x0C010000, + RC_BASE = IO_PHYS + 0x0C011000, + RC_STATE_BASE = IO_PHYS + 0x0C011100, GPT_BASE = IO_PHYS + 0x0C015000, VLP_CKSYS_BASE = IO_PHYS + 0x0C016000, PMIF_SPMI_P_BASE = IO_PHYS + 0x0C018000, diff --git a/src/soc/mediatek/mt8196/include/soc/srclken_rc.h b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h new file mode 100644 index 0000000..08d0e30 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__ + +/*********************************************************************************** +** Definitions +************************************************************************************/ +/* Channel id: Update this enum for porting */ +enum chn_id { + CHN_SUSPEND = 0, + CHN_MD1, + CHN_MD2, + CHN_MD3, + CHN_MDRF, + CHN_MMWAVE = 5, + CHN_GPS, + CHN_PCIE_CONN1, + CHN_VCORE, + CHN_CONN_MCU, + CHN_COANT = 10, + CHN_NFC_CONN2, + CHN_SUSPEND2, + CHN_UFS_VREQ, + CHN_DCXO_L, + CHN_DCXO_H = 15, + CHN_UFS_2, + CHN_PCIE_2, + CHN_NFC_2, + CHN_EXT1, + CHN_EXT2 = 20, + CHN_EXT3, + CHN_T900, + CHN_RSV1, + CHN_RSV2, + CHN_RSV3 = 25, + CHN_RSV4, + CHN_RSV5, + CHN_RSV6, + CHN_RSV7, + CHN_RSV8 = 30, + CHN_RSV9, + MAX_CHN_NUM, +}; + +struct mtk_rc_regs { + u32 srclken_rc_cfg; + u32 rc_central_cfg1; + u32 rc_central_cfg2; + u32 rc_cmd_arb_cfg; + u32 rc_pmic_rcen_addr; + u32 rc_pmic_rcen_set_clr_addr; + u32 rc_dcxo_fpm_cfg; + u32 rc_central_cfg3; + u32 reserved1[14]; + u32 srclken_sw_con_cfg; + u32 rc_central_cfg4; + u32 reserved2; + u32 rc_debug_cfg; + u32 reserved3; + u32 reserved4; + u32 rc_central_cfg5; + u32 rc_central_cfg6; + u32 rcen_mt_m_cfg_0; + u32 rcen_mt_m_cfg_1; + u32 rcen_mt_p_cfg_0; + u32 rcen_mt_p_cfg_1; + u32 rcen_mt_cfg_0; + u32 reserved5[173]; + u32 central_cfg4_1; + u32 central_cfg6_1; + u32 central_cfg6_2; + u32 reserved6[39]; + u32 subsys_intf_cfg_fpm; + u32 reserved7[5]; + u32 src_pmrc_starter_bypass_cfg; + u32 src_pmrc_starter_disable_cfg; + u32 src_pmrc_multi_master_cfg; + u32 src_pmrc_starter_mask_cfg; + u32 src_pmrc_starter_turn_on_cnt_size; + u32 src_pmrc_starter_turn_off_cnt_size; + u32 reserved8[58]; + u32 rc_mxx_srclken_cfg[MAX_CHN_NUM]; +}; + +DEFINE_BIT(SW_RESET, 0) +DEFINE_BITFIELD(CG_32K_EN, 3, 1) +DEFINE_BIT(CG_FCLK_EN, 2) +DEFINE_BIT(CG_FCLK_FR_EN, 3) +DEFINE_BIT(MUX_FCLK_FR, 4) +DEFINE_BIT(RC_32K_DCM, 8) +DEFINE_BIT(SRCLKEN_RC_EN, 0) +DEFINE_BIT(RCEN_ISSUE_M, 1) +DEFINE_BIT(RC_SPI_ACTIVE, 2) +DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3) +DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5) +DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8) +DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12) +DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22) +DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0) +DEFINE_BITFIELD(VREQ_CTRL, 7, 4) +DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8) +DEFINE_BIT(SRCVOLTEN_VREQ_M, 9) +DEFINE_BIT(FORCE_SRCVOLTEN_OFF, 10) +DEFINE_BIT(FORCE_SRCVOLTEN_ON, 11) +DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12) +DEFINE_BIT(FORCE_VCORE_RDY, 16) +DEFINE_BIT(FORCE_ULPOSC2ON, 17) +DEFINE_BIT(FORCE_ULPOSC_CLK_EN, 18) +DEFINE_BIT(FORCE_ULPOSC_ON, 19) +DEFINE_BIT(DIS_ULPOSC_RDY_CHK, 20) +DEFINE_BIT(PWRAP_SLP_CTRL_M, 21) +DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25) +DEFINE_BIT(FORCE_PWRAP_ON, 26) +DEFINE_BIT(FORCE_PWRAP_AWK, 27) +DEFINE_BIT(NON_DCXO_REQ_FORCEON, 28) +DEFINE_BIT(NON_DCXO_REQ_FORCEOFF, 29) +DEFINE_BIT(DCXO_REQ_FORCEON, 30) +DEFINE_BIT(DCXO_REQ_FORCEOFF, 31) + +DEFINE_BITFIELD(SW_RC_EN, 12, 0) +DEFINE_BITFIELD(SW_RCEN_EN, 25, 13) +DEFINE_BIT(SW_DCXO_M_EN, 28) +DEFINE_BITFIELD(SW_DCXO_M, 31, 29) + +DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0) +DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4) +DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16) + +DEFINE_BIT(TO_LPM_SETTLE_EN, 0) +DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1) +DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2) +DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3) +DEFINE_BIT(TO_BBLPM_SETTLE_ND_EN, 4) +DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12) + +DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1) +DEFINE_BIT(BYPASS_CMD_EN, 2) +DEFINE_BIT(SW_SRCLKEN_RC, 3) +DEFINE_BIT(SW_SRCLKEN_FPM, 4) +DEFINE_BIT(SW_SRCLKEN_BBLPM, 5) +DEFINE_BIT(XO_SOC_LINKAGE_EN, 6) +DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7) +DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8) +DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10) +DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12) +DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22) + +DEFINE_BIT(TACE_EN, 0) +DEFINE_BITFIELD(TIE_SYS_RDY, 4, 1) + +DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 12, 0) +DEFINE_BIT(PWRAP_VLD_FORCE, 16) +DEFINE_BIT(SLEEP_VLD_MODE, 17) +DEFINE_BIT(SCP_SLEEP_REQ_MODE, 18) +DEFINE_BIT(SLEEP_REQ_MODE, 20) +DEFINE_BIT(BYPASS_PMIF_M, 24) +DEFINE_BIT(BYPASS_PMIF_P, 25) + +DEFINE_BIT(TRACE_MODE_EN, 24) +DEFINE_BIT(DBG_STOP_PROT_EN, 28) + +DEFINE_BIT(SPMI_CMD_BYTE_CNT, 0) +DEFINE_BITFIELD(SPMI_M_SLV_ID, 8, 5) +DEFINE_BITFIELD(SPMI_P_SLV_ID, 12, 9) +DEFINE_BIT(SPMI_M_PMIF_ID, 17) +DEFINE_BIT(SPMI_P_PMIF_ID, 18) +DEFINE_BITFIELD(SPMI_M_CMD_TYPE, 21, 19) +DEFINE_BITFIELD(SPMI_P_CMD_TYPE, 22, 21) +DEFINE_BIT(SPMI_M_WRITE_EN, 23) +DEFINE_BIT(SPMI_P_WRITE_EN, 24) +DEFINE_BIT(BROADCAST_MODE_EN, 25) +DEFINE_BIT(MULTI_CMD_MODE_EN, 26) +DEFINE_BIT(DCXO_ENCODE, 27) +DEFINE_BIT(SPMI_M_FIRST, 28) +DEFINE_BITFIELD(REQ_TO_DCXO_MASK, 15, 0) +DEFINE_BITFIELD(PMIC_M_COUNTER_VAL, 3, 0) +DEFINE_BITFIELD(PMIC_P_COUNTER_VAL, 7, 4) +DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 13, 0) +DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 29, 16) +DEFINE_BIT(FPM_ACK, 1) +DEFINE_BIT(BBLPM_ACK, 3) + +struct mtk_rc_status_regs { + u32 reserved1[3]; + u32 rc_spi_sta_0; + u32 rc_pi_po_sta; + u32 reserved2[283]; + u32 rc_mxx_req_sta_0[MAX_CHN_NUM]; +}; + +#define REQ_TO_SPMI_P_MASK_SHFT 0 +#define BYPASS_DCXO_VOTE_L_SHIFT 0 +#define BYPASS_DCXO_VOTE_H_SHIFT 16 + +enum { + SW_SRCLKEN_FPM_MSK = 0x1, + SW_SRCLKEN_BBLPM_MSK = 0x1, +}; + +/* RC_CENTRAL_CFG2[8] */ +#define SRCLKENAO_MODE 0 +#define VREQ_MODE 1 + +/* RC_CENTRAL_CFG2[25] */ +#define RC_32K 0 +#define RC_ULPOSC1 1 + +/* Signal Control Mode */ +#define MERGE_OR_MODE 0x0 +#define BYPASS_MODE 0x1 +#define MERGE_AND_MODE BIT(1) +#define BYPASS_RC_MODE (0x2 << 1) +#define BYPASS_OR_MODE 0x3 +#define BYPASS_OTHER_MODE (0x3 << 1) +#define ASYNC_MODE BIT(3) + +#define NO_REQ 0 +#define FPM_REQ BIT(4) +#define BBLPM_REQ BIT(5) + +enum rc_ctrl_m { + HW_MODE = 0, + SW_MODE = 1, + INIT_MODE = 0xff, +}; + +enum { + SRLCKEN_RC_BRINGUP = 0, + SRCLKEN_RC_DISABLE, + SRCLKEN_RC_ENABLE, + SRCLKEN_RC_SKIP, +}; + +struct subsys_rc_con { + unsigned int dcxo_prd; + unsigned int xo_prd; + unsigned int cnt_step; + unsigned int track_en; + unsigned int req_ack_imd_en; + unsigned int xo_soc_link_en; + unsigned int sw_bblpm; + unsigned int sw_fpm; + unsigned int sw_rc; + unsigned int bypass_cmd; + unsigned int dcxo_settle_blk_en; +}; + +int srclken_rc_init(void); + +#endif diff --git a/src/soc/mediatek/mt8196/srclken_rc.c b/src/soc/mediatek/mt8196/srclken_rc.c new file mode 100644 index 0000000..cf2215a --- /dev/null +++ b/src/soc/mediatek/mt8196/srclken_rc.c @@ -0,0 +1,543 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/clkbuf_ctl.h> +#include <soc/pmif.h> +#include <soc/pmif_common.h> +#include <soc/spmi.h> +#include <soc/srclken_rc.h> +#include <timer.h> + +static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE; +static struct mtk_rc_status_regs *rc_status_regs = (struct mtk_rc_status_regs *)RC_STATE_BASE; + +#define ACK_DELAY_US 10 +#define ACK_DELAY_TIMES 200 + +/* RC_CENTRAL_CFG1 setting */ +#define RC_CENTRAL_ENABLE_VAL 1 +#define RC_CENTRAL_DISABLE_VAL 0 + +/* register direct write */ +#define IS_SPI2PMIC_SET_CLR_VAL 0 +#define KEEP_RC_SPI_ACTIVE_VAL 1 +#define SRCLKEN_RC_EN_SEL_VAL 0 + +/* RC_CENTRAL_CFG1 settle time setting */ +#define VCORE_SETTLE_TIME_VAL 0x7 /* ~= 200us */ +#define ULPOSC_SETTLE_TIME_VAL 0x4 /* ~= ? 150us */ +#define NON_DCXO_SETTLE_TIME_VAL 0x1 /* 2^(step+5)*0x33*30.77ns~=400us */ +#define DCXO_SETTLE_TIME_VAL 0x41 /* 2^(step+5)*0x87*30.77ns~= 1063us */ + +/* RC_CENTRAL_CFG2 setting */ +/* use srlckenao to set vcore */ +#define SPI_TRIG_MODE SRCLKENAO_MODE +/* release vcore when spi request done */ +#define IS_SPI_DONE_RELEASE 0 +/* pmic spec under 200us */ +#define SPI_CLK_SRC RC_32K +/* RC_CENTRAL_CFG2 control mode */ +/* merge with spm */ +#define SRCLKENO_0_CTRL_M BYPASS_MODE +/* merge with vreq */ +#define VREQ_CTRL_M BYPASS_MODE +/* merge with ulposc */ +#define ULPOSC_CTRL_M_VAL BYPASS_MODE +/* merge with pwrap_scp */ +#define PWRAP_CTRL_M MERGE_OR_MODE + +/* RC_DCXO_FPM_CFG*/ +#define MD0_SRCLKENO_0_MASK_B 0 /* md0 control by pmrc */ +#define FULL_SET_HW_MODE 0 /* dcxo mode use pmrc_en */ +/* RC_DCXO_FPM_CFG control mode*/ +/* merge with spm */ +#define DCXO_FPM_CTRL_MODE (MERGE_OR_MODE | ASYNC_MODE) + +/* RC_CENTRAL_CFG5 */ +#define RC_SPMI_BYTE_LEN 0x1 /* 0: 2bytes, 1: 2 * 2bytes */ +#define PMIC_GROUP_ID 0xB + +/* pmrc_en address */ +/* default use this reg direct write */ +#define PMRC_CON0 0x190 +#define PMRC_CON0_SET 0x198 +#define PMRC_CON0_CLR 0x19A + +#define SW_BBLPM_HIGH 1 +#define SW_BBLPM_LOW 0 +#define SW_FPM_HIGH 1 +#define SW_FPM_LOW 0 +enum { + DXCO_SETTLE_BLK_EN = 1, + DXCO_SETTLE_BLK_DIS = 0, +}; + +#define REQ_ACK_IMD_EN 1 +#define REQ_ACK_IMD_DIS 0 + +#define SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + _sw_bblpm, _sw_fpm, _sw_rc, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + [_id] = { \ + .dcxo_prd = _dcxo_prd, \ + .xo_prd = _xo_prd, \ + .cnt_step = CENTROL_CNT_STEP, \ + .track_en = 0, \ + .req_ack_imd_en = _req_ack_imd_en, \ + .xo_soc_link_en = 0, \ + .sw_bblpm = _sw_bblpm, \ + .sw_fpm = _sw_fpm, \ + .sw_rc = _sw_rc, \ + .bypass_cmd = _bypass_cmd, \ + .dcxo_settle_blk_en = _dcxo_settle_blk_en, \ + } + +/* Init as SW FPM mode */ +#define SUB_CTRL_CON_INIT(_id, _dcxo_prd, _xo_prd, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) + +/* Init as SW LPM mode */ +#define SUB_CTRL_CON_NO_INIT(_id, _dcxo_prd, _xo_prd, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + SW_BBLPM_LOW, SW_FPM_LOW, SW_MODE, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) + +/* Normal init, SW FPM mode */ +#define SUB_CTRL_CON_EN(_id, _xo_prd, _req_ack_imd_en) \ + SUB_CTRL_CON_INIT(_id, \ + DCXO_STABLE_TIME, _xo_prd, \ + _req_ack_imd_en, 0, DXCO_SETTLE_BLK_EN) + +/* XO/DCXO settle time=0, bypass cmd */ +#define SUB_CTRL_CON_DIS(_id) \ + SUB_CTRL_CON_INIT(_id, \ + DCXO_STABLE_TIME, 0, REQ_ACK_IMD_EN, \ + 0x1, DXCO_SETTLE_BLK_DIS) + +/* Normal init, SW LPM mode */ +#define SUB_CTRL_CON_UNUSE(_id, _xo_prd, _req_ack_imd_en) \ + SUB_CTRL_CON_NO_INIT(_id, \ + DCXO_STABLE_TIME, _xo_prd, \ + _req_ack_imd_en, 0, DXCO_SETTLE_BLK_EN) + + +/* Porting starting from here */ +/* MXX_SRCLKEN_CFG settle time setting */ +#define CENTROL_CNT_STEP 0x3 /* Fix in 3 */ +#define DCXO_STABLE_TIME 0x70 /* ~= 700us */ +#define XO_DEFAULT_STABLE_TIME 0x29 /* ~= 400us */ +#define XO_MD0_STABLE_TIME 0x15 /* ~= 200us */ +#define XO_MD1_STABLE_TIME 0x15 /* ~= 200us */ +#define XO_MD2_STABLE_TIME 0x33 /* ~= 500us */ +#define XO_MDRF_STABLE_TIME 0x3D /* ~= 600us */ +#define VCORE_STABLE_TIME 0x15 /* ~= 200us */ + +/* SUBSYS_INTF_CFG_FPM */ +#define SUB_FPM_SET (BIT(CHN_SUSPEND) | BIT(CHN_MD1) \ + | BIT(CHN_MD2) | BIT(CHN_MD3) \ + | BIT(CHN_MDRF) | BIT(CHN_MMWAVE) \ + | BIT(CHN_GPS) | BIT(CHN_PCIE_CONN1) \ + | BIT(CHN_VCORE) | BIT(CHN_CONN_MCU) \ + | BIT(CHN_COANT) | BIT(CHN_NFC_CONN2) \ + | BIT(CHN_SUSPEND2) | BIT(CHN_UFS_VREQ)) + +/* first try to switch fpm */ +#define INIT_SUBSYS_FPM2LPM (1 << CHN_GPS | 1 << CHN_VCORE \ + | 1 << CHN_CONN_MCU | 1 << CHN_COANT \ + | 1 << CHN_NFC_CONN2) + +/* CFG6_1, all 1 means RC M & P used */ +#define REQ_TO_SPMI_P_SUBSYS 0xFFFFFFFF +/* subsys 8-vcore on/off & subsys 11-pmic power not join DCXO vote*/ +#define SUBSYS_EN_L 0x110E +#define SUBSYS_EN_H 0x0000 + +#define CHN_MASK (BIT(CHN_DCXO_L) | BIT(CHN_DCXO_H)) +#define CHN_NOT_SUPPORT(i) (BIT(i) & CHN_MASK) + +/* after polling ack done, switch to HW mode */ +#define INIT_SUBSYS_TO_HW (1 << CHN_SUSPEND | 1 << CHN_MD1 \ + | 1 << CHN_MD2 | 1 << CHN_MD3 \ + | 1 << CHN_MDRF | 1 << CHN_MMWAVE \ + | 1 << CHN_GPS | 1 << CHN_PCIE_CONN1 \ + | 1 << CHN_CONN_MCU \ + | 1 << CHN_COANT | 1 << CHN_NFC_CONN2 \ + | 1 << CHN_SUSPEND2 | 1 << CHN_UFS_VREQ) + +static struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = { + SUB_CTRL_CON_EN(CHN_SUSPEND, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + /* CFG[2] = 0x1 for bypass waiting DCXO settle time */ + /* usually also need to set CFG6_2 not involve FPM vote*/ + SUB_CTRL_CON_INIT(CHN_MD1, DCXO_STABLE_TIME, XO_MD0_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_INIT(CHN_MD2, DCXO_STABLE_TIME, XO_MD1_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_INIT(CHN_MD3, DCXO_STABLE_TIME, XO_MD2_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_MDRF, XO_MDRF_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_MMWAVE, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_GPS, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_PCIE_CONN1, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_INIT(CHN_VCORE, DCXO_STABLE_TIME, VCORE_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_CONN_MCU, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_DIS(CHN_COANT), + SUB_CTRL_CON_EN(CHN_NFC_CONN2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_INIT(CHN_SUSPEND2, DCXO_STABLE_TIME, VCORE_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_UFS_VREQ, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_DIS(CHN_DCXO_L), + SUB_CTRL_CON_DIS(CHN_DCXO_H), + SUB_CTRL_CON_UNUSE(CHN_UFS_2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_PCIE_2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_NFC_2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_EXT1, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_EXT2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_EXT3, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_T900, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV1, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV3, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV4, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV5, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV6, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV7, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV8, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_UNUSE(CHN_RSV9, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN) +}; + +static void rc_dump_reg_info(void) +{ + u32 ch; + + printk(BIOS_INFO, "RG_DEBUG_CFG[24] : 0x%#lx\n", + (read32(&rc_regs->rc_debug_cfg) & BIT(24)) >> 24); + printk(BIOS_INFO, "RG_SRCLKEN_RC_CFG : 0x%x\n", read32(&rc_regs->srclken_rc_cfg)); + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (CHN_NOT_SUPPORT(ch)) + continue; + printk(BIOS_INFO, "RG_M0%d_SRCLKEN_CFG : 0x%#x\n", + ch, read32(&rc_regs->rc_mxx_srclken_cfg[ch])); + } + + printk(BIOS_INFO, "RG_SRCLKEN_SW_CON_CFG : 0x%x\n", + read32(&rc_regs->srclken_sw_con_cfg)); + printk(BIOS_INFO, "RG_PMIC_RCEN_ADDR : 0x%x\n", read32(&rc_regs->rc_pmic_rcen_addr)); + printk(BIOS_INFO, "RG_PMIC_RCEN_SET_CLR_ADDR : 0x%x\n", + read32(&rc_regs->rc_pmic_rcen_set_clr_addr)); + printk(BIOS_INFO, "RG_CMD_ARB_CFG : 0x%x\n", read32(&rc_regs->rc_cmd_arb_cfg)); + printk(BIOS_INFO, "RG_CENTRAL_CFG1 : 0x%x\n", read32(&rc_regs->rc_central_cfg1)); + printk(BIOS_INFO, "RG_CENTRAL_CFG2 : 0x%x\n", read32(&rc_regs->rc_central_cfg2)); + printk(BIOS_INFO, "RG_CENTRAL_CFG3 : 0x%x\n", read32(&rc_regs->rc_central_cfg3)); + printk(BIOS_INFO, "RG_CENTRAL_CFG5 : 0x%x\n", read32(&rc_regs->rc_central_cfg5)); + printk(BIOS_INFO, "RG_CENTRAL_CFG6_1 : 0x%x\n", read32(&rc_regs->central_cfg6_1)); + printk(BIOS_INFO, "RG_CENTRAL_CFG6_2 : 0x%x\n", read32(&rc_regs->central_cfg6_2)); + printk(BIOS_INFO, "RG_DCXO_FPM_CFG : 0x%x\n", read32(&rc_regs->rc_dcxo_fpm_cfg)); + printk(BIOS_INFO, "SUBSYS_INTF_CFG_FPM : 0x%x\n", + read32(&rc_regs->subsys_intf_cfg_fpm)); + printk(BIOS_INFO, "RG_CENTRAL_CFG4 : 0x%x\n", read32(&rc_regs->rc_central_cfg4)); + printk(BIOS_INFO, "RG_CENTRAL_CFG4_1 : 0x%x\n", read32(&rc_regs->central_cfg4_1)); + printk(BIOS_INFO, "RG_SRC_PMIC_MULTI_MASTER_CFG : 0x%x\n", + read32(&rc_regs->src_pmrc_multi_master_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_DISABLE_CFG : 0x%x\n", + read32(&rc_regs->src_pmrc_starter_disable_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_MASK_CFG : 0x%x\n", + read32(&rc_regs->src_pmrc_starter_mask_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_BYPASS_CFG : 0x%x\n", + read32(&rc_regs->src_pmrc_starter_bypass_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_TURN_ON_CNT_SIZE : 0x%x\n", + read32(&rc_regs->src_pmrc_starter_turn_on_cnt_size)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_TURN_OFF_CNT_SIZE : 0x%x\n", + read32(&rc_regs->src_pmrc_starter_turn_off_cnt_size)); + /* skip print RC_Mxx_REQ_STA_0 because code flow ASSERT already */ + printk(BIOS_INFO, "RC_SPI_STA_0:0x%x\n", read32(&rc_status_regs->rc_spi_sta_0)); + printk(BIOS_INFO, "RC_PI_PO_STA:0x%x\n", read32(&rc_status_regs->rc_pi_po_sta)); +} + +/* RC initial flow and relative setting */ +static void rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode) +{ + ASSERT(id < MAX_CHN_NUM); + + switch (mode) { + case INIT_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], + DCXO_SETTLE_BLK_EN, rc_ctrl[id].dcxo_settle_blk_en, + BYPASS_CMD_EN, rc_ctrl[id].bypass_cmd, + SW_SRCLKEN_RC, rc_ctrl[id].sw_rc, + SW_SRCLKEN_FPM, rc_ctrl[id].sw_fpm, + SW_SRCLKEN_BBLPM, rc_ctrl[id].sw_bblpm, + XO_SOC_LINKAGE_EN, rc_ctrl[id].xo_soc_link_en, + REQ_ACK_LOW_IMD_EN, rc_ctrl[id].req_ack_imd_en, + SRCLKEN_TRACK_M_EN, rc_ctrl[id].track_en, + CNT_PRD_STEP, rc_ctrl[id].cnt_step, + XO_STABLE_PRD, rc_ctrl[id].xo_prd, + DCXO_STABLE_PRD, rc_ctrl[id].dcxo_prd); + break; + case SW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 1); + break; + case HW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 0); + break; + default: + return; + } + + printk(BIOS_INFO, "M0%d: 0x%x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + +/* RC subsys FPM control*/ +static void rc_ctrl_fpm_switch(enum chn_id id, unsigned int mode) +{ + ASSERT(id < MAX_CHN_NUM); + + if (mode == SW_FPM_HIGH) + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, 1); + else if (mode == SW_FPM_LOW) + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, 0); + else + return; + + rc_ctrl[id].sw_fpm = mode; + + printk(BIOS_INFO, "M0%d FPM SWITCH: 0x%x\n", + id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + + +static void rc_init_subsys_hw_mode(void) +{ + unsigned int ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (CHN_NOT_SUPPORT(ch)) + continue; + if (INIT_SUBSYS_TO_HW & BIT(ch)) + rc_ctrl_mode_switch(ch, HW_MODE); + } +} + +static void rc_init_subsys_lpm(void) +{ + unsigned int ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (CHN_NOT_SUPPORT(ch)) + continue; + if (INIT_SUBSYS_FPM2LPM & BIT(ch)) + rc_ctrl_fpm_switch(ch, SW_FPM_LOW); + } +} + +static void rc_ctrl_mode_switch_init(void) +{ + unsigned int ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (CHN_NOT_SUPPORT(ch)) + continue; + rc_ctrl_mode_switch(ch, INIT_MODE); + } +} + +static int polling_rc_chn_ack(unsigned int chn, unsigned int state) +{ + if (!retry(ACK_DELAY_TIMES, (read32(&rc_status_regs->rc_mxx_req_sta_0[chn]) & 0xa) == state, udelay(ACK_DELAY_US))) { + printk(BIOS_INFO, "%s: polling M%u status fail(R:0x%x)(C:0x%x)(PMRC:0x%x)\n", + __func__, + chn, + read32(&rc_status_regs->rc_mxx_req_sta_0[chn]), + read32(&rc_regs->rc_mxx_srclken_cfg[chn]), + clk_buf_get_pmrc_en0()); + return -1; + } + + return 0; +} + +int srclken_rc_init(void) +{ + unsigned int ch; + unsigned int state; + int ret = 0; + + /* enable srclken_rc debug trace */ + SET32_BITFIELDS(&rc_regs->rc_debug_cfg, TRACE_MODE_EN, 0x1); + + /* Set SW RESET 1 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0x1); + + /* Wait 100us */ + dsb(); + udelay(100); + + /* Set SW CG 1 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0x7); + + /* Wait 100us */ + dsb(); + udelay(100); + + /* Set Clock Mux*/ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, MUX_FCLK_FR, 0x1); + + /* Set req_filter m00~m13 as default SW_FPM */ + rc_ctrl_mode_switch_init(); + + /* enable sw trace & pmrc_o0 sel */ + SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TACE_EN, 0x1); + SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TIE_SYS_RDY, 0x1); + + /* Set PMIC addr for SPI CMD */ + write32(&rc_regs->rc_pmic_rcen_addr, PMRC_CON0); + + write32(&rc_regs->rc_pmic_rcen_set_clr_addr, PMRC_CON0); + + write32(&rc_regs->rc_cmd_arb_cfg, 0); + + /* CFG1 setting for spi cmd config */ + write32(&rc_regs->rc_central_cfg1, + _BF_VALUE(DCXO_SETTLE_T, DCXO_SETTLE_TIME_VAL) | + _BF_VALUE(NON_DCXO_SETTLE_T, NON_DCXO_SETTLE_TIME_VAL) | + _BF_VALUE(ULPOSC_SETTLE_T, ULPOSC_SETTLE_TIME_VAL) | + _BF_VALUE(VCORE_SETTLE_T, VCORE_SETTLE_TIME_VAL) | + _BF_VALUE(SRCLKEN_RC_EN_SEL, SRCLKEN_RC_EN_SEL_VAL) | + _BF_VALUE(RC_SPI_ACTIVE, KEEP_RC_SPI_ACTIVE_VAL) | + _BF_VALUE(RCEN_ISSUE_M, IS_SPI2PMIC_SET_CLR_VAL) | + _BF_VALUE(SRCLKEN_RC_EN, RC_CENTRAL_DISABLE_VAL)); + + /* CFG2 setting for signal mode of each control mux */ + write32(&rc_regs->rc_central_cfg2, + _BF_VALUE(PWRAP_SLP_MUX_SEL, SPI_CLK_SRC) | + _BF_VALUE(PWRAP_SLP_CTRL_M, PWRAP_CTRL_M) | + _BF_VALUE(ULPOSC_CTRL_M, ULPOSC_CTRL_M_VAL) | + _BF_VALUE(SRCVOLTEN_VREQ_M, IS_SPI_DONE_RELEASE) | + _BF_VALUE(SRCVOLTEN_VREQ_SEL, SPI_TRIG_MODE) | + _BF_VALUE(VREQ_CTRL, VREQ_CTRL_M) | + _BF_VALUE(SRCVOLTEN_CTRL, SRCLKENO_0_CTRL_M)); + + write32(&rc_regs->rc_central_cfg3, + _BF_VALUE(TO_LPM_SETTLE_T, 0x4) | + _BF_VALUE(TO_BBLPM_SETTLE_EN, 0x1) | + _BF_VALUE(BLK_COANT_DXCO_MD_TARGET, 0x1) | + _BF_VALUE(BLK_SCP_DXCO_MD_TARGET, 0x1) | + _BF_VALUE(TO_LPM_SETTLE_EN, 0x1)); + + /* broadcast/multi-cmd setting */ + write32(&rc_regs->rc_central_cfg5, + _BF_VALUE(SPMI_CMD_BYTE_CNT, RC_SPMI_BYTE_LEN) | + _BF_VALUE(SPMI_M_SLV_ID, PMIC_GROUP_ID) | + _BF_VALUE(SPMI_P_SLV_ID, PMIC_GROUP_ID) | + _BF_VALUE(SPMI_P_PMIF_ID, 0x1) | + _BF_VALUE(SPMI_M_CMD_TYPE, 0x3) | /* SPMI Burst write */ + _BF_VALUE(SPMI_P_CMD_TYPE, 0x3) | /* SPMI Burst write */ + _BF_VALUE(SPMI_M_WRITE_EN, 0x1) | + _BF_VALUE(SPMI_P_WRITE_EN, 0x1) | + _BF_VALUE(BROADCAST_MODE_EN, 0x1) | + _BF_VALUE(DCXO_ENCODE, 0x1) | /* DCXO 3bits --> 2bits */ + _BF_VALUE(SPMI_M_FIRST, 0x1) | + BIT(29)); /* Setting: [29:30] = 1 means send 2 bytes to pmif*/ + + /* CFG6-1 = 0x11111111 */ + write32(&rc_regs->central_cfg6_1, + REQ_TO_SPMI_P_SUBSYS << REQ_TO_SPMI_P_MASK_SHFT); + + /* CFG6-2 = 0x00001100 */ + write32(&rc_regs->central_cfg6_2, + SUBSYS_EN_L << BYPASS_DCXO_VOTE_L_SHIFT | + SUBSYS_EN_H << BYPASS_DCXO_VOTE_H_SHIFT); + + /* Set srclkeno_0/conn_bt as factor to allow dcxo change to FPM */ + write32(&rc_regs->rc_dcxo_fpm_cfg, + _BF_VALUE(SUB_SRCLKEN_FPM_MSK_B, FULL_SET_HW_MODE) | + _BF_VALUE(SRCVOLTEN_FPM_MSK_B, MD0_SRCLKENO_0_MASK_B) | + _BF_VALUE(DCXO_FPM_CTRL_M, DCXO_FPM_CTRL_MODE)); + + /* Set fpm channel */ + write32(&rc_regs->subsys_intf_cfg_fpm, + _BF_VALUE(SRCLKEN_FPM_MASK_B, SUB_FPM_SET)); + + /* Trigger srclken_rc enable */ + SET32_BITFIELDS(&rc_regs->rc_central_cfg1, SRCLKEN_RC_EN, 0x1); + + /* use PMIF_M + PMIF_P */ + write32(&rc_regs->rc_central_cfg4, + _BF_VALUE(SLEEP_VLD_MODE, 0x1) | _BF_VALUE(PWRAP_VLD_FORCE, 0x1)); + + /* CFG4_1: extension CFG4[0:15] */ + write32(&rc_regs->central_cfg4_1, + _BF_VALUE(KEEP_RC_SPI_ACTIVE, 0x800)); + + /* Wait 100us */ + dsb(); + udelay(100); + + /* Set SW RESET 0 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0); + + /* Wait 100us */ + dsb(); + udelay(100); + + /* Set SW CG 0 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0); + + /* Wait 500us */ + dsb(); + udelay(500); + + /* Set req_filter m00~m31 FPM to LPM, hack original rc_ctrl[]*/ + rc_init_subsys_lpm(); + + /* Polling ACK of Initial Subsys Input */ + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (CHN_NOT_SUPPORT(ch)) + continue; + + state = (rc_ctrl[ch].sw_fpm & SW_SRCLKEN_FPM_MSK) << 1 | + (rc_ctrl[ch].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << 3; + + ret = polling_rc_chn_ack(ch, state); + ASSERT(!ret); + } + + /* Set req_filter m00~m31 */ + rc_init_subsys_hw_mode(); + + /* [1] = 1 means pmrc7,11,13 mux choose non multi master */ + write32(&rc_regs->src_pmrc_multi_master_cfg, 0x00000002); + + /* [0] = 1 means disable pmic starter */ + write32(&rc_regs->src_pmrc_starter_disable_cfg, 0x00000001); + write32(&rc_regs->src_pmrc_starter_mask_cfg, 0x00000000); + + /* pmrc8 & pmrc12 : bypass trigger pmic starter */ + write32(&rc_regs->src_pmrc_starter_bypass_cfg, 0x00001100); + + /* 92E ---> 90us */ + write32(&rc_regs->src_pmrc_starter_turn_on_cnt_size, 0x0000092E); + + /* 92E ---> 90us */ + write32(&rc_regs->src_pmrc_starter_turn_off_cnt_size, 0x0000092E); + + /* write 0 to release force pmic req signal */ + SET32_BITFIELDS(&rc_regs->rc_central_cfg4, PWRAP_VLD_FORCE, 0); + + rc_dump_reg_info(); + + return ret; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85841?usp=email ) Change subject: soc/mediatek/mt8196: Add clk_buf drivers ...................................................................... soc/mediatek/mt8196: Add clk_buf drivers Mt8196 use mt6685 clk_buf, and will use new RC mode with srclken_rc. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/clkbuf_ctl.c A src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h 3 files changed, 971 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85841/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index e967707..a079a05 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -24,6 +24,7 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c +romstage-y += clkbuf_ctl.c romstage-y += ../common/dram_init.c romstage-y += ../common/dramc_param.c romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c diff --git a/src/soc/mediatek/mt8196/clkbuf_ctl.c b/src/soc/mediatek/mt8196/clkbuf_ctl.c new file mode 100644 index 0000000..23a56a7 --- /dev/null +++ b/src/soc/mediatek/mt8196/clkbuf_ctl.c @@ -0,0 +1,430 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <soc/addressmap.h> +#include <soc/clkbuf_ctl.h> +#include <soc/mt6685.h> +#include <timer.h> + +#define XO_RC_MODE 0x1 +#define XO_DISABLE_MODE 0x0 + +#define XO_EN_MODE_MASK 0x7 +#define XO_EN_MODE_SHIFT 0 + +/* Impedance mask/shift, may need update for PMIC which is not 6685*/ +#define XO_IMPEDANCE_MASK 0x7 +#define XO_IMPEDANCE_SHIFT 3 +#define XO_DRIVING_MASK 0x3 +#define XO_DRIVING_SHIFT 6 +#define XO_MODE_SHIFT 0 + +#define clk_buf_enable_xo(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + XO_RC_MODE, \ + XO_EN_MODE_MASK, \ + XO_MODE_SHIFT) + +#define clk_buf_disable_xo(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + XO_DISABLE_MODE, \ + XO_EN_MODE_MASK, \ + XO_MODE_SHIFT) + +#define clk_buf_impedance_config(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + ox[(xo_id)].impedance, \ + XO_IMPEDANCE_MASK, \ + XO_IMPEDANCE_SHIFT) + +#define clk_buf_driving_config(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + ox[(xo_id)].driving, \ + XO_DRIVING_MASK, \ + XO_DRIVING_SHIFT) + +/* Porting starting from here */ + +/* SPMI master/slave, might change in the future */ +#define CLKBUF_SPMI_MASTER SPMI_MASTER_1 +#define CLKBUF_SPMI_SLAVE SPMI_SLAVE_9 + +/* Voting table */ +#define SOC_VOTER_L_MASK 0x01 +#define SOC_VOTER_H_MASK 0x00 + +#define CONN_PCIE_VOTER_L_MASK 0x80 +#define CONN_PCIE_VOTER_H_MASK 0x02 + +#define CONN_GPS_VOTER_L_MASK 0x40 +#define CONN_GPS_VOTER_H_MASK 0x00 + +#define MMWAVE_VOTER_L_MASK 0x00 +#define MMWAVE_VOTER_H_MASK 0x00 + +#define NFC_VOTER_L_MASK 0x00 +#define NFC_VOTER_H_MASK 0x08 + +#define RFMD_2A_VOTER_L_MASK 0x10 +#define RFMD_2A_VOTER_H_MASK 0x00 + +#define UFS_VOTER_L_MASK 0x00 +#define UFS_VOTER_H_MASK 0x20 + +struct ox_cfg ox[] = { + [XO_BBCK1] = { + .reg = XO_BBCK1_MODE_ADDR, + .mode = BBCK_BUF1_STATUS_PMIC, + .impedance = BBCK_BUF1_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF1_DRIVING_STRENGTH, + .voter_mask = { /* 0x0001 */ + .low_byte = SOC_VOTER_L_MASK, + .high_byte = SOC_VOTER_H_MASK, + }, + }, + [XO_BBCK2] = { + .reg = XO_BBCK2_MODE_ADDR, + .mode = BBCK_BUF2_STATUS_PMIC, + .impedance = BBCK_BUF2_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF2_DRIVING_STRENGTH, + .voter_mask = { /* 0x0280 */ + .low_byte = CONN_PCIE_VOTER_L_MASK, + .high_byte = CONN_PCIE_VOTER_H_MASK, + }, + }, + [XO_BBCK3] = { + .reg = XO_BBCK3_MODE_ADDR, + .mode = BBCK_BUF3_STATUS_PMIC, + .impedance = BBCK_BUF3_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF3_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_BBCK4] = { + .reg = XO_BBCK4_MODE_ADDR, + .mode = BBCK_BUF4_STATUS_PMIC, + .impedance = BBCK_BUF4_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF4_DRIVING_STRENGTH, + .voter_mask = { /* 0x0800 */ + .low_byte = NFC_VOTER_L_MASK, + .high_byte = NFC_VOTER_H_MASK, + }, + }, + [XO_BBCK5] = { + .reg = XO_BBCK5_MODE_ADDR, + .mode = BBCK_BUF5_STATUS_PMIC, + .impedance = BBCK_BUF5_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF5_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_RFCK1A] = { + .reg = XO_RFCK1A_MODE_ADDR, + .mode = RFCK_BUF1A_STATUS_PMIC, + .impedance = RFCK_BUF1A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0000 */ + .low_byte = MMWAVE_VOTER_L_MASK, + .high_byte = MMWAVE_VOTER_H_MASK, + }, + }, + [XO_RFCK1B] = { + .reg = XO_RFCK1B_MODE_ADDR, + .mode = RFCK_BUF1B_STATUS_PMIC, + .impedance = RFCK_BUF1B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x2000 */ + .low_byte = UFS_VOTER_L_MASK, + .high_byte = UFS_VOTER_H_MASK, + }, + }, + [XO_RFCK1C] = { + .reg = XO_RFCK1C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_RFCK2A] = { + .reg = XO_RFCK2A_MODE_ADDR, + .mode = RFCK_BUF2A_STATUS_PMIC, + .impedance = RFCK_BUF2A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0010 */ + .low_byte = RFMD_2A_VOTER_L_MASK, + .high_byte = RFMD_2A_VOTER_H_MASK, + }, + }, + [XO_RFCK2B] = { + .reg = XO_RFCK2B_MODE_ADDR, + .mode = RFCK_BUF2B_STATUS_PMIC, + .impedance = RFCK_BUF2B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0040 */ + .low_byte = CONN_GPS_VOTER_L_MASK, + .high_byte = CONN_GPS_VOTER_H_MASK, + }, + }, + [XO_RFCK2C] = { + .reg = XO_RFCK2C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_CONCK1] = { + .reg = XO_CONCK1_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_CONCK2] = { + .reg = XO_CONCK2_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + } +}; + +unsigned int clk_buf_get_pmrc_en0(void) +{ + unsigned int out = 0; + unsigned char tmp = 0; + + tmp = mt6685_read8(MT6685_PMRC_CON0); + out = tmp; + tmp = mt6685_read8(MT6685_PMRC_CON1); + out |= tmp << 8; + + return out; +} + +static void clk_buf_dump_dws_log(void) +{ + u8 i; + + printk(BIOS_INFO, "%s: DWS_CLKBUF_STA BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\n"); + + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_IMPEDANCE BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_DRIVING BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].driving); + + printk(BIOS_INFO, "\n"); +} + +static void clk_buf_dump_clkbuf_log(void) +{ + u8 val; + u8 xo_buf_cw[XO_NUMBER]; + u16 xo_buf_vote[XO_NUMBER]; + u8 dig_manctrl_cw1; + u8 bblpm_cw0; + u32 dig26m_div2; + u8 i; + + for (i = 0; i < XO_NUMBER; i++) { + xo_buf_cw[i] = mt6685_read8(MT6685_DCXO_EXTBUF1_CW0 + i); + val = mt6685_read8(MT6685_XO_BUF_CTL0_L + (2 * i)); + xo_buf_vote[i] = val; + + val = mt6685_read8(MT6685_XO_BUF_CTL0_H + (2 * i)); + xo_buf_vote[i] |= (val << 8); + } + + dig_manctrl_cw1 = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + bblpm_cw0 = mt6685_read8(MT6685_DCXO_BBLPM_CW0); + + dig26m_div2 = mt6685_read_field(RG_XO_DIG26M_DIV2_ADDR, + RG_XO_DIG26M_DIV2_MASK, + RG_XO_DIG26M_DIV2_SHIFT); + + printk(BIOS_INFO, "%s: xo_buf_cw(0x79A ~ 0x7A6):\n", __func__); + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "0x%x/", xo_buf_cw[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: xo_buf_vote(0x54C ~ 0x565):\n", __func__); + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "0x%x/", xo_buf_vote[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: dig_manctrl_cw1(0x%x): 0x%x\nbblpm_cw0(0x%x): 0x%x\n", + __func__, + MT6685_DCXO_DIG_MANCTRL_CW1, + dig_manctrl_cw1, + MT6685_DCXO_BBLPM_CW0, + bblpm_cw0); + printk(BIOS_INFO, "%s: dig26m_div2(0x%x): 0x%x\n", + __func__, + RG_XO_DIG26M_DIV2_ADDR, + dig26m_div2); +} + +static void clk_buf_init_pmic_clkbuf(void) +{ + u8 val; + u8 i; + + /* 1.1 Write XO_BUF impedance & driving */ + for (i = 0; i < XO_NUMBER; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + clk_buf_impedance_config(i); + + /* 1.2 Write XO_BUF driving */ + for (i = 0; i <= XO_BBCK5; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + clk_buf_driving_config(i); + + /* 1.3 Mask RC voting table by dws */ + for (i = 0; i < XO_NUMBER; ++i) { + if (ox[i].mode == CLOCK_BUFFER_DISABLE) { + ox[i].voter_mask.low_byte = 0; + ox[i].voter_mask.high_byte = 0; + } + } + + /* 1.4 Write RC voting table */ + for (i = 0; i < XO_NUMBER; i++) { + mt6685_write8(XO_BBCK1_VOTE_L_ADDR + (2 * i), + ox[i].voter_mask.low_byte); + mt6685_write8(XO_BBCK1_VOTE_H_ADDR + (2 * i), + ox[i].voter_mask.high_byte); + } + + /* 1.5 turn on LDO HW control from XO_BUFs */ + mt6685_write_field(RG_LDO_VRFCK1_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK1_HW14_OP_EN_MASK, + RG_LDO_VRFCK1_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK2_HW14_OP_EN_MASK, + RG_LDO_VRFCK2_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VBBCK_HW14_OP_EN_MASK, + RG_LDO_VBBCK_HW14_OP_EN_SHIFT); + + /* 1.6 turn off LDO SW control */ + mt6685_write_field(RG_LDO_VRFCK1_EN_ADDR, + 0x0, + RG_LDO_VRFCK1_EN_MASK, + RG_LDO_VRFCK1_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_EN_ADDR, + 0x0, + RG_LDO_VRFCK2_EN_MASK, + RG_LDO_VRFCK2_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_EN_ADDR, + 0x0, + RG_LDO_VBBCK_EN_MASK, + RG_LDO_VBBCK_EN_SHIFT); + + /* 1.7 Enable/Disable XO by dws */ + for (i = 0; i < XO_NUMBER; ++i) { + if (ox[i].mode == CLOCK_BUFFER_DISABLE || + ox[i].mode == CLOCK_BUFFER_SW_CONTROL) + clk_buf_disable_xo(i); + else if (ox[i].mode == CLOCK_BUFFER_HW_CONTROL) + clk_buf_enable_xo(i); + } + + /* 1.8 RC mode setting + * en_bb hw mode + * switch to srclken_rc mode + */ + val = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + val &= (~(XO_PMIC_TOP_DIG_SW_MASK << XO_PMIC_TOP_DIG_SW_SHIFT)); + val &= (~(XO_ENBB_MAN_MASK << XO_ENBB_MAN_SHIFT)); + val &= (~(XO_ENBB_EN_M_MASK << XO_ENBB_EN_M_SHIFT)); + val &= (~(XO_CLKSEL_EN_M_MASK << XO_CLKSEL_EN_M_SHIFT)); + mt6685_write8(MT6685_DCXO_DIG_MANCTRL_CW1, val); +} + +static u16 dcxo_dbg_read_auxout(u8 sel) +{ + u16 val = 0; + u8 tmp = 0; + + mt6685_write8(XO_STATIC_AUXOUT_SEL_ADDR, sel); + + tmp = mt6685_read8(XO_STATIC_AUXOUT_L_ADDR); + val = tmp; + + tmp = mt6685_read8(XO_STATIC_AUXOUT_H_ADDR); + val |= tmp << 8; + + printk(BIOS_INFO, "%s: sel=%d, rg_auxout=0x%x\n", + __func__, sel, val); + + return val; +} + +int clk_buf_init(void) +{ + _Static_assert(ARRAY_SIZE(ox) == XO_NUMBER, "Wrong array size of ox"); + + /* Check dws setting */ + clk_buf_dump_dws_log(); + + /* dump lpsd dbg0-3 for debug during pmic_long_press_reset */ + dcxo_dbg_read_auxout(124); + dcxo_dbg_read_auxout(125); + dcxo_dbg_read_auxout(126); + dcxo_dbg_read_auxout(127); + + clk_buf_init_pmic_clkbuf(); + + /* Check if the setting is ok */ + clk_buf_dump_clkbuf_log(); + + return 0; +} diff --git a/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h new file mode 100644 index 0000000..94bdaae --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h @@ -0,0 +1,540 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ + +#include <console/console.h> + +#define MT6685_PMRC_CON0 0x190 +#define MT6685_PMRC_CON1 0x191 +#define MT6685_PMRC_CON0_SET 0x198 +#define MT6685_PMRC_CON1_SET 0x199 +#define MT6685_PMRC_CON0_CLR 0x19a +#define MT6685_PMRC_CON1_CLR 0x19b +#define MT6685_PMRC_CON3 0x19c +#define MT6685_XO_BUF_CTL0_L 0x54c +#define MT6685_XO_BUF_CTL0_H 0x54d +#define MT6685_XO_BUF_CTL1_L 0x54e +#define MT6685_XO_BUF_CTL1_H 0x54f +#define MT6685_XO_BUF_CTL2_L 0x550 +#define MT6685_XO_BUF_CTL2_H 0x551 +#define MT6685_XO_BUF_CTL3_L 0x552 +#define MT6685_XO_BUF_CTL3_H 0x553 +#define MT6685_XO_BUF_CTL4_L 0x554 +#define MT6685_XO_BUF_CTL4_H 0x555 +#define MT6685_XO_BUF_CTL5_L 0x556 +#define MT6685_XO_BUF_CTL5_H 0x557 +#define MT6685_XO_BUF_CTL6_L 0x558 +#define MT6685_XO_BUF_CTL6_H 0x559 +#define MT6685_XO_BUF_CTL7_L 0x55a +#define MT6685_XO_BUF_CTL7_H 0x55b +#define MT6685_XO_BUF_CTL8_L 0x55c +#define MT6685_XO_BUF_CTL8_H 0x55d +#define MT6685_XO_BUF_CTL9_L 0x55e +#define MT6685_XO_BUF_CTL9_H 0x55f +#define MT6685_XO_BUF_CTL10_L 0x560 +#define MT6685_XO_BUF_CTL10_H 0x561 +#define MT6685_XO_BUF_CTL11_L 0x562 +#define MT6685_XO_BUF_CTL11_H 0x563 +#define MT6685_XO_BUF_CTL12_L 0x564 +#define MT6685_XO_BUF_CTL12_H 0x565 +#define MT6685_XO_CONN_BT0 0x567 +#define MT6685_DCXO_DIG_MANCTRL_CW1 0x796 +#define MT6685_DCXO_BBLPM_CW0 0x797 +#define MT6685_DCXO_BBLPM_CW1 0x798 +#define MT6685_DCXO_LDO_CW0 0x799 +#define MT6685_DCXO_EXTBUF1_CW0 0x79a +#define MT6685_DCXO_EXTBUF2_CW0 0x79b +#define MT6685_DCXO_EXTBUF3_CW0 0x79c +#define MT6685_DCXO_EXTBUF4_CW0 0x79d +#define MT6685_DCXO_EXTBUF5_CW0 0x79e +#define MT6685_DCXO_EXTBUF6_CW0 0x79f +#define MT6685_DCXO_EXTBUF7_CW0 0x7a0 +#define MT6685_DCXO_EXTBUF8_CW0 0x7a1 +#define MT6685_DCXO_EXTBUF9_CW0 0x7a2 +#define MT6685_DCXO_EXTBUF10_CW0 0x7a3 +#define MT6685_DCXO_EXTBUF11_CW0 0x7a4 +#define MT6685_DCXO_EXTBUF12_CW0 0x7a5 +#define MT6685_DCXO_EXTBUF13_CW0 0x7a6 +#define MT6685_DCXO_RGMON_CW0_L 0x7b2 +#define MT6685_DCXO_RGMON_CW0_H 0x7b3 +#define MT6685_DCXO_RGMON_CW2_L 0x7b4 +#define MT6685_DCXO_RGMON_CW2_H 0x7b5 +#define MT6685_DCXO_RGMON_CW1 0x7c3 +#define MT6685_DCXO_DIGCLK_ELR 0x7f4 +#define MT6685_LDO_VBBCK_CON0 0x1b87 +#define MT6685_LDO_VBBCK_OP_EN1 0x1b8e +#define MT6685_LDO_VBBCK_OP_EN1_SET 0x1b8f +#define MT6685_LDO_VBBCK_OP_EN1_CLR 0x1b90 +#define MT6685_LDO_VRFCK1_CON0 0x1b97 +#define MT6685_LDO_VRFCK1_OP_EN1 0x1b9e +#define MT6685_LDO_VRFCK1_OP_EN1_SET 0x1b9f +#define MT6685_LDO_VRFCK1_OP_EN1_CLR 0x1ba0 +#define MT6685_LDO_VRFCK2_CON0 0x1ba7 +#define MT6685_LDO_VRFCK2_OP_EN1 0x1bae +#define MT6685_LDO_VRFCK2_OP_EN1_SET 0x1baf +#define MT6685_LDO_VRFCK2_OP_EN1_CLR 0x1bb0 + +/* Register_TOP_REG*/ +#define RG_DCXO_SRCLKEN1_MODE_ADDR MT6685_PMRC_CON3 +#define RG_DCXO_SRCLKEN1_MODE_MASK 0x3 +#define RG_DCXO_SRCLKEN1_MODE_SHIFT 2 +/* Register_SCK_REG*/ +#define XO_BBCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL0_L +#define XO_BBCK1_VOTE_L_MASK 0xff +#define XO_BBCK1_VOTE_L_SHIFT 0 +#define XO_BBCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL0_H +#define XO_BBCK1_VOTE_H_MASK 0x3f +#define XO_BBCK1_VOTE_H_SHIFT 0 +#define XO_BBCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL1_L +#define XO_BBCK2_VOTE_L_MASK 0xff +#define XO_BBCK2_VOTE_L_SHIFT 0 +#define XO_BBCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL1_H +#define XO_BBCK2_VOTE_H_MASK 0x3f +#define XO_BBCK2_VOTE_H_SHIFT 0 +#define XO_BBCK3_VOTE_L_ADDR MT6685_XO_BUF_CTL2_L +#define XO_BBCK3_VOTE_L_MASK 0xff +#define XO_BBCK3_VOTE_L_SHIFT 0 +#define XO_BBCK3_VOTE_H_ADDR MT6685_XO_BUF_CTL2_H +#define XO_BBCK3_VOTE_H_MASK 0x3f +#define XO_BBCK3_VOTE_H_SHIFT 0 +#define XO_BBCK4_VOTE_L_ADDR MT6685_XO_BUF_CTL3_L +#define XO_BBCK4_VOTE_L_MASK 0xff +#define XO_BBCK4_VOTE_L_SHIFT 0 +#define XO_BBCK4_VOTE_H_ADDR MT6685_XO_BUF_CTL3_H +#define XO_BBCK4_VOTE_H_MASK 0x3f +#define XO_BBCK4_VOTE_H_SHIFT 0 +#define XO_BBCK5_VOTE_L_ADDR MT6685_XO_BUF_CTL4_L +#define XO_BBCK5_VOTE_L_MASK 0xff +#define XO_BBCK5_VOTE_L_SHIFT 0 +#define XO_BBCK5_VOTE_H_ADDR MT6685_XO_BUF_CTL4_H +#define XO_BBCK5_VOTE_H_MASK 0x3f +#define XO_BBCK5_VOTE_H_SHIFT 0 +#define XO_RFCK1A_VOTE_L_ADDR MT6685_XO_BUF_CTL5_L +#define XO_RFCK1A_VOTE_L_MASK 0xff +#define XO_RFCK1A_VOTE_L_SHIFT 0 +#define XO_RFCK1A_VOTE_H_ADDR MT6685_XO_BUF_CTL5_H +#define XO_RFCK1A_VOTE_H_MASK 0x3f +#define XO_RFCK1A_VOTE_H_SHIFT 0 +#define XO_RFCK1B_VOTE_L_ADDR MT6685_XO_BUF_CTL6_L +#define XO_RFCK1B_VOTE_L_MASK 0xff +#define XO_RFCK1B_VOTE_L_SHIFT 0 +#define XO_RFCK1B_VOTE_H_ADDR MT6685_XO_BUF_CTL6_H +#define XO_RFCK1B_VOTE_H_MASK 0x3f +#define XO_RFCK1B_VOTE_H_SHIFT 0 +#define XO_RFCK1C_VOTE_L_ADDR MT6685_XO_BUF_CTL7_L +#define XO_RFCK1C_VOTE_L_MASK 0xff +#define XO_RFCK1C_VOTE_L_SHIFT 0 +#define XO_RFCK1C_VOTE_H_ADDR MT6685_XO_BUF_CTL7_H +#define XO_RFCK1C_VOTE_H_MASK 0x3f +#define XO_RFCK1C_VOTE_H_SHIFT 0 +#define XO_RFCK2A_VOTE_L_ADDR MT6685_XO_BUF_CTL8_L +#define XO_RFCK2A_VOTE_L_MASK 0xff +#define XO_RFCK2A_VOTE_L_SHIFT 0 +#define XO_RFCK2A_VOTE_H_ADDR MT6685_XO_BUF_CTL8_H +#define XO_RFCK2A_VOTE_H_MASK 0x3f +#define XO_RFCK2A_VOTE_H_SHIFT 0 +#define XO_RFCK2B_VOTE_L_ADDR MT6685_XO_BUF_CTL9_L +#define XO_RFCK2B_VOTE_L_MASK 0xff +#define XO_RFCK2B_VOTE_L_SHIFT 0 +#define XO_RFCK2B_VOTE_H_ADDR MT6685_XO_BUF_CTL9_H +#define XO_RFCK2B_VOTE_H_MASK 0x3f +#define XO_RFCK2B_VOTE_H_SHIFT 0 +#define XO_RFCK2C_VOTE_L_ADDR MT6685_XO_BUF_CTL10_L +#define XO_RFCK2C_VOTE_L_MASK 0xff +#define XO_RFCK2C_VOTE_L_SHIFT 0 +#define XO_RFCK2C_VOTE_H_ADDR MT6685_XO_BUF_CTL10_H +#define XO_RFCK2C_VOTE_H_MASK 0x3f +#define XO_RFCK2C_VOTE_H_SHIFT 0 +#define XO_CONCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL11_L +#define XO_CONCK1_VOTE_L_MASK 0xff +#define XO_CONCK1_VOTE_L_SHIFT 0 +#define XO_CONCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL11_H +#define XO_CONCK1_VOTE_H_MASK 0x3f +#define XO_CONCK1_VOTE_H_SHIFT 0 +#define XO_CONCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL12_L +#define XO_CONCK2_VOTE_L_MASK 0xff +#define XO_CONCK2_VOTE_L_SHIFT 0 +#define XO_CONCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL12_H +#define XO_CONCK2_VOTE_H_MASK 0x3f +#define XO_CONCK2_VOTE_H_SHIFT 0 +#define XO_MODE_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_MODE_CONN_BT_MASK_MASK 0x1 +#define XO_MODE_CONN_BT_MASK_SHIFT 0 +#define XO_BUF_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_BUF_CONN_BT_MASK_MASK 0x1 +#define XO_BUF_CONN_BT_MASK_SHIFT 1 +/* Register_DCXO_REG*/ +#define XO_PMIC_TOP_DIG_SW_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_PMIC_TOP_DIG_SW_MASK 0x1 +#define XO_PMIC_TOP_DIG_SW_SHIFT 0 +#define XO_ENBB_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_MAN_MASK 0x1 +#define XO_ENBB_MAN_SHIFT 1 +#define XO_ENBB_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_EN_M_MASK 0x1 +#define XO_ENBB_EN_M_SHIFT 2 +#define XO_CLKSEL_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_MAN_MASK 0x1 +#define XO_CLKSEL_MAN_SHIFT 3 +#define XO_CLKSEL_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_EN_M_MASK 0x1 +#define XO_CLKSEL_EN_M_SHIFT 4 +#define XO_BB_LPM_EN_M_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_M_MASK 0x1 +#define XO_BB_LPM_EN_M_SHIFT 0 +#define XO_BB_LPM_EN_SEL_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_SEL_MASK 0x1 +#define XO_BB_LPM_EN_SEL_SHIFT 1 +#define XO_BBCK1_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK1_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK1_BBLPM_EN_MASK_SHIFT 2 +#define XO_BBCK2_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK2_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK2_BBLPM_EN_MASK_SHIFT 3 +#define XO_BBCK3_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK3_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK3_BBLPM_EN_MASK_SHIFT 4 +#define XO_BBCK4_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK4_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK4_BBLPM_EN_MASK_SHIFT 5 +#define XO_BBCK5_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK5_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK5_BBLPM_EN_MASK_SHIFT 6 +#define XO_BBLPM_EN_MAN_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_MASK 0x1 +#define XO_BBLPM_EN_MAN_SHIFT 0 +#define XO_BBLPM_EN_MAN_M_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_M_MASK 0x1 +#define XO_BBLPM_EN_MAN_M_SHIFT 1 +#define XO_VBBCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_MAN_MASK 0x1 +#define XO_VBBCK_EN_MAN_SHIFT 0 +#define XO_VBBCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_M_MASK 0x1 +#define XO_VBBCK_EN_M_SHIFT 1 +#define XO_VRFCK1_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_MAN_MASK 0x1 +#define XO_VRFCK1_EN_MAN_SHIFT 2 +#define XO_VRFCK1_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_M_MASK 0x1 +#define XO_VRFCK1_EN_M_SHIFT 3 +#define XO_VRFCK2_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_MAN_MASK 0x1 +#define XO_VRFCK2_EN_MAN_SHIFT 4 +#define XO_VRFCK2_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_M_MASK 0x1 +#define XO_VRFCK2_EN_M_SHIFT 5 +#define XO_VCONCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_MAN_MASK 0x1 +#define XO_VCONCK_EN_MAN_SHIFT 6 +#define XO_VCONCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_M_MASK 0x1 +#define XO_VCONCK_EN_M_SHIFT 7 +#define XO_BBCK1_MODE_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_MASK 0x1 +#define XO_BBCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK1_RSEL_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK1_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK1_HD_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK1_HD_SHIFT 6 +#define XO_BBCK2_MODE_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_MASK 0x1 +#define XO_BBCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK2_RSEL_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK2_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK2_HD_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK2_HD_SHIFT 6 +#define XO_BBCK3_MODE_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_MASK 0x1 +#define XO_BBCK3_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK3_RSEL_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK3_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK3_HD_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK3_HD_SHIFT 6 +#define XO_BBCK4_MODE_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_MASK 0x1 +#define XO_BBCK4_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK4_RSEL_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK4_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK4_HD_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK4_HD_SHIFT 6 +#define XO_BBCK5_MODE_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_MASK 0x1 +#define XO_BBCK5_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK5_RSEL_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK5_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK5_HD_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK5_HD_SHIFT 6 +#define XO_RFCK1A_MODE_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_MASK 0x1 +#define XO_RFCK1A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1A_RSEL_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define RG_XO_EXTBUF_RFCK1A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1A_RSEL_SHIFT 3 +#define XO_RFCK1B_MODE_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_MASK 0x1 +#define XO_RFCK1B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1B_RSEL_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define RG_XO_EXTBUF_RFCK1B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1B_RSEL_SHIFT 3 +#define XO_RFCK1C_MODE_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_MASK 0x1 +#define XO_RFCK1C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1C_RSEL_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define RG_XO_EXTBUF_RFCK1C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1C_RSEL_SHIFT 3 +#define XO_RFCK2A_MODE_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_MASK 0x1 +#define XO_RFCK2A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2A_RSEL_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define RG_XO_EXTBUF_RFCK2A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2A_RSEL_SHIFT 3 +#define XO_RFCK2B_MODE_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_MASK 0x1 +#define XO_RFCK2B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2B_RSEL_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define RG_XO_EXTBUF_RFCK2B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2B_RSEL_SHIFT 3 +#define XO_RFCK2C_MODE_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_MASK 0x1 +#define XO_RFCK2C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2C_RSEL_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define RG_XO_EXTBUF_RFCK2C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2C_RSEL_SHIFT 3 +#define XO_CONCK1_MODE_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_MASK 0x1 +#define XO_CONCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK1_RSEL_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define RG_XO_EXTBUF_CONCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK1_RSEL_SHIFT 3 +#define XO_CONCK2_MODE_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_MASK 0x1 +#define XO_CONCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK2_RSEL_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define RG_XO_EXTBUF_CONCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK2_RSEL_SHIFT 3 +#define XO_AUXOUT_SEL_L_ADDR MT6685_DCXO_RGMON_CW0_L +#define XO_AUXOUT_SEL_L_MASK 0xff +#define XO_AUXOUT_SEL_L_SHIFT 0 +#define XO_AUXOUT_SEL_H_ADDR MT6685_DCXO_RGMON_CW0_H +#define XO_AUXOUT_SEL_H_MASK 0x3 +#define XO_AUXOUT_SEL_H_SHIFT 0 +#define XO_STATIC_AUXOUT_L_ADDR MT6685_DCXO_RGMON_CW2_L +#define XO_STATIC_AUXOUT_L_MASK 0xff +#define XO_STATIC_AUXOUT_L_SHIFT 0 +#define XO_STATIC_AUXOUT_H_ADDR MT6685_DCXO_RGMON_CW2_H +#define XO_STATIC_AUXOUT_H_MASK 0xff +#define XO_STATIC_AUXOUT_H_SHIFT 0 +#define XO_STATIC_AUXOUT_SEL_ADDR MT6685_DCXO_RGMON_CW1 +#define XO_STATIC_AUXOUT_SEL_MASK 0x7f +#define XO_STATIC_AUXOUT_SEL_SHIFT 0 +#define RG_XO_DIG26M_DIV2_ADDR MT6685_DCXO_DIGCLK_ELR +#define RG_XO_DIG26M_DIV2_MASK 0x1 +#define RG_XO_DIG26M_DIV2_SHIFT 0 +/* Register_LDO_REG*/ +#define RG_LDO_VBBCK_EN_ADDR MT6685_LDO_VBBCK_CON0 +#define RG_LDO_VBBCK_EN_MASK 0x1 +#define RG_LDO_VBBCK_EN_SHIFT 0 +#define RG_LDO_VBBCK_HW14_OP_EN_ADDR MT6685_LDO_VBBCK_OP_EN1 +#define RG_LDO_VBBCK_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VBBCK_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK1_EN_ADDR MT6685_LDO_VRFCK1_CON0 +#define RG_LDO_VRFCK1_EN_MASK 0x1 +#define RG_LDO_VRFCK1_EN_SHIFT 0 +#define RG_LDO_VRFCK1_HW14_OP_EN_ADDR MT6685_LDO_VRFCK1_OP_EN1 +#define RG_LDO_VRFCK1_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK1_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK2_EN_ADDR MT6685_LDO_VRFCK2_CON0 +#define RG_LDO_VRFCK2_EN_MASK 0x1 +#define RG_LDO_VRFCK2_EN_SHIFT 0 +#define RG_LDO_VRFCK2_HW14_OP_EN_ADDR MT6685_LDO_VRFCK2_OP_EN1 +#define RG_LDO_VRFCK2_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK2_HW14_OP_EN_SHIFT 6 + + +/* Update PMIF base by platform if needed */ +#if !defined(PMIF_SPMI_P_BASE_CLKBUF) +#define PMIF_SPMI_P_BASE_CLKBUF 0x1C014000 +#endif /* !defined(PMIF_SPMI_P_BASE_CLKBUF) */ + +/* PMIF Register*/ +#define PMIFSPMI_INF_EN (PMIF_SPMI_BASE + 0x0024) +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPMI_OTHER_INF_EN (PMIF_SPMI_BASE + 0x0028) +#define SPMI_OTHER_INF_DCXO0_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO0_EN_SHFT 0 +#define SPMI_OTHER_INF_DCXO1_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO1_EN_SHFT 1 + +#define PMIFSPMI_ARB_EN (PMIF_SPMI_BASE + 0x0150) +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPMI_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_CONN_SHFT 17 +#define PMIFSPMI_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_NFC_SHFT 18 + +#define PMIFSPMI_SLEEP_PROTECTION_CRL (PMIF_SPMI_BASE + 0x03F0) +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI_MODE_CRL (PMIF_SPMI_BASE + 0x0408) +#define PMIFSPMI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI_MD_CTL_PMIF_RDY_SHFT 9 +#define PMIFSPMI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRCLK_EN_SHFT 10 +#define PMIFSPMI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRVOL_EN_SHFT 11 + +/* SPMI_P part */ +#define PMIFSPMI2_INF_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0024) +#define PMIFSPMI2_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI2_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPMI2_OTHER_INF_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0028) +#define SPMI2_OTHER_INF_DCXO0_EN_MSK 0x1 +#define SPMI2_OTHER_INF_DCXO0_EN_SHFT 0 +#define SPMI2_OTHER_INF_DCXO1_EN_MSK 0x1 +#define SPMI2_OTHER_INF_DCXO1_EN_SHFT 1 + +#define PMIFSPMI2_ARB_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0150) +#define PMIFSPMI2_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI2_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPMI2_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPMI2_ARB_EN_DCXO_CONN_SHFT 17 +#define PMIFSPMI2_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPMI2_ARB_EN_DCXO_NFC_SHFT 18 + +#define PMIFSPMI2_SLEEP_PROTECTION_CRL (PMIF_SPMI_P_BASE_CLKBUF + 0x03F0) +#define PMIFSPMI2_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI2_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI2_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI2_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI2_MODE_CRL (PMIF_SPMI_P_BASE_CLKBUF + 0x0408) +#define PMIFSPMI2_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI2_MD_CTL_PMIF_RDY_SHFT 9 +#define PMIFSPMI2_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI2_MD_CTL_SRCLK_EN_SHFT 10 +#define PMIFSPMI2_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI2_MD_CTL_SRVOL_EN_SHFT 11 + +enum { + CLOCK_BUFFER_DISABLE, + CLOCK_BUFFER_SW_CONTROL, + CLOCK_BUFFER_HW_CONTROL +}; + +enum { + CLK_BUF_OUTPUT_IMPEDANCE_0, + CLK_BUF_OUTPUT_IMPEDANCE_1, + CLK_BUF_OUTPUT_IMPEDANCE_2, + CLK_BUF_OUTPUT_IMPEDANCE_3, + CLK_BUF_OUTPUT_IMPEDANCE_4, + CLK_BUF_OUTPUT_IMPEDANCE_5, + CLK_BUF_OUTPUT_IMPEDANCE_6, + CLK_BUF_OUTPUT_IMPEDANCE_7 +}; + +enum { + CLK_BUF_DRIVING_STRENGTH_0,/* Max */ + CLK_BUF_DRIVING_STRENGTH_1, + CLK_BUF_DRIVING_STRENGTH_2, + CLK_BUF_DRIVING_STRENGTH_3,/* Min */ +}; + +#define BBCK_BUF1_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF2_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF3_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF4_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF5_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1B_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define RFCK_BUF2A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF2B_STATUS_PMIC CLOCK_BUFFER_DISABLE + +#define BBCK_BUF1_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF2_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF3_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF4_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF5_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define RFCK_BUF1A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF1B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 + +#define BBCK_BUF1_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF2_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF3_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF4_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF5_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 + +enum pmic_interface_clkbuf { + PMIF_VLD_RDY_CLKBUF = 0, + PMIF_SLP_REQ_CLKBUF, + PMIF_MAX, +}; + +/* XO id: Update this enum for porting */ +enum xo_id { + XO_BBCK1 = 0, + XO_BBCK2, + XO_BBCK3, + XO_BBCK4, + XO_BBCK5, + XO_RFCK1A, + XO_RFCK1B, + XO_RFCK1C, + XO_RFCK2A, + XO_RFCK2B, + XO_RFCK2C, + XO_CONCK1, + XO_CONCK2, + XO_NUMBER, +}; + +struct ox_cfg { + u32 reg; + u8 mode; + u8 impedance; + u8 driving; + struct { + u8 low_byte; + u8 high_byte; + } voter_mask; +}; + +int clk_buf_init(void); +int clk_buf_set_default(void); +unsigned int clk_buf_get_pmrc_en0(void); +void pwrap_interface_init(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Gerrit-Change-Number: 85841 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Correct MT6363 buck5 enable API
by Yidi Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85838?usp=email ) Change subject: soc/mediatek/mt8196: Correct MT6363 buck5 enable API ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Why does the solution modify the mask/offset instead of deleting the function? -- To view, visit https://review.coreboot.org/c/coreboot/+/85838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5 Gerrit-Change-Number: 85838 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 12:03:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Felix Held (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) Change subject: drivers/option: Add forms in cbtables ...................................................................... Patch Set 30: (2 comments) File Documentation/drivers/cfr.md: https://review.coreboot.org/c/coreboot/+/74121/comment/8eabffee_f52bd973?us… : PS30, Line 1: form representation > I think no one bothers to follow up or make new decision, so we decided to get the V1 in with this s […] this has been discussed in at least one coreboot leadership meeting in 2023 and i think also some separate meeting about this specific topic and i'm reasonably certain that we made the decision to use a different name. i'm not too happy about the fact that we spent time discussing this and the result of that discussion basically got ignored https://review.coreboot.org/c/coreboot/+/74121/comment/7fca78cb_7c94793d?us… : PS30, Line 72: > Sorry I dont get it, what do you mean actually? the tags should be defined before being referenced. right now some are referenced in the allowed/required sub nodes of other tags before they are defined -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 30 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 11:28:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <tanleansheng(a)outlook.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: Fix up CFR's open issues
by Felix Held (Code Review) 03 Jan '25

03 Jan '25

Felix Held has posted comments on this change by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/85780?usp=email ) Change subject: Fix up CFR's open issues ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id66808382b93e32c58024462c18b20c2a89d6d23 Gerrit-Change-Number: 85780 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 11:23:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Correct the argument type of ADC
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85840?usp=email to review the following change. Change subject: mb/google/rauru: Correct the argument type of ADC ...................................................................... mb/google/rauru: Correct the argument type of ADC Correct the argument type when calling the mt6363_sdmadc_read API. TEST=Build pass BUG=b:317009620 Change-Id: I3d55e787dd86d474c299b2f7ad4a2fefda436a60 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/boardid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85840/1 diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index e3e0979..fc0230d 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -38,7 +38,7 @@ static uint32_t get_adc_index(unsigned int channel) { - int value; + u32 value; mt6363_sdmadc_read(channel, &value, SDMADC_OPEN, AUXADC_VAL_PROCESSED); assert(channel < ARRAY_SIZE(adc_voltages)); -- To view, visit https://review.coreboot.org/c/coreboot/+/85840?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d55e787dd86d474c299b2f7ad4a2fefda436a60 Gerrit-Change-Number: 85840 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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