coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Paul Menzel, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85806/comment/25437395_d80e936b?us… : PS3, Line 21: > Maybe add the new log messages? ``` MMU: Upper MEM limit is 0x228000000000 MMU: New page tables are required``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:20:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Paul Menzel, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85806/comment/882190b4_cf8c5725?us… : PS3, Line 9: support > support*s* Done File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/a761a118_8933c49e?us… : PS3, Line 150: else > unnecessary `else` keyword. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:20:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85806?usp=email to look at the new patch set (#5). Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... cpu/x86/64bit: Install extended page tables in BSS On Intel 14nm Xeon-SP every processor supports 1TiB of DRAM. Since MMIO is mapped above usable DRAM, the default page tables in RODATA are not sufficient to cover the high MMIO space. This prevents the use of coreboot's ramstage drivers as they cannot access the PCI BARs residing in high MMIO. Introduce a simple page table generator that installs extended page tables in BSS to access up to 48bit of the virtual address space. TEST: QEMU (that does not support 1GB PT) is able to access up to 512 GiB of memory after installing PT in BSS. IBM/SBP1 (that does support 1GB PT) is able to boot to OS with new page tables installed. Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/mmu.c M src/cpu/x86/Kconfig M src/soc/intel/xeon_sp/Kconfig 4 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85806/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 4: (6 comments) File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/735a6aae_4acae07b?us… : PS3, Line 12: #define _PRES (1ULL << 0) > Can't you use the BIT macro? Done https://review.coreboot.org/c/coreboot/+/85806/comment/4911fe13_a46d9706?us… : PS3, Line 49: * when 1GB PT aren't supported it maps 40 bits of the address space (512GiB). > IMO the x86_64 by default boot with 4-level paging and here the 40bit VA is mainly for consideration […] Yes, it "only" increases BSS by 2.1MiB. Older platforms can access up to 40bit VA as access to 48bit VA would make pagetable too big (512MiB of page tables?) and those older platforms do likely not have such high amount of DRAM/MMIO anyways. https://review.coreboot.org/c/coreboot/+/85806/comment/85655878_a17a9793?us… : PS3, Line 64: int > size_t Done https://review.coreboot.org/c/coreboot/+/85806/comment/0981b97b_dd8ed45e?us… : PS3, Line 59: if (cpu_supports_1gb_hugepage()) { : const uintptr_t max_addr = 1ULL * GiB * 512ULL * 512ULL; : const uint64_t incr = 1ULL * GiB; : : /* Build P4MLE */ : for (int i = 0; i < 512; i++) : p4mle[i] = _GEN_DIR(&pdpt[i * 512]); : : /* Build PDPT */ : uint64_t *page_table_ptr = pdpt; : for (uintptr_t addr = 0; addr < max_addr; addr += incr, page_table_ptr++) : *page_table_ptr = _GEN_PAGE(addr); : } else { : const uintptr_t max_addr = 2ULL * MiB * 512ULL * 512ULL; : const uint64_t incr = 2ULL * MiB; : : /* Build P4MLE */ : p4mle[0] = _GEN_DIR(&pdpt[0]); : : /* Build PDPT */ : for (int i = 0; i < 512; i++) : pdpt[i] = _GEN_DIR(&pdt[i * 512]); : : /* Build PDT */ : uint64_t *page_table_ptr = pdt; : for (uintptr_t addr = 0; addr < max_addr; addr += incr, page_table_ptr++) : *page_table_ptr = _GEN_PAGE(addr); : } : > I don't see that. Please explain how it can be improved without reducing readability. Done https://review.coreboot.org/c/coreboot/+/85806/comment/0684ce37_c365ff41?us… : PS3, Line 157: */ > It would be helpful if we could have comments here as well, e.g. […] Done https://review.coreboot.org/c/coreboot/+/85806/comment/2ad36fd6_421bb751?us… : PS3, Line 160: /* Using 512 4K pages limits the usable address space */ > Do we need to make sure the CPU is not working under 5-level paging? (though coreboot never enables […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:18:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85806?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... cpu/x86/64bit: Install extended page tables in BSS On Intel 14nm Xeon-SP every processor support 1TiB of DRAM. Since MMIO is mapped above usable DRAM, the default page tables in RODATA are not sufficient to cover the high MMIO space. This prevents the use of coreboot's ramstage drivers as they cannot access the PCI BARs residing in high MMIO. Introduce a simple page table generator that installs extended page tables in BSS to access up to 48bit of the virtual address space. TEST: QEMU (that does not support 1GB PT) is able to access up to 512 GiB of memory after installing PT in BSS. IBM/SBP1 (that does support 1GB PT) is able to boot to OS with new page tables installed. Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/mmu.c M src/cpu/x86/Kconfig M src/soc/intel/xeon_sp/Kconfig 4 files changed, 217 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85806/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Add support for setting the charging speed
by Sean Rhodes (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Angel Pons, Maxim Polyakov, Maximilian Brune, Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84633?usp=email ) Change subject: ec/starlabs/merlin: Add support for setting the charging speed ...................................................................... Patch Set 17: (3 comments) File src/ec/starlabs/merlin/Kconfig: https://review.coreboot.org/c/coreboot/+/84633/comment/4c1bb9af_735d14c5?us… : PS14, Line 69: EC_STARLABS_ITE > Commit message says Merlin Done File src/ec/starlabs/merlin/ite.c: https://review.coreboot.org/c/coreboot/+/84633/comment/29724598_7fa92383?us… : PS14, Line 251: 0.C > Typo? `0.5C` […] Done, and C-rate https://review.coreboot.org/c/coreboot/+/84633/comment/47f2def6_6e4955bc?us… : PS14, Line 263: 0 > If I remember how the code works, this will fallback to `SPEED_1_0C` Ah, not sure why I didn't use the enum values there.. -- To view, visit https://review.coreboot.org/c/coreboot/+/84633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46faa540530c5bd7f5473021561380213158152e Gerrit-Change-Number: 84633 Gerrit-PatchSet: 17 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:06:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Add support for setting the charging speed
by Angel Pons (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Maxim Polyakov, Maximilian Brune, Paul Menzel, Sean Rhodes. Angel Pons has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84633?usp=email ) Change subject: ec/starlabs/merlin: Add support for setting the charging speed ...................................................................... Patch Set 14: Code-Review+1 (3 comments) File src/ec/starlabs/merlin/Kconfig: https://review.coreboot.org/c/coreboot/+/84633/comment/80079c41_a3133d5e?us… : PS14, Line 69: EC_STARLABS_ITE Commit message says Merlin File src/ec/starlabs/merlin/ite.c: https://review.coreboot.org/c/coreboot/+/84633/comment/cba766fb_24181a86?us… : PS14, Line 251: 0.C Typo? `0.5C` Also, what are the units? https://review.coreboot.org/c/coreboot/+/84633/comment/5da8a0fc_5e31f3dc?us… : PS14, Line 263: 0 If I remember how the code works, this will fallback to `SPEED_1_0C` -- To view, visit https://review.coreboot.org/c/coreboot/+/84633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46faa540530c5bd7f5473021561380213158152e Gerrit-Change-Number: 84633 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 14:55:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
by Anand Vaikar (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85865?usp=email to look at the new patch set (#2). Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config ...................................................................... soc/amd/cezanne: Disable I2S internal clock based on mainboard config Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Gerrit-Change-Number: 85865 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Add support for setting the charging speed
by Sean Rhodes (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Angel Pons, Maxim Polyakov, Maximilian Brune, Paul Menzel. Hello Angel Pons, Maxim Polyakov, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84633?usp=email to look at the new patch set (#14). Change subject: ec/starlabs/merlin: Add support for setting the charging speed ...................................................................... ec/starlabs/merlin: Add support for setting the charging speed Allow boards that use the merlin EC to configure the charging speed, as all versions of the merlin EC support this. All coreboot does it write a value to the EC RAM and the EC will handle the rest. Change-Id: I46faa540530c5bd7f5473021561380213158152e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starfighter/Kconfig M src/mainboard/starlabs/starfighter/cmos.default M src/mainboard/starlabs/starfighter/cmos.layout M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout 18 files changed, 63 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84633/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46faa540530c5bd7f5473021561380213158152e Gerrit-Change-Number: 84633 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
by Anand Vaikar (Code Review) 06 Jan '25

06 Jan '25

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85865?usp=email ) Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config ...................................................................... soc/amd/cezanne: Disable I2S internal clock based on mainboard config Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/1 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index a8b7f22..2204b66 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -108,6 +108,8 @@ uint8_t tx_eq_post; uint8_t tx_vboost_lvl; } edp_tuningset; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index b9f529d..39b1694 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -83,8 +83,17 @@ static void fch_clk_output_48Mhz(void) { uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); - /* Enable BP_X48M0 Clock Output */ - ctrl |= BP_X48M0_OUTPUT_EN; + const struct soc_amd_cezanne_config *cfg; + cfg = config_of_soc(); + + /*Master clock is dsabled as the clock is given externally*/ + /* If used external clock source for I2S, disable the internal clock output */ + if (cfg->acp_i2s_use_external_48mhz_osc && + cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM) + ctrl &= ~BP_X48M0_OUTPUT_EN; + else + ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/85865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Gerrit-Change-Number: 85865 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com>

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