coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Jakub Czapiga, Jędrzej Ciupis, Matt DeVillier. Subrata Banik has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email ) Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/84359/comment/1c2a117c_d08bc635?us… : PS1, Line 39: select SOC_INTEL_CRASHLOG > I also don't know why we'd want to move it to the SoC vs the mainboard ideally MAINBOARD_HAS_CHROMEOS and CHROMEOS seem to be the same thing. I get how you plan to work around it by moving SOC_INTEL_CRASHLOG under the CHROMEOS config, since we don't select CHROMEOS from the main board kconfig in upsream. we select the below config from our .config. ``` # Chrome OS CONFIG_CHROMEOS=y ``` Although I don't see any problem w/ CB:84365 cl but I felt this cl is a W/A to the problem that you faced while booting windows/linux on jsl Chromebook. -- To view, visit https://review.coreboot.org/c/coreboot/+/84359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b Gerrit-Change-Number: 84359 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 15 Sep 2024 17:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Enable CRASHLOG for Chrome OS
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Matt DeVillier, Nick Vaccaro, Rishika Raj. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84365?usp=email ) Change subject: soc/intel/alderlake: Enable CRASHLOG for Chrome OS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/84365/comment/c178528a_4ecddeb9?us… : PS1, Line 87: MAINBOARD_HAS_CHROMEOS > while this is consistent with the previous behavior, I'm not sure why you want to move it to the SoC code, rather than select it in the mainboard(s) only for ChromeOS There are three main reasons to move Crashlog into the System-on-a-Chip (SoC) codebase: 1. Crashlog is a SoC feature, so it makes sense for the control knobs to stay within the SoC code. If a board doesn't want to use Crashlog, it can simply unsubscribe from it. 2. Using the SoC Kconfig allows us to support a wider range of boards without requiring each baseboard or variant to select the Crashlog Kconfig. For example, multiple vendors are making boards for Alder Lake (ADL), and asking each mainboard to select Crashlog features would lead to unnecessary duplication. 3. Maintaining consistent behavior with the latest SoCs MTL and PTL is important. Intel recommends that we enable Crashlog by default. -- To view, visit https://review.coreboot.org/c/coreboot/+/84365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd Gerrit-Change-Number: 84365 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 15 Sep 2024 17:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: Updating MESSAGE and RESOPONSE address for SMU Mail box for STX
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84384?usp=email ) Change subject: Updating MESSAGE and RESOPONSE address for SMU Mail box for STX ...................................................................... Updating MESSAGE and RESOPONSE address for SMU Mail box for STX Signed-off-by: Avinash Munduru <AvinashMunduru(a)amd.com> Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778 Tested-by: Avinash Munduru <Avinash.Munduru(a)amd.com> Reviewed-by: Anand Vaikar <Anand.Vaikar(a)amd.com> --- M src/soc/amd/glinda/include/soc/smu.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/84384/1 diff --git a/src/soc/amd/glinda/include/soc/smu.h b/src/soc/amd/glinda/include/soc/smu.h index 32d5856..7916774 100644 --- a/src/soc/amd/glinda/include/soc/smu.h +++ b/src/soc/amd/glinda/include/soc/smu.h @@ -6,8 +6,8 @@ #define AMD_GLINDA_SMU_H /* SMU mailbox register offsets in SMN */ -#define SMN_SMU_MESG_ID 0x3b10528 -#define SMN_SMU_MESG_RESP 0x3b10578 +#define SMN_SMU_MESG_ID 0x3b10928 +#define SMN_SMU_MESG_RESP 0x3b10978 #define SMN_SMU_MESG_ARGS_BASE 0x3b10998 #define SMU_NUM_ARGS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778 Gerrit-Change-Number: 84384 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: soc/amd/glinda/include/soc/smi.h: Update for glinda
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84383?usp=email ) Change subject: soc/amd/glinda/include/soc/smi.h: Update for glinda ...................................................................... soc/amd/glinda/include/soc/smi.h: Update for glinda It aligns the names in the datasheet with the one in the code. It also removes and adds some. Resource: Document 57254 Chapter 15.3.5 TODO it may very well be that I don't have the full truth, because most of these register just have a different name and some of these names like ESPI seem more recent that for example LPC. Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/smi.h 1 file changed, 34 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/84383/1 diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h index 3bde93f..850a237 100644 --- a/src/soc/amd/glinda/include/soc/smi.h +++ b/src/soc/amd/glinda/include/soc/smi.h @@ -25,13 +25,13 @@ #define SMITYPE_G_GENINT1_L 0 #define SMITYPE_G_GENINT2_L 1 #define SMITYPE_G_AGPIO3 2 -#define SMITYPE_G_ESPI_ALERT_L 3 +#define SMITYPE_G_LPC_PME_L 3 #define SMITYPE_G_AGPIO4 4 -#define SMITYPE_G_BLINK 5 +#define SMITYPE_G_LPC_PD_L 5 #define SMITYPE_G_SPKR 6 #define SMITYPE_G_AGPIO5 7 #define SMITYPE_G_WAKE_L 8 -#define SMITYPE_G_SPI_TPM_CS_L 9 +#define SMITYPE_G_LPC_SMI_L 9 #define SMITYPE_G_AGPIO6 10 #define SMITYPE_G_AGPIO7 11 #define SMITYPE_G_USBOC0_L 12 @@ -39,7 +39,7 @@ #define SMITYPE_G_USBOC2_L 14 #define SMITYPE_G_USBOC3_L 15 #define SMITYPE_G_AGPIO23 16 -#define SMITYPE_G_AGPIO32 17 +#define SMITYPE_G_ESPI_RESET_L 17 #define SMITYPE_G_FANIN0 18 #define SMITYPE_G_SYSRESET_L 19 #define SMITYPE_G_AGPIO40 20 @@ -49,13 +49,13 @@ #define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ | (1 << SMITYPE_G_GENINT2_L) \ | (1 << SMITYPE_G_AGPIO3) \ - | (1 << SMITYPE_G_ESPI_ALERT_L) \ + | (1 << SMITYPE_G_LPC_PME_L) \ | (1 << SMITYPE_G_AGPIO4) \ - | (1 << SMITYPE_G_BLINK) \ + | (1 << SMITYPE_G_LPC_PD_L) \ | (1 << SMITYPE_G_SPKR) \ | (1 << SMITYPE_G_AGPIO5) \ | (1 << SMITYPE_G_WAKE_L) \ - | (1 << SMITYPE_G_SPI_TPM_CS_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ | (1 << SMITYPE_G_AGPIO6) \ | (1 << SMITYPE_G_AGPIO7) \ | (1 << SMITYPE_G_USBOC0_L) \ @@ -63,7 +63,7 @@ | (1 << SMITYPE_G_USBOC2_L) \ | (1 << SMITYPE_G_USBOC3_L) \ | (1 << SMITYPE_G_AGPIO23) \ - | (1 << SMITYPE_G_AGPIO32) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ | (1 << SMITYPE_G_FANIN0) \ | (1 << SMITYPE_G_SYSRESET_L) \ | (1 << SMITYPE_G_AGPIO40) \ @@ -72,22 +72,26 @@ | (1 << SMITYPE_G_AGPIO8)) #define SMITYPE_MP2_WAKE 24 #define SMITYPE_MP2_GPIO0 25 -#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_SYS_EVT_B 26 #define SMITYPE_ESPI_WAKE_PME 27 #define SMITYPE_MP2_GPIO1 28 #define SMITYPE_GPP_PME 29 #define SMITYPE_NB_GPP_HOT_PLUG 30 /* 31 Reserved */ -#define SMITYPE_WAKE_L2 32 -#define SMITYPE_PSP 33 -/* 34,35 Reserved */ +#define SMITYPE_WAKE_L 32 +#define SMITYPE_FAKE_0 33 +#define SMITYPE_PSP SMITYPE_FAKE_0 +#define SMITYPE_FAKE_1 34 +#define SMITYPE_FAKE_2 35 #define SMITYPE_ESPI_SCI_B 36 -#define SMITYPE_CIO_FCH_PME_S5_0 37 -#define SMITYPE_CIO_FCH_PME_S5_1 38 -#define SMITYPE_AZPME 39 -#define SMITYPE_GPIO_CTL 41 -#define SMITYPE_XHC2_PME 42 -#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_USB4_0_PME 37 +#define SMITYPE_USB4_1_PME 38 +#define SMITYPE_AZ_WAKE 39 +#define SMITYPE_SCI_40 40 +#define SMITYPE_GPIO_INTR 41 +#define SMITYPE_USBADP_USB3_DRD_0_1 42 +#define SMITYPE_XHC2_PME SMITYPE_USBADP_USB3_DRD_0_1 +#define SMITYPE_ALT_MM_TIMER_ALARM 43 #define SMITYPE_FAN_THERMAL 44 #define SMITYPE_ASF_MASTER_SLAVE 45 #define SMITYPE_I2S_WAKE 46 @@ -98,28 +102,28 @@ #define SMITYPE_PWRBUTTON_UP 51 #define SMITYPE_PROCHOT 52 #define SMITYPE_APU_HW 53 -#define SMITYPE_NB_SCI 54 -#define SMITYPE_RAS_SERR 55 +#define SMITYPE_APU_SCI 54 +#define SMITYPE_INTERNAL_SERR 55 #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-60 Reserved */ -#define SMITYPE_XHC3_PME 61 -#define SMITYPE_XHC4_PME 62 +#define SMITYPE_DSM_TRIGGER_0 59 +#define SMITYPE_DSM_TRIGGER_1 60 +#define SMITYPE_USB_XHC3_PME_3 61 +#define SMITYPE_USB_XHC3_PME_4 62 +#define SMITYPE_XHC3_PME SMITYPE_USB_XHC3_PME_3 +#define SMITYPE_XHC4_PME SMITYPE_USB_XHC3_PME_4 #define SMITYPE_CUR_TEMP_STATUS_5 63 #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -/* 67 Reserved */ -#define SMITYPE_NB_GPP_PME_PULSE 68 -#define SMITYPE_NB_GPP_HP_PULSE 69 -/* 71 Reserved */ +/* 67-71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 #define SMITYPE_PWRBUTTON_DOWN 74 #define SMITYPE_SMI_CMD_PORT 75 #define SMITYPE_USB_SMI 76 -#define SMITYPE_SERIRQ 77 +#define SMITYPE_SERIAL_IRQ 77 #define SMITYPE_SMBUS0_INTR 78 /* 79-80 Reserved */ #define SMITYPE_INTRUDER 81 @@ -135,7 +139,6 @@ #define SMITYPE_SHORT_TIMER 142 #define SMITYPE_LONG_TIMER 143 #define SMITYPE_AB_SMI 144 -#define SMITYPE_ANY_RESET 145 #define SMITYPE_ESPI_SMI 146 /* 147 Reserved */ #define SMITYPE_IOTRAP0 148 @@ -168,7 +171,8 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) +# define SMITRIG0_FAKESTS0 (1 << 25) +# define SMITRIG0_PSP SMITRIG0_FAKESTS0 # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) -- To view, visit https://review.coreboot.org/c/coreboot/+/84383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Gerrit-Change-Number: 84383 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/amd/glinda: Update I2C for glinda
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Update I2C for glinda ...................................................................... soc/amd/glinda: Update I2C for glinda I24 and I2C5 don't exist. Reference: Document 57254 Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/glinda/include/soc/aoac_defs.h M src/soc/amd/glinda/include/soc/i2c.h M src/soc/amd/glinda/include/soc/smi.h 5 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/1 diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 2218ce3..8c58f5b 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -65,7 +65,6 @@ { PIRQ_I2C3, "I2C3" }, { PIRQ_UART0, "UART0" }, { PIRQ_UART1, "UART1" }, - { PIRQ_I2C4, "I2C4" }, { PIRQ_UART4, "UART4" }, { PIRQ_UART2, "UART2" }, { PIRQ_UART3, "UART3" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index c7ff65b..ebe1d2c 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -54,7 +54,6 @@ #define PIRQ_I2C3 0x73 /* I2C3 */ #define PIRQ_UART0 0x74 /* UART0 */ #define PIRQ_UART1 0x75 /* UART1 */ -#define PIRQ_I2C4 0x76 /* I2C4 */ #define PIRQ_UART4 0x77 /* UART4 */ #define PIRQ_UART2 0x78 /* UART2 */ #define PIRQ_UART3 0x79 /* UART3 */ diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h index b923ab3..98fb4ce 100644 --- a/src/soc/amd/glinda/include/soc/aoac_defs.h +++ b/src/soc/amd/glinda/include/soc/aoac_defs.h @@ -11,8 +11,6 @@ #define FCH_AOAC_DEV_I2C1 6 #define FCH_AOAC_DEV_I2C2 7 #define FCH_AOAC_DEV_I2C3 8 -#define FCH_AOAC_DEV_I2C4 9 -#define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART2 16 diff --git a/src/soc/amd/glinda/include/soc/i2c.h b/src/soc/amd/glinda/include/soc/i2c.h index f942c3b..05c6350 100644 --- a/src/soc/amd/glinda/include/soc/i2c.h +++ b/src/soc/amd/glinda/include/soc/i2c.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_I2C_H #define AMD_GLINDA_I2C_H diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h index 611840c..3bde93f 100644 --- a/src/soc/amd/glinda/include/soc/smi.h +++ b/src/soc/amd/glinda/include/soc/smi.h @@ -85,7 +85,6 @@ #define SMITYPE_CIO_FCH_PME_S5_0 37 #define SMITYPE_CIO_FCH_PME_S5_1 38 #define SMITYPE_AZPME 39 -#define SMITYPE_USB_PD_I2C4 40 #define SMITYPE_GPIO_CTL 41 #define SMITYPE_XHC2_PME 42 #define SMITYPE_ALT_HPET_ALARM 43 @@ -114,7 +113,6 @@ /* 67 Reserved */ #define SMITYPE_NB_GPP_PME_PULSE 68 #define SMITYPE_NB_GPP_HP_PULSE 69 -#define SMITYPE_USB_PD_I2C4_INTR2 70 /* 71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update SCI mapping
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84381?usp=email ) Change subject: soc/amd/glinda: Update SCI mapping ...................................................................... soc/amd/glinda: Update SCI mapping source: PPR #57254 Rev 1.71 Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/pci_devs.h M src/soc/amd/glinda/xhci.c 2 files changed, 24 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/84381/1 diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index a37d3ee..0ef6864 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -66,7 +66,7 @@ #define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) #define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 +#define XHCI0_FUNC 0 #define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) #define XHCI1_DEV 0x0 @@ -89,9 +89,14 @@ #define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) -#define XHCI2_DEV 0x0 -#define XHCI2_FUNC 0 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + /* SMBUS */ #define SMBUS_DEV 0x14 diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index 74e8816..70a0d84 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -25,7 +25,13 @@ .level = SMI_SCI_EDG }, { - .scimap = SMITYPE_XHC2_PME, + .scimap = SMITYPE_XHC3_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, .gpe = GEVENT_31, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG @@ -41,18 +47,20 @@ return CB_ERR_ARG; if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { - if (dev->path.pci.devfn == XHCI0_DEVFN) { - *gpe = xhci_sci_sources[0].gpe; - return CB_SUCCESS; - } else if (dev->path.pci.devfn == XHCI1_DEVFN) { + if (dev->path.pci.devfn == XHCI1_DEVFN) { *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { - if (dev->path.pci.devfn == XHCI2_DEVFN - && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { + if (dev->path.pci.devfn == XHCI0_DEVFN) { + *gpe = xhci_sci_sources[0].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { *gpe = xhci_sci_sources[2].gpe; return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Gerrit-Change-Number: 84381 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: [WIP] soc/amd/glinda/.../iomap.h: Remove update for glinda TODO
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email ) Change subject: [WIP] soc/amd/glinda/.../iomap.h: Remove update for glinda TODO ...................................................................... [WIP] soc/amd/glinda/.../iomap.h: Remove update for glinda TODO TODO Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/iomap.h 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/84380/1 diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index 029dd1c..9678e9d 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_IOMAP_H #define AMD_GLINDA_IOMAP_H @@ -13,11 +11,11 @@ /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ -#define GNB_IO_APIC_ADDR 0xfec01000 -#define SPI_BASE_ADDRESS 0xfec10000 +#define GNB_IO_APIC_ADDR 0xfec01000 //TODO +#define SPI_BASE_ADDRESS 0xfec10000 //TODO /* FCH AL2AHB Registers */ -#define ALINK_AHB_ADDRESS 0xfedc0000 +#define ALINK_AHB_ADDRESS 0xfedc0000 //TODO Its not in the table anymore (maybe it moved in the PPR) #define APU_I2C0_BASE 0xfedc2000 #define APU_I2C1_BASE 0xfedc3000 @@ -32,13 +30,13 @@ #define APU_DMAC3_BASE 0xfedcd000 #define APU_UART2_BASE 0xfedce000 #define APU_UART3_BASE 0xfedcf000 -#define APU_DMAC4_BASE 0xfedd0000 -#define APU_UART4_BASE 0xfedd1000 +#define APU_UART4_BASE 0xfedd1000 //TODO not in the table but used on actual schematics (does it exist or not?) #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) +//TODO /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) -- To view, visit https://review.coreboot.org/c/coreboot/+/84380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Gerrit-Change-Number: 84380 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: Update UPD for system configuration, Fast and Slow PPT to set 45W TDP
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84379?usp=email ) Change subject: Update UPD for system configuration, Fast and Slow PPT to set 45W TDP ...................................................................... Update UPD for system configuration, Fast and Slow PPT to set 45W TDP Signed-off-by: Anand Vaikar <Anand.Vaikar(a)amd.com> Change-Id: Ib73c3a1270c7b1d490fd14c4e60f7aa9be93429b Reviewed-by: Avinash Munduru <Avinash.Munduru(a)amd.com> --- M src/soc/amd/glinda/fsp_m_params.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/84379/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib73c3a1270c7b1d490fd14c4e60f7aa9be93429b Gerrit-Change-Number: 84379 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update UPD for system configuration, Fast and Slow PPT to set 45W TDP
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84379?usp=email ) Change subject: Update UPD for system configuration, Fast and Slow PPT to set 45W TDP ...................................................................... Update UPD for system configuration, Fast and Slow PPT to set 45W TDP Signed-off-by: Anand Vaikar <Anand.Vaikar(a)amd.com> Change-Id: Ib73c3a1270c7b1d490fd14c4e60f7aa9be93429b Reviewed-on: https://gerrit-git.amd.com/c/embedded/ec/coreboot/+/1031235 Reviewed-by: Avinash Munduru <Avinash.Munduru(a)amd.com> --- M src/soc/amd/glinda/fsp_m_params.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/84379/1 diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index 843a2d9..1142a09 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -115,6 +115,8 @@ mcfg->sustained_power_limit = config->sustained_power_limit_mW; mcfg->fast_ppt_limit = config->fast_ppt_limit_mW; mcfg->slow_ppt_limit = config->slow_ppt_limit_mW; + mcfg->fast_ppt_limit = 45 * 1000; + mcfg->slow_ppt_limit = 45 * 1000; mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s; mcfg->thermctl_limit = config->thermctl_limit_degreeC; @@ -123,7 +125,7 @@ /* 0 is default */ mcfg->system_configuration = config->system_configuration; - + mcfg->system_configuration = 4; //TDP to 45W /* when cppc_ctrl is 0 the other values won't be used */ mcfg->cppc_ctrl = config->cppc_ctrl; mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; -- To view, visit https://review.coreboot.org/c/coreboot/+/84379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib73c3a1270c7b1d490fd14c4e60f7aa9be93429b Gerrit-Change-Number: 84379 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... soc/amd/glinda: Update gpp bridge naming scheme This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/soc/amd/glinda/chipset.cb 3 files changed, 16 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84378/1 diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index dfcd176..9fa1918 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -158,9 +158,11 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # NVME SSD0 + device ref gpp_bridge_2_2 on end # SD + device ref gpp_bridge_2_3 on end # WLAN + device ref gpp_bridge_2_4 on end # GBE + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 025680e..c134915 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 6e23c2d..f328797 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -14,13 +14,15 @@ device pci 01.2 alias usb4_pcie_bridge_1 off end device pci 01.3 alias usb4_pcie_bridge_2 off end + # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy device function, do not disable device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit September 2024