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Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
......................................................................
mb/google/dedede/var/beadrix: Add LTE only daughterboard support
Add FW_CONFIG for no port LTE skus.
BUG=b:364431483
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69
Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/beadrix/gpio.c
M src/mainboard/google/dedede/variants/beadrix/overridetree.cb
2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84232/2
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Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/dedede/variants/beadrix/gpio.c:
https://review.coreboot.org/c/coreboot/+/84232/comment/7685262e_655ba151?us… :
PS1, Line 125: if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) &&
> `Statements should start on a tabstop`
Please fix.
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Change subject: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84254/comment/a9f8c040_0af39ac0?us… :
PS2, Line 8:
> Please mention your source.
Done
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Change subject: soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84399/comment/b5ae8120_bd332e13?us… :
PS3, Line 7: Fix double setting of 'PchPwrOptEnable'
> I misunderstood the summary. Maybe something like: […]
Done
https://review.coreboot.org/c/coreboot/+/84399/comment/4e0df6df_4f5436fb?us… :
PS3, Line 9: If real-time tuning was enabled, 'PchPwrOptEnable' was set two times.
> … with different values.
Done
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Hello Lean Sheng Tan, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning
......................................................................
soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times
with different values. This patch fixes the issue.
BUG=none
TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84399/4
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Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/apollolake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84356/comment/7c8b33ea_8612faa6?us… :
PS6, Line 400: default 5
> I disagree. The previous implementation was unmanageable.
you can only blame the FSP spec for that. look at FSP spec < 2.4 (if you think it is unmanageable)
> It was duplicating information, hard-coding values and adding unnecessary complexity. What is wrong in having a simple number as documented in the Kconfig instead of creating many Kconfig ?
The previous implementation was following "FSP EAS v2.0 section 11.2.2 - OEM Status Code".
details: https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/edk…
looks like with FSP2.4 specification, Intel has added support for 64-bit hence, updated the hardcoded macro as https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Include/FspEas/F…
The issue is that we need to keep things consistent between the old and new spec FSPs. In the older spec, the values `3` and `5` don't mean anything on their own. They're always the full 32-bit value, like `0x40000003` or `0x40000005`. The latest spec FSP proposes encoding a reset type as `3` or `5` inside a wrapper. This makes sense for an EDK2-based bootloader, but not for us. We need to figure out what the reset type is by looking at the macro, not just the number.
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Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84409?usp=email )
Change subject: mb/google/fatcat: Add HDA verb tables
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84409/comment/94639bc8_c6359e46?us… :
PS1, Line 8:
Where did you get these from, or from what source did you create the file?
https://review.coreboot.org/c/coreboot/+/84409/comment/fb97c18d_85f7320d?us… :
PS1, Line 10: TEST=Boot on google fatcat board
Tested how?
File src/mainboard/google/fatcat/variants/fatcat/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/84409/comment/7b2e5626_5f29817b?us… :
PS1, Line 79: /* Widget node 0x20 - 6
: * Silence data mode Threshold (-90dB) */
The recommended concise style is:
/* …
… */
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Change subject: soc/amd/glinda/.../iomap.h: Update for glinda
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84380/comment/8f8ff08d_e0229c1d?us… :
PS2, Line 8:
Please elaborate.
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