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[L] Change in coreboot[main]: inteltool: elkhartlake: keep the same names as coreboot code uses
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Pratikkumar V Prajapati. Hello Pratikkumar V Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84190?usp=email to look at the new patch set (#2). Change subject: inteltool: elkhartlake: keep the same names as coreboot code uses ...................................................................... inteltool: elkhartlake: keep the same names as coreboot code uses coreboot doesn't have a leading zero in gpio < 10. E.g. G00 -> G0 Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 --- M util/inteltool/gpio_names/elkhartlake.h 1 file changed, 131 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/84190/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Gerrit-Change-Number: 84190 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[L] Change in coreboot[main]: intelp2m: add support for elkhartlake
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Maxim. Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) Change subject: intelp2m: add support for elkhartlake ...................................................................... intelp2m: add support for elkhartlake Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 --- M util/intelp2m/config/config.go M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/ehl/macro.go A util/intelp2m/platforms/ehl/template.go 5 files changed, 340 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84191/1 diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go index 5578a05..b388b98 100644 --- a/util/intelp2m/config/config.go +++ b/util/intelp2m/config/config.go @@ -33,6 +33,7 @@ JasperType uint8 = 6 MeteorType uint8 = 7 EmmitsburgType uint8 = 8 + ElkhartType uint8 = 9 ) var key uint8 = SunriseType @@ -41,6 +42,7 @@ "snr": SunriseType, "lbg": LewisburgType, "apl": ApolloType, + "ehl": ElkhartType, "cnl": CannonType, "tgl": TigerType, "adl": AlderType, @@ -85,6 +87,9 @@ func IsPlatformEmmitsburg() bool { return IsPlatform(EmmitsburgType) } +func IsPlatformElkhartLake() bool { + return IsPlatform(ElkhartType) +} var InputRegDumpFile *os.File = nil var OutputGenFile *os.File = nil diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index 38a3b5fc..03adfe4 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -68,6 +68,7 @@ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ + "\tehl - Elkhart Lake SoC\n"+ "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n"+ "\ttgl - TigerLake-H SoC\n"+ "\tadl - AlderLake PCH\n"+ diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index fd3191d..394ebc0 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -10,6 +10,7 @@ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/ehl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" @@ -150,6 +151,7 @@ InheritanceTemplate : snr.PlatformSpecific{}, }, config.ApolloType : apl.PlatformSpecific{}, + config.ElkhartType : ehl.PlatformSpecific{}, config.CannonType : cnl.PlatformSpecific{ InheritanceTemplate : snr.PlatformSpecific{}, }, diff --git a/util/intelp2m/platforms/ehl/macro.go b/util/intelp2m/platforms/ehl/macro.go new file mode 100644 index 0000000..7e1d66e --- /dev/null +++ b/util/intelp2m/platforms/ehl/macro.go @@ -0,0 +1,310 @@ +package ehl + +import ( + "fmt" + "strconv" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/fields" +) + +const ( + PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0xf << 14) | 0xfc + PAD_CFG_DW1_RO_FIELDS = 0xfffc00ff +) + +const ( + PAD_CFG_DW0 = common.PAD_CFG_DW0 + PAD_CFG_DW1 = common.PAD_CFG_DW1 + MAX_DW_NUM = common.MAX_DW_NUM +) + +const ( + PULL_NONE = 0x0 // 0 000: none + PULL_DN_1K = 0x1 // 0 001: 1k wpd + PULL_DN_5K = 0x2 // 0 010: 5k wpd + PULL_DN_20K = 0x4 // 0 100: 20k wpd + PULL_UP_1K_5K_20K = 0x8 // 1 000: 20k & 5k & 1k wpu + PULL_UP_1K = 0x9 // 1 001: 1k wpu + PULL_UP_5K = 0xa // 1 010: 5k wpu + PULL_UP_1K_5K = 0xb // 1 011: 1k & 5k wpu + PULL_UP_20K = 0xc // 1 100: 20k wpu + PULL_UP_1K_20K = 0xd // 1 101: 20k & 1k wpu + PULL_UP_5K_20K = 0xe // 1 110: 20k & 5k wpu + PULL_NATIVE = 0xf // 1 111: (optional) Native controller selected by Pad Mode +) + +type PlatformSpecific struct {} + +// RemmapRstSrc - remmap Pad Reset Source Config +// remmap is not required because it is the same as common. +func (PlatformSpecific) RemmapRstSrc() {} + +// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument +// return: macro +func (PlatformSpecific) Pull() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + var pull = map[uint8]string{ + PULL_NONE: "NONE", + PULL_DN_1K: "DN_1K", + PULL_DN_5K: "DN_5K", + PULL_DN_20K: "DN_20K", + PULL_UP_1K_5K_20K: "UP_1K_5K_20K", + PULL_UP_1K: "UP_1K", + PULL_UP_5K: "UP_5K", + PULL_UP_1K_5K: "UP_1K_5K", + PULL_UP_20K: "UP_20K", + PULL_UP_1K_20K: "UP_1K_20K", + PULL_UP_5K_20K: "UP_5K_20K", + PULL_NATIVE: "NATIVE", + } + terminationFieldValue := dw1.GetTermination() + str, valid := pull[terminationFieldValue] + if !valid { + str = strconv.Itoa(int(terminationFieldValue)) + fmt.Println("Error", macro.PadIdGet(), " invalid TERM value = ", str) + } + macro.Separator().Add(str) +} + +// Generate macro to cause peripheral IRQ when configured in GPIO input mode +func ioApicRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + if dw0.GetGPIOInputRouteIOxAPIC() == 0 { + return false + } + macro.Add("_APIC") + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // e.g. H1_PCH_INT_ODL + // PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + macro.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else { + // PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + } + macro.Add("),") + return true +} + +// Generate macro to cause NMI when configured in GPIO input mode +func nmiRoute() bool { + macro := common.GetMacro() + if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 { + return false + } + // e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause SCI when configured in GPIO input mode +func sciRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSCI() == 0 { + return false + } + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD), + macro.Add("_SCI_IOS") + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 { + // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), + macro.Add("_ACPI_SCI").Add("(").Id().Pull().Rstsrc().Invert() + } else { + // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert() + } + macro.Add("),") + return true +} + +// Generate macro to cause SMI when configured in GPIO input mode +func smiRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + if dw0.GetGPIOInputRouteSMI() == 0 { + return false + } + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), + macro.Add("_SMI_IOS") + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 { + // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), + macro.Add("_ACPI_SMI").Add("(").Id().Pull().Rstsrc().Invert() + } else { + // e.g. PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert() + } + macro.Add("),") + return true +} + +// Generate macro for GPI port +func (PlatformSpecific) GpiMacroAdd() { + macro := common.GetMacro() + var ids []string + macro.Set("PAD_CFG_GPI") + for routeid, isRoute := range map[string]func() (bool) { + "IOAPIC": ioApicRoute, + "SCI": sciRoute, + "SMI": smiRoute, + "NMI": nmiRoute, + } { + if isRoute() { + ids = append(ids, routeid) + } + } + + switch argc := len(ids); argc { + case 0: + dw1 := macro.Register(PAD_CFG_DW1) + isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0 + isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0 + if isIOStandbyStateUsed && !isIOStandbyTerminationUsed { + macro.Add("_TRIG_IOSSTATE_OWN(") + // PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) + macro.Id().Pull().Rstsrc().Trig().IOSstate().Own().Add("),") + } else if isIOStandbyTerminationUsed { + macro.Add("_TRIG_IOS_OWN(") + // PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) + macro.Id().Pull().Rstsrc().Trig().IOSstate().IOTerm().Own().Add("),") + } else { + // PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) + macro.Add("_TRIG_OWN(").Id().Pull().Rstsrc().Trig().Own().Add("),") + } + case 1: + // GPI with IRQ route + if config.AreFieldsIgnored() { + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + case 2: + // PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) + macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert() + macro.Add(", " + ids[0] + ", " + ids[1] + "),") + if config.AreFieldsIgnored() { + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + default: + // Clear the control mask so that the check fails and "Advanced" macro is + // generated + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + } +} + + +// Adds PAD_CFG_GPO macro with arguments +func (PlatformSpecific) GpoMacroAdd() { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + term := dw1.GetTermination() + + macro.Set("PAD_CFG") + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + // PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) + macro.Add("_GPO_IOSSTATE_IOSTERM(").Id().Val().Rstsrc().Pull().IOSstate().IOTerm() + } else { + if term != 0 { + // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + // PAD_CFG_TERM_GPO(pad, val, pull, rst) + macro.Add("_TERM") + } + macro.Add("_GPO(").Id().Val() + if term != 0 { + macro.Pull() + } + macro.Rstsrc() + } + macro.Add("),") + + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + // ignore if trig = OFF is not set + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } +} + +// Adds PAD_CFG_NF macro with arguments +func (PlatformSpecific) NativeFunctionMacroAdd() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0 + isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0 + + macro.Set("PAD_CFG_NF") + if !isIOStandbyTerminationUsed && isIOStandbyStateUsed { + if dw1.GetIOStandbyState() == common.StandbyIgnore { + // PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + macro.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn() + } else { + // PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), + macro.Add("_IOSSTATE(").Id().Pull().Rstsrc().Padfn().IOSstate() + } + } else if isIOStandbyTerminationUsed { + // PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), + macro.Add("_IOSSTATE_IOSTERM(").Id().Pull().Rstsrc().Padfn().IOSstate().IOTerm() + } else { + // e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1) + macro.Add("(").Id().Pull().Rstsrc().Padfn() + } + macro.Add("),") + + if dw0 := macro.Register(PAD_CFG_DW0); dw0.GetGPIORxTxDisableStatus() != 0 { + // Since the bufbis parameter will be ignored for NF, we should clear + // the corresponding bits in the control mask. + dw0.CntrMaskFieldsClear(common.RxTxBufDisableMask) + } +} + +// Adds PAD_NC macro +func (PlatformSpecific) NoConnMacroAdd() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + + if dw1.GetIOStandbyState() == common.TxDRxE { + dw0 := macro.Register(PAD_CFG_DW0) + + // See comments in sunrise/macro.go : NoConnMacroAdd() + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } + if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) + } + + // PAD_NC(OSC_CLK_OUT_1, DN_20K) + macro.Set("PAD_NC").Add("(").Id().Pull().Add("),") + return + } + // PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), + macro.Set("PAD_CFG_GPIO_") + if macro.IsOwnershipDriver() { + // PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU), + macro.Add("DRIVER_") + } + macro.Add("HI_Z(").Id().Pull().Rstsrc().IOSstate().IOTerm().Add("),") +} + +// GenMacro - generate pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string { + macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet()) + // use platform-specific interface in Macro struct + macro.PadIdSet(id).SetPadOwnership(ownership) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS) + macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS) + return macro.Generate() +} diff --git a/util/intelp2m/platforms/ehl/template.go b/util/intelp2m/platforms/ehl/template.go new file mode 100644 index 0000000..3d4de85 --- /dev/null +++ b/util/intelp2m/platforms/ehl/template.go @@ -0,0 +1,22 @@ +package ehl + +import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + +// GroupNameExtract - This function extracts the group ID, if it exists in a row +// line : string from the configuration file +// return +// bool : true if the string contains a group identifier +// string : group identifier +func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { + // Not supported + return false, "" +} + +// KeywordCheck - This function is used to filter parsed lines of the configuration file and +// returns true if the keyword is contained in the line. +// line : string from the configuration file +func (PlatformSpecific) KeywordCheck(line string) bool { + isIncluded, _ := common.KeywordsCheck(line, + "GPP_", "GPD_", "GPIO_", "VGPIO_") + return isIncluded +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com>

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[L] Change in coreboot[main]: inteltool: keep the same names as coreboot code uses
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84190?usp=email ) Change subject: inteltool: keep the same names as coreboot code uses ...................................................................... inteltool: keep the same names as coreboot code uses coreboot doesn't have a leading zero in gpio < 10. E.g. G00 -> G0 Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 --- M util/inteltool/gpio_names/elkhartlake.h 1 file changed, 131 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/84190/1 diff --git a/util/inteltool/gpio_names/elkhartlake.h b/util/inteltool/gpio_names/elkhartlake.h index 75d65d3..43dc0f7 100644 --- a/util/inteltool/gpio_names/elkhartlake.h +++ b/util/inteltool/gpio_names/elkhartlake.h @@ -8,16 +8,16 @@ /* ----------------------------- Elkhart Lake ----------------------------- */ const char *const elkhartlake_pch_group_a_names[] = { - "GPP_A00", "PSE_GBE0_RGMII_TXD3", "n/a", - "GPP_A01", "PSE_GBE0_RGMII_TXD2", "n/a", - "GPP_A02", "PSE_GBE0_RGMII_TXD1", "n/a", - "GPP_A03", "PSE_GBE0_RGMII_TXD0", "n/a", - "GPP_A04", "PSE_GBE0_RGMII_TXCLK", "n/a", - "GPP_A05", "PSE_GBE0_RGMII_TXCTL", "n/a", - "GPP_A06", "PSE_GBE0_RGMII_RXCLK", "n/a", - "GPP_A07", "PSE_GBE0_RGMII_RXD3", "n/a", - "GPP_A08", "PSE_GBE0_RGMII_RXD2", "n/a", - "GPP_A09", "PSE_GBE0_RGMII_RXD1", "n/a", + "GPP_A0", "PSE_GBE0_RGMII_TXD3", "n/a", + "GPP_A1", "PSE_GBE0_RGMII_TXD2", "n/a", + "GPP_A2", "PSE_GBE0_RGMII_TXD1", "n/a", + "GPP_A3", "PSE_GBE0_RGMII_TXD0", "n/a", + "GPP_A4", "PSE_GBE0_RGMII_TXCLK", "n/a", + "GPP_A5", "PSE_GBE0_RGMII_TXCTL", "n/a", + "GPP_A6", "PSE_GBE0_RGMII_RXCLK", "n/a", + "GPP_A7", "PSE_GBE0_RGMII_RXD3", "n/a", + "GPP_A8", "PSE_GBE0_RGMII_RXD2", "n/a", + "GPP_A9", "PSE_GBE0_RGMII_RXD1", "n/a", "GPP_A10", "PSE_GBE0_RGMII_RXD0", "n/a", "GPP_A11", "PSE_GBE1_RGMII_TXD3", "n/a", "GPP_A12", "PSE_GBE1_RGMII_TXD2", "n/a", @@ -42,16 +42,16 @@ }; const char *const elkhartlake_pch_group_b_names[] = { - "GPP_B00" ,"PMC_CORE_VID0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_B01" ,"PMC_CORE_VID1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_B02" ,"PMC_VRALERT_N", "n/a", "n/a", "ESPI_ALERT2_N", "n/a", "n/a", "n/a", "PSE_TGPIO25", - "GPP_B03" ,"CPU_GP2", "n/a", "n/a", "ESPI_ALERT0_N", "n/a", "n/a", "n/a", "PSE_TGPIO26", - "GPP_B04" ,"CPU_GP3", "n/a", "n/a", "ESPI_ALERT1_N", "n/a", "n/a", "n/a", "PSE_TGPIO27", - "GPP_B05" ,"PSE_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", - "GPP_B06" ,"PSE_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", - "GPP_B07" ,"PSE_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", - "GPP_B08" ,"PSE_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", - "GPP_B09" ,"SIO_I2C5_SDA", "PSE_I2C2_SDA", "n/a", "ESPI_CS3_N", "n/a", "n/a", "n/a", "n/a", + "GPP_B0" ,"PMC_CORE_VID0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B1" ,"PMC_CORE_VID1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B2" ,"PMC_VRALERT_N", "n/a", "n/a", "ESPI_ALERT2_N", "n/a", "n/a", "n/a", "PSE_TGPIO25", + "GPP_B3" ,"CPU_GP2", "n/a", "n/a", "ESPI_ALERT0_N", "n/a", "n/a", "n/a", "PSE_TGPIO26", + "GPP_B4" ,"CPU_GP3", "n/a", "n/a", "ESPI_ALERT1_N", "n/a", "n/a", "n/a", "PSE_TGPIO27", + "GPP_B5" ,"PSE_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", + "GPP_B6" ,"PSE_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", + "GPP_B7" ,"PSE_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", + "GPP_B8" ,"PSE_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", + "GPP_B9" ,"SIO_I2C5_SDA", "PSE_I2C2_SDA", "n/a", "ESPI_CS3_N", "n/a", "n/a", "n/a", "n/a", "GPP_B10" ,"SIO_I2C5_SCL", "PSE_I2C2_SCL", "n/a", "ESPI_ALERT3_N", "n/a", "n/a", "n/a", "n/a", "GPP_B11" ,"PMC_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", "GPP_B12" ,"PMC_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -78,16 +78,16 @@ }; const char *const elkhartlake_pch_group_c_names[] = { - "GPP_C00", "SMB_CLK", "PSE_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO18", - "GPP_C01", "SMB_DATA", "PSE_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO19", - "GPP_C02", "PSE_PWM00", "SMB_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO29", - "GPP_C03", "PSE_GBE0_MDC", "n/a", "PSE_HSUART3_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", - "GPP_C04", "PSE_GBE0_MDIO", "n/a", "PSE_UART3_RTS_N", "PSE_HSUART3_DE", "n/a", "RSVD", "n/a", "n/a", - "GPP_C05", "PSE_PWM01", "n/a", "PSE_UART3_CTS_N", "n/a", "n/a", "SML_ALERT0_N", "n/a", "PSE_TGPIO30", - "GPP_C06", "PSE_GBE1_MDC", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_C07", "PSE_GBE1_MDIO", "n/a", "PSE_HSUART3_RE", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_C08", "PSE_TGPIO04", "DNX_FORCE_RELOAD", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_C09", "PSE_HSUART0_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_C0", "SMB_CLK", "PSE_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO18", + "GPP_C1", "SMB_DATA", "PSE_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO19", + "GPP_C2", "PSE_PWM00", "SMB_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO29", + "GPP_C3", "PSE_GBE0_MDC", "n/a", "PSE_HSUART3_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", + "GPP_C4", "PSE_GBE0_MDIO", "n/a", "PSE_UART3_RTS_N", "PSE_HSUART3_DE", "n/a", "RSVD", "n/a", "n/a", + "GPP_C5", "PSE_PWM01", "n/a", "PSE_UART3_CTS_N", "n/a", "n/a", "SML_ALERT0_N", "n/a", "PSE_TGPIO30", + "GPP_C6", "PSE_GBE1_MDC", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C7", "PSE_GBE1_MDIO", "n/a", "PSE_HSUART3_RE", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C8", "PSE_TGPIO04", "DNX_FORCE_RELOAD", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_C9", "PSE_HSUART0_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C10", "PSE_TGPIO05", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C11", "PSE_HSUART0_RE", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C12", "PSE_UART0_RXD", "n/a", "n/a", "SIO_UART1_RXD", "n/a", "n/a", "n/a", "n/a", @@ -112,16 +112,16 @@ }; const char *const elkhartlake_pch_group_d_names[] = { - "GPP_D00", "PSE_QEPA0", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "PSE_TGPIO32", - "GPP_D01", "PSE_QEPB0", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "PSE_TGPIO33", - "GPP_D02", "PSE_QEPI0", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "PSE_TGPIO34", - "GPP_D03", "PSE_PWM06", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO35", - "GPP_D04", "PSE_PWM02", "n/a", "RSVD", "PSE_SPI1_CS1_N", "n/a", "n/a", "n/a", "PSE_TGPIO36", - "GPP_D05", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D06", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D07", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D08", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D09", "PSE_SPI0_CS0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CS0_N", "PSE_TGPIO10", + "GPP_D0", "PSE_QEPA0", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "PSE_TGPIO32", + "GPP_D1", "PSE_QEPB0", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "PSE_TGPIO33", + "GPP_D2", "PSE_QEPI0", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "PSE_TGPIO34", + "GPP_D3", "PSE_PWM06", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO35", + "GPP_D4", "PSE_PWM02", "n/a", "RSVD", "PSE_SPI1_CS1_N", "n/a", "n/a", "n/a", "PSE_TGPIO36", + "GPP_D5", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D6", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D7", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D8", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D9", "PSE_SPI0_CS0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CS0_N", "PSE_TGPIO10", "GPP_D10", "PSE_SPI0_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CLK", "PSE_TGPIO11", "GPP_D11", "PSE_SPI0_MISO", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_MISO", "PSE_TGPIO12", "GPP_D12", "PSE_SPI0_MOSI", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_MOSI", "PSE_TGPIO13", @@ -143,17 +143,17 @@ }; const char *const elkhartlake_pch_group_gpd_names[] = { - "GPD_00", "PMC_BATLOW_N", - "GPD_01", "PMC_ACPRESENT", - "GPD_02", "RSVD", - "GPD_03", "PMC_PWRBTN_N", - "GPD_04", "PMC_SLP_S3_N", - "GPD_05", "PMC_SLP_S4_N", - "GPD_07", "RSVD", - "GPD_08", "PMC_SUSCLK", - "GPD_09", "RSVD", - "GPD_10", "PMC_SLP_S5_N", - "GPD_11", "RSVD", + "GPD0", "PMC_BATLOW_N", + "GPD1", "PMC_ACPRESENT", + "GPD2", "RSVD", + "GPD3", "PMC_PWRBTN_N", + "GPD4", "PMC_SLP_S3_N", + "GPD5", "PMC_SLP_S4_N", + "GPD7", "RSVD", + "GPD8", "PMC_SUSCLK", + "GPD9", "RSVD", + "GPD10", "PMC_SLP_S5_N", + "GPD11", "RSVD", "GPIO_RSVD_8", "n/a", "GPIO_RSVD_9", "n/a", "GPIO_RSVD_10", "n/a", @@ -169,16 +169,16 @@ }; const char *const elkhartlake_pch_group_e_names[] = { - "GPP_E00", "SATA_LED_N", "SATAXPCIE_0", "RSVD", "RSVD", "RSVD", "RSVD", "SATA_0_GP", "n/a", - "GPP_E01", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", - "GPP_E02", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", - "GPP_E03", "DDI1_HPD", "PNL_MISC_DDI1", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP0", "PSE_TGPIO15", - "GPP_E04", "SATA_0_DEVSLP", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM08", "PSE_TGPIO44", - "GPP_E05", "DDI1_DDC_SDA", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM09", "PSE_TGPIO17", - "GPP_E06", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM10", "PSE_TGPIO18", - "GPP_E07", "DDI1_DDC_SCL", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP1", "PSE_TGPIO16", - "GPP_E08", "n/a", "SATA_1_DEVSLP", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "PSE_TGPIO45", - "GPP_E09", "USB2_OC0_N", "n/a", "RSVD", "RSVD", "n/a", "RSVD", "n/a", "n/a", + "GPP_E0", "SATA_LED_N", "SATAXPCIE_0", "RSVD", "RSVD", "RSVD", "RSVD", "SATA_0_GP", "n/a", + "GPP_E1", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", + "GPP_E2", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", + "GPP_E3", "DDI1_HPD", "PNL_MISC_DDI1", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP0", "PSE_TGPIO15", + "GPP_E4", "SATA_0_DEVSLP", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM08", "PSE_TGPIO44", + "GPP_E5", "DDI1_DDC_SDA", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM09", "PSE_TGPIO17", + "GPP_E6", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM10", "PSE_TGPIO18", + "GPP_E7", "DDI1_DDC_SCL", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP1", "PSE_TGPIO16", + "GPP_E8", "n/a", "SATA_1_DEVSLP", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "PSE_TGPIO45", + "GPP_E9", "USB2_OC0_N", "n/a", "RSVD", "RSVD", "n/a", "RSVD", "n/a", "n/a", "GPP_E10", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD" , "n/a", "GPP_E11", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "n/a", "GPP_E12", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "n/a", @@ -203,16 +203,16 @@ }; const char *const elkhartlake_pch_group_f_names[] = { - "GPP_F00", "RSVD", "SIO_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F01", "RSVD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F02", "RSVD", "SIO_UART0_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F03", "RSVD", "SIO_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F04", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F05", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO14", - "GPP_F06", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO47", - "GPP_F07", "PSE_I2S1_SCLK", "n/a", "n/a", "n/a", "AVS_I2S4_SCLK", "n/a", "n/a", "PSE_TGPIO14", - "GPP_F08", "AVS_I2S_MCLK2", "n/a", "n/a", "PSE_TRACEDATA_0", "ISI_TRACEDATA_0", "n/a", "n/a", "PSE_TGPIO48", - "GPP_F09", "BOOT_PWR_EN", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F0", "RSVD", "SIO_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F1", "RSVD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F2", "RSVD", "SIO_UART0_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F3", "RSVD", "SIO_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F4", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F5", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO14", + "GPP_F6", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO47", + "GPP_F7", "PSE_I2S1_SCLK", "n/a", "n/a", "n/a", "AVS_I2S4_SCLK", "n/a", "n/a", "PSE_TGPIO14", + "GPP_F8", "AVS_I2S_MCLK2", "n/a", "n/a", "PSE_TRACEDATA_0", "ISI_TRACEDATA_0", "n/a", "n/a", "PSE_TGPIO48", + "GPP_F9", "BOOT_PWR_EN", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_F10", "PSE_I2S1_SFRM", "n/a", "n/a", "n/a", "AVS_I2S4_SFRM", "n/a", "n/a", "PSE_TGPIO15", "GPP_F11", "n/a", "n/a", "RSVD", "PSE_TRACECLK", "ISI_TRACECLK", "n/a", "n/a", "PSE_TGPIO49", "GPP_F12", "RSVD", "AVS_I2S4_TXD", "RSVD", "PSE_TRACESWO", "ISI_TRACESWO", "n/a", "n/a", "n/a", @@ -244,16 +244,16 @@ }; const char *const elkhartlake_pch_group_g_names[] = { - "GPP_G00", "SD_SDIO_CMD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G01", "SD_SDIO_D0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G02", "SD_SDIO_D1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G03", "SD_SDIO_D2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G04", "SD_SDIO_D3", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G05", "SD_SDIO_CD_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G06", "SD_SDIO_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G07", "AVS_I2S2_SCLK", "n/a", "n/a", "DMIC_CLK_A0", "n/a", "n/a", "n/a", "n/a", - "GPP_G08", "AVS_I2S2_SFRM", "RSVD", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "n/a", - "GPP_G09", "AVS_I2S2_TXD", "RSVD", "RSVD", "DMIC_CLK_A1", "n/a", "n/a", "n/a", "n/a", + "GPP_G0", "SD_SDIO_CMD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G1", "SD_SDIO_D0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G2", "SD_SDIO_D1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G3", "SD_SDIO_D2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G4", "SD_SDIO_D3", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G5", "SD_SDIO_CD_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G6", "SD_SDIO_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G7", "AVS_I2S2_SCLK", "n/a", "n/a", "DMIC_CLK_A0", "n/a", "n/a", "n/a", "n/a", + "GPP_G8", "AVS_I2S2_SFRM", "RSVD", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "n/a", + "GPP_G9", "AVS_I2S2_TXD", "RSVD", "RSVD", "DMIC_CLK_A1", "n/a", "n/a", "n/a", "n/a", "GPP_G10", "AVS_I2S2_RXD", "n/a", "n/a", "DMIC_DATA1", "n/a", "n/a", "n/a", "n/a", "GPP_G11", "AVS_I2S3_SCLK", "n/a", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "PSE_TGPIO07", "GPP_G12", "AVS_I2S3_SFRM", "SATA_1_GP", "SATAXPCIE_1", "DMIC_DATA1", "n/a", "n/a", "n/a", "PSE_TGPIO31", @@ -279,16 +279,16 @@ }; const char *const elkhartlake_pch_group_h_names[] = { - "GPP_H00", "PSE_GBE1_INT", "n/a", "n/a", "PSE_UART5_RXD", "n/a", "n/a", "n/a", "n/a", - "GPP_H01", "PSE_GBE1_RST_N", "n/a", "n/a", "PSE_UART5_TXD", "n/a", "n/a", "n/a", "n/a", - "GPP_H02", "PSE_GBE1_AUXTS", "n/a", "n/a", "PSE_UART5_RTS_N", "n/a", "n/a", "n/a", "n/a", - "GPP_H03", "PSE_GBE1_PPS", "n/a", "n/a", "PSE_UART5_CTS_N", "n/a", "n/a", "n/a", "PSE_TGPIO21", - "GPP_H04", "SIO_I2C2_SDA", "n/a", "n/a", "PSE_PWM08", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_H05", "SIO_I2C2_SCL", "n/a", "n/a", "PSE_PWM09", "n/a", "n/a", "n/a", "PSE_TGPIO11", - "GPP_H06", "SIO_I2C3_SDA", "PSE_I2C5_SDA", "n/a", "PSE_PWM10", "n/a", "n/a", "n/a", "n/a", - "GPP_H07", "SIO_I2C3_SCL", "PSE_I2C5_SCL", "n/a", "PSE_PWM11", "n/a", "n/a", "n/a", "n/a", - "GPP_H08", "SIO_I2C4_SDA", "RSVD", "n/a", "PSE_PWM12", "n/a", "n/a", "n/a", "n/a", - "GPP_H09", "SIO_I2C4_SCL", "RSVD", "n/a", "PSE_PWM13", "n/a", "n/a", "n/a", "n/a", + "GPP_H0", "PSE_GBE1_INT", "n/a", "n/a", "PSE_UART5_RXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H1", "PSE_GBE1_RST_N", "n/a", "n/a", "PSE_UART5_TXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H2", "PSE_GBE1_AUXTS", "n/a", "n/a", "PSE_UART5_RTS_N", "n/a", "n/a", "n/a", "n/a", + "GPP_H3", "PSE_GBE1_PPS", "n/a", "n/a", "PSE_UART5_CTS_N", "n/a", "n/a", "n/a", "PSE_TGPIO21", + "GPP_H4", "SIO_I2C2_SDA", "n/a", "n/a", "PSE_PWM08", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_H5", "SIO_I2C2_SCL", "n/a", "n/a", "PSE_PWM09", "n/a", "n/a", "n/a", "PSE_TGPIO11", + "GPP_H6", "SIO_I2C3_SDA", "PSE_I2C5_SDA", "n/a", "PSE_PWM10", "n/a", "n/a", "n/a", "n/a", + "GPP_H7", "SIO_I2C3_SCL", "PSE_I2C5_SCL", "n/a", "PSE_PWM11", "n/a", "n/a", "n/a", "n/a", + "GPP_H8", "SIO_I2C4_SDA", "RSVD", "n/a", "PSE_PWM12", "n/a", "n/a", "n/a", "n/a", + "GPP_H9", "SIO_I2C4_SCL", "RSVD", "n/a", "PSE_PWM13", "n/a", "n/a", "n/a", "n/a", "GPP_H10", "PCIE_CLKREQ4_N", "n/a", "n/a", "PSE_PWM14", "n/a", "n/a", "n/a", "n/a", "GPP_H11", "PCIE_CLKREQ5_N", "n/a", "n/a", "PSE_PWM15", "n/a", "n/a", "n/a", "n/a", "GPP_H12", "PSE_UART1_RXD", "n/a", "n/a", "M2_SKT2_CFG0", "n/a", "n/a", "n/a", "PSE_TGPIO51", @@ -313,14 +313,14 @@ }; const char *const elkhartlake_pch_group_r_names[] = { - "GPP_R00", "HDA_BCLK", "AVS_I2S0_SCLK", "PSE_I2S0_SCLK", "RSVD", "n/a", - "GPP_R01", "HDA_SYNC", "AVS_I2S0_SFRM", "PSE_I2S0_SFRM", "n/a", "n/a", - "GPP_R02", "HDA_SDO", "AVS_I2S0_TXD", "PSE_I2S0_TXD", "RSVD", "DMIC_CLK_B0", - "GPP_R03", "HDA_SDI0", "AVS_I2S0_RXD", "PSE_I2S0_RXD", "RSVD", "DMIC_CLK_B1", - "GPP_R04", "HDA_RST_N", "n/a", "n/a", "n/a", "DMIC_CLK_A1", - "GPP_R05", "HDA_SDI1", "AVS_I2S1_RXD", "n/a", "n/a", "DMIC_DATA1", - "GPP_R06", "n/a", "AVS_I2S1_TXD", "n/a", "n/a", "DMIC_CLK_A0", - "GPP_R07", "n/a", "AVS_I2S1_SFRM", "n/a", "n/a", "DMIC_DATA0", + "GPP_R0", "HDA_BCLK", "AVS_I2S0_SCLK", "PSE_I2S0_SCLK", "RSVD", "n/a", + "GPP_R1", "HDA_SYNC", "AVS_I2S0_SFRM", "PSE_I2S0_SFRM", "n/a", "n/a", + "GPP_R2", "HDA_SDO", "AVS_I2S0_TXD", "PSE_I2S0_TXD", "RSVD", "DMIC_CLK_B0", + "GPP_R3", "HDA_SDI0", "AVS_I2S0_RXD", "PSE_I2S0_RXD", "RSVD", "DMIC_CLK_B1", + "GPP_R4", "HDA_RST_N", "n/a", "n/a", "n/a", "DMIC_CLK_A1", + "GPP_R5", "HDA_SDI1", "AVS_I2S1_RXD", "n/a", "n/a", "DMIC_DATA1", + "GPP_R6", "n/a", "AVS_I2S1_TXD", "n/a", "n/a", "DMIC_CLK_A0", + "GPP_R7", "n/a", "AVS_I2S1_SFRM", "n/a", "n/a", "DMIC_DATA0", }; const struct gpio_group elkhartlake_pch_group_r = { @@ -348,8 +348,8 @@ "GPIO_RSVD_27", "n/a", "GPIO_RSVD_28", "n/a", "GPIO_RSVD_29", "n/a", - "GPP_S00", "n/a", - "GPP_S01", "n/a", + "GPP_S0", "n/a", + "GPP_S1", "n/a", }; const struct gpio_group elkhartlake_pch_group_s = { @@ -360,16 +360,16 @@ }; const char *const elkhartlake_pch_group_t_names[] = { - "GPP_T00", "PSE_QEPA2", "n/a", "SIO_I2C6_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", - "GPP_T01", "PSE_QEPB2", "n/a", "SIO_I2C6_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", - "GPP_T02", "PSE_QEPI2", "n/a", "SIO_I2C7_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", - "GPP_T03", "n/a", "n/a", "SIO_I2C7_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", - "GPP_T04", "PSE_GBE0_INT", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T05", "PSE_GBE0_RST_N", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T06", "PSE_GBE0_AUXTS", "USB2_OC1_N", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T07", "PSE_GBE0_PPS", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO59", - "GPP_T08", "USB2_OC2_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO22", - "GPP_T09", "PSE_HSUART2_EN", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_T0", "PSE_QEPA2", "n/a", "SIO_I2C6_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", + "GPP_T1", "PSE_QEPB2", "n/a", "SIO_I2C6_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", + "GPP_T2", "PSE_QEPI2", "n/a", "SIO_I2C7_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", + "GPP_T3", "n/a", "n/a", "SIO_I2C7_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", + "GPP_T4", "PSE_GBE0_INT", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T5", "PSE_GBE0_RST_N", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T6", "PSE_GBE0_AUXTS", "USB2_OC1_N", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T7", "PSE_GBE0_PPS", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO59", + "GPP_T8", "USB2_OC2_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO22", + "GPP_T9", "PSE_HSUART2_EN", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_T10", "PSE_HSUART2_RE", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_T11", "USB2_OC3_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", "GPP_T12", "PSE_UART2_RXD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -386,16 +386,16 @@ }; const char *const elkhartlake_pch_group_u_names[] = { - "GPP_U00", "GBE_INT", "PSE_I2C6_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U01", "GBE_RST_N", "PSE_I2C6_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U02", "GBE_PPS", "PSE_I2C7_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U03", "GBE_AUXTS", "PSE_I2C7_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U04", "ISI_SPIM_CS", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "n/a", - "GPP_U05", "ISI_SPIM_SCLK", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "n/a", - "GPP_U06", "ISI_SPIM_MISO", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "n/a", - "GPP_U07", "PSE_QEPA3", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_U08", "ISI_SPIS_CS", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_U09", "ISI_SPIS_SCLK", "ISI_I2CS_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", + "GPP_U0", "GBE_INT", "PSE_I2C6_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U1", "GBE_RST_N", "PSE_I2C6_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U2", "GBE_PPS", "PSE_I2C7_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U3", "GBE_AUXTS", "PSE_I2C7_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U4", "ISI_SPIM_CS", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPP_U5", "ISI_SPIM_SCLK", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "n/a", + "GPP_U6", "ISI_SPIM_MISO", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "n/a", + "GPP_U7", "PSE_QEPA3", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_U8", "ISI_SPIS_CS", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_U9", "ISI_SPIS_SCLK", "ISI_I2CS_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", "GPP_U10", "ISI_SPIS_MISO", "ISI_I2CS_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO12", "GPP_U11", "PSE_QEPB3", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", "GPP_U12", "ISI_CHX_OKNOK_0", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -420,16 +420,16 @@ }; const char *const elkhartlake_pch_group_v_names[] = { - "GPP_V00", "EMMC_CMD", - "GPP_V01", "EMMC_DATA0", - "GPP_V02", "EMMC_DATA1", - "GPP_V03", "EMMC_DATA2", - "GPP_V04", "EMMC_DATA3", - "GPP_V05", "EMMC_DATA4", - "GPP_V06", "EMMC_DATA5", - "GPP_V07", "EMMC_DATA6", - "GPP_V08", "EMMC_DATA7", - "GPP_V09", "EMMC_RCLK", + "GPP_V0", "EMMC_CMD", + "GPP_V1", "EMMC_DATA0", + "GPP_V2", "EMMC_DATA1", + "GPP_V3", "EMMC_DATA2", + "GPP_V4", "EMMC_DATA3", + "GPP_V5", "EMMC_DATA4", + "GPP_V6", "EMMC_DATA5", + "GPP_V7", "EMMC_DATA6", + "GPP_V8", "EMMC_DATA7", + "GPP_V9", "EMMC_RCLK", "GPP_V10", "EMMC_CLK", "GPP_V11", "EMMC_RST_N", "GPP_V12", "PSE_TGPIO00", -- To view, visit https://review.coreboot.org/c/coreboot/+/84190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Gerrit-Change-Number: 84190 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Remove unused pch_handle_sideband() function
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84189?usp=email ) Change subject: soc/intel/meteorlake: Remove unused pch_handle_sideband() function ...................................................................... soc/intel/meteorlake: Remove unused pch_handle_sideband() function This change removes the unused pch_handle_sideband() function from the Meteor Lake platform code. TEST=Able to build and boot google/rex. Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/finalize.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/84189/1 diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index ed29ba9..36837f9 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -23,10 +23,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> -static void pch_handle_sideband(config_t *config) -{ -} - static void pch_finalize(void) { config_t *config = config_of_soc(); @@ -36,8 +32,6 @@ /* TODO: Add Thermal Configuration */ - pch_handle_sideband(config); - pmc_clear_pmcon_sts(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Gerrit-Change-Number: 84189 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: spdtool: ignore utf-8 errors when decoding manufactorer
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84188?usp=email ) Change subject: spdtool: ignore utf-8 errors when decoding manufactorer ...................................................................... spdtool: ignore utf-8 errors when decoding manufactorer Fix early failures when filling it with invalid data. Change-Id: I7dfec2a67d7c46459fb96c752f2eb8caafb68fa2 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/spdtool/spdtool.py 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/84188/1 diff --git a/util/spdtool/spdtool.py b/util/spdtool/spdtool.py index 89976ea..aa25fad 100644 --- a/util/spdtool/spdtool.py +++ b/util/spdtool/spdtool.py @@ -148,7 +148,7 @@ if offset + 0x15c >= len(self.blob): return "" tmp = self.blob[offset + 0x149:offset + 0x15c + 1] - return tmp.decode('utf-8').rstrip() + return tmp.decode('utf-8', 'ignore').rstrip() def get_manufacturer_id(self, offset): """Return manufacturer ID""" -- To view, visit https://review.coreboot.org/c/coreboot/+/84188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dfec2a67d7c46459fb96c752f2eb8caafb68fa2 Gerrit-Change-Number: 84188 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Angel Pons, Paul Menzel, Pratikkumar V Prajapati. Alexander Couzens has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/75214?usp=email ) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... Patch Set 6: (2 comments) File util/inteltool/inteltool.h: https://review.coreboot.org/c/coreboot/+/75214/comment/445f8d52_d3df7826?us… : PS5, Line 338: #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_1 0x4514 > replace this by coreboot's own version of it. will do it in a separate patch. https://review.coreboot.org/c/coreboot/+/75214/comment/3db962f3_eeaaf7d1?us… : PS5, Line 487: #define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551 > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 16:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Angel Pons, Paul Menzel, Pratikkumar V Prajapati. Alexander Couzens has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/75214?usp=email ) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... Patch Set 5: (1 comment) File util/inteltool/spi.c: https://review.coreboot.org/c/coreboot/+/75214/comment/a5ec2a14_7e2a6441?us… : PS5, Line 450: !rcba_size > Isn't this check a bit redundant? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 16:14:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alexander Couzens, Paul Menzel, Pratikkumar V Prajapati. Hello Paul Menzel, Pratikkumar V Prajapati, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75214?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... inteltool: improve support for Elkhart Lake Add support for SPI/flash, LPC/eSPI, MCH and add pci vendor/product description. References: * CPU: Linux kernel * GPU: Linux kernel * GPU: https://dgpu-docs.intel.com/devices/hardware-table.html * Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for IoT Applications, February 2023, 636722 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/lpc.c M util/inteltool/memory.c M util/inteltool/spi.c 5 files changed, 219 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/75214/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[M] Change in coreboot[main]: soc/intel: Refactor ITSS macros
by Sean Rhodes (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jayvik Desai, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Rishika Raj, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Werner Zeh. Sean Rhodes has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84183?usp=email ) Change subject: soc/intel: Refactor ITSS macros ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Gerrit-Change-Number: 84183 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 15:50:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/inteltool: pci ids are 16 bit
by Paul Menzel (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alexander Couzens, Felix Held, Pratikkumar V Prajapati. Paul Menzel has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84186?usp=email ) Change subject: util/inteltool: pci ids are 16 bit ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84186/comment/1125c556_e2a0f41e?us… : PS1, Line 7: pci ids are 16 bit Maybe: > Reduce field width to 4 in unknown PCI ID message https://review.coreboot.org/c/coreboot/+/84186/comment/161fa0b6_7a70c240?us… : PS1, Line 8: Maybe print log before and after? -- To view, visit https://review.coreboot.org/c/coreboot/+/84186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87804a63f04b7461d348a245531542776575eb7a Gerrit-Change-Number: 84186 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 Sep 2024 15:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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