coreboot-gerrit September 2024

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[NoOp] Change in blobs[main]: 3rdparty/blobs/mb/google/zork: Update PSP signing token
by Matt DeVillier (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jon Murphy, Martin Roth, Raul Rangel, Tim Van Patten. Matt DeVillier has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/blobs/+/84179?usp=email ) Change subject: 3rdparty/blobs/mb/google/zork: Update PSP signing token ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/84179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Idb11284cf4ef3abcfdd9186d672b995d82c35ad1 Gerrit-Change-Number: 84179 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 16:03:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/inteltool: Fix format for PCI vendor/device IDs
by Matt DeVillier (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Alexander Couzens, Felix Held, Paul Menzel, Pratikkumar V Prajapati. Matt DeVillier has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84186?usp=email ) Change subject: util/inteltool: Fix format for PCI vendor/device IDs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84186/comment/535eea5e_83589459?us… : PS1, Line 8: > I don't think it's needed agreed -- To view, visit https://review.coreboot.org/c/coreboot/+/84186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87804a63f04b7461d348a245531542776575eb7a Gerrit-Change-Number: 84186 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Sep 2024 16:02:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: util/inteltool: Fix format for PCI vendor/device IDs
by Matt DeVillier (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Alexander Couzens, Felix Held, Paul Menzel, Pratikkumar V Prajapati. Matt DeVillier has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84186?usp=email ) Change subject: util/inteltool: Fix format for PCI vendor/device IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87804a63f04b7461d348a245531542776575eb7a Gerrit-Change-Number: 84186 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Sep 2024 16:02:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[NoOp] Change in blobs[main]: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
by Matt DeVillier (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jon Murphy, Martin Roth, Raul Rangel. Matt DeVillier has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/blobs/+/84181?usp=email ) Change subject: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/84181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2 Gerrit-Change-Number: 84181 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 16:01:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: include/spd_bin.h: Add 3 SPD IO functions
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

yuchi.chen(a)intel.com has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84201?usp=email ) Change subject: include/spd_bin.h: Add 3 SPD IO functions ...................................................................... include/spd_bin.h: Add 3 SPD IO functions Now SMBus calls the new SPD IO functions to retreive SPD data. The default implementation is to forward to SMBus IO functions directly. Based on this patch, SoC could provide another implementation of SPD IO functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c A src/soc/intel/common/block/smbus/spd_access.c 4 files changed, 40 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84201/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Gerrit-Change-Number: 84201 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: include/spd_bin.h: Add 3 SPD IO functions
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84201?usp=email ) Change subject: include/spd_bin.h: Add 3 SPD IO functions ...................................................................... include/spd_bin.h: Add 3 SPD IO functions Now SMBus calls the new SPD IO functions to retrive SPD data. The default implementation is to forward to SMBus IO functions directly. Based on this patch, SoC could provide another implementation of SPD IO functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c A src/soc/intel/common/block/smbus/spd_access.c 4 files changed, 40 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84201/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c51e449..434d674 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -49,6 +49,10 @@ void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +int spd_read_byte(u8 slave_addr, u8 bus_addr); +int spd_read_word(u8 slave_addr, u8 bus_addr); +void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value); + /* * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. * return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present. diff --git a/src/soc/intel/common/block/smbus/Makefile.mk b/src/soc/intel/common/block/smbus/Makefile.mk index 777d92a..dd56814 100644 --- a/src/soc/intel/common/block/smbus/Makefile.mk +++ b/src/soc/intel/common/block/smbus/Makefile.mk @@ -1,8 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index aff6fb0..deb09b3 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -20,7 +20,7 @@ blk->len = SPD_PAGE_LEN; } -static void smbus_read_spd(u8 *spd, u8 addr) +static void spd_read(u8 *spd, u8 addr) { u16 i; u8 step = 1; @@ -31,9 +31,9 @@ for (i = 0; i < SPD_PAGE_LEN; i += step) { if (CONFIG(SPD_READ_BY_WORD)) ((u16*)spd)[i / sizeof(uint16_t)] = - smbus_read_word(addr, i); + spd_read_word(addr, i); else - spd[i] = smbus_read_byte(addr, i); + spd[i] = spd_read_byte(addr, i); } } @@ -42,11 +42,11 @@ { if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Restore to page 0 before reading */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } /* If address is not 0, it will return CB_ERR(-1) if no dimm */ - if (smbus_read_byte(addr, 0) < 0) { + if (spd_read_byte(addr, 0) < 0) { printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1); return -1; @@ -54,20 +54,20 @@ if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd, addr); + spd_read(spd, addr); } /* Check if module is DDR4, DDR4 spd is 512 byte. */ if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + spd_write_byte(SPD_PAGE_1, 0, 0); if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); + spd_read(spd + SPD_PAGE_LEN, addr); } /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } return 0; } @@ -109,11 +109,11 @@ if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Restore to page 0 before reading */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } /* If dimm is not present, set sn to 0xff. */ - smbus_ret = smbus_read_byte(addr, SPD_DRAM_TYPE); + smbus_ret = spd_read_byte(addr, SPD_DRAM_TYPE); if (smbus_ret < 0) { printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1); *sn = 0xffffffff; @@ -125,17 +125,17 @@ /* Check if module is DDR4, DDR4 spd is 512 byte. */ if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + spd_write_byte(SPD_PAGE_1, 0, 0); for (i = 0; i < SPD_SN_LEN; i++) - *((u8 *)sn + i) = smbus_read_byte(addr, + *((u8 *)sn + i) = spd_read_byte(addr, i + DDR4_SPD_SN_OFF); /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } else if (dram_type == SPD_DRAM_DDR3) { for (i = 0; i < SPD_SN_LEN; i++) - *((u8 *)sn + i) = smbus_read_byte(addr, + *((u8 *)sn + i) = spd_read_byte(addr, i + DDR3_SPD_SN_OFF); } else { printk(BIOS_ERR, "Unsupported dram_type\n"); diff --git a/src/soc/intel/common/block/smbus/spd_access.c b/src/soc/intel/common/block/smbus/spd_access.c new file mode 100644 index 0000000..f37e313 --- /dev/null +++ b/src/soc/intel/common/block/smbus/spd_access.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> +#include <spd_bin.h> + +int spd_read_byte(u8 slave_addr, u8 bus_addr) +{ + return smbus_read_byte(slave_addr, bus_addr); +} + +int spd_read_word(u8 slave_addr, u8 bus_addr) +{ + return smbus_read_word(slave_addr, bus_addr); +} + +void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value) +{ + smbus_write_byte(slave_addr, bus_addr, value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Gerrit-Change-Number: 84201 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84200?usp=email ) Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER ...................................................................... soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER Systemagent assumes GSM region is next to TSEG region, but some SoC may not have GSM region (https://review.coreboot.org/c/coreboot/+/84108). On such platforms, TSEG region is limited by the TSEG limit register, and the default offset for that is (TSEG + 4). Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84200/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 42d579a..1fbc861 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -55,4 +55,10 @@ help Specify if the SOC has BDSM and BGSM registres. +config HAVE_TSEG_LIMIT_REGISTER + bool + default n + help + Specify if SoC has TSEG limit register next to TSEG register. + endif diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index aecdfbb..9a03f19 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -148,7 +148,14 @@ size_t sa_get_tseg_size(void) { - return sa_get_gsm_base() - sa_get_tseg_base(); + if (!CONFIG(HAVE_TSEG_LIMIT_REGISTER)) { + return sa_get_gsm_base() - sa_get_tseg_base(); + } else { + /* TSEG limit is next to TSEG by default. */ + return soc_systemagent_fixup_address(TSEG + 4, + pci_read_config32(SA_DEV_ROOT, TSEG + 4)) - + sa_get_tseg_base(); + } } union dpr_register txt_get_chipset_dpr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/84200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Gerrit-Change-Number: 84200 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: soc/intel/common/systemagent: Fix grammer in comments
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84199?usp=email ) Change subject: soc/intel/common/systemagent: Fix grammer in comments ...................................................................... soc/intel/common/systemagent: Fix grammer in comments Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84199/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8d7432..6239a46 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -274,7 +274,7 @@ int index = 0; /** - * If SoC has multiple PCIe domains, only reading resources from the first one. + * If SoC has multiple PCIe domains, only read resources from the first one. */ if (!is_dev_on_domain0(dev)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/84199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Gerrit-Change-Number: 84199 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Fixup systemagent address
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Felix Held, Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent: Fixup systemagent address ...................................................................... soc/intel/common/systemagent: Fixup systemagent address System agent in Intel common block (1) assumes TOLUD and TOUUD registers hold the max available address plus 1, but on some SoC like Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD and TSEG registers to 1 MiB default, but some SoC may have different alignments. This patch add a new function soc_systemagent_fixup_address() to improve it. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 38 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 16 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/ith.asl A src/soc/intel/snowridge/acpi/lpc.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/sata0.asl A src/soc/intel/snowridge/acpi/sata2.asl A src/soc/intel/snowridge/acpi/smbus.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/hob_iiouds.h A src/soc/intel/snowridge/hqm.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/itss.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pci_ids.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/memmap.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 73 files changed, 5,866 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 18 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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coreboot-gerrit September 2024