coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
2151 discussions

[XS] Change in coreboot[main]: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > oh ya, i see. got confused with the naming of macro. no worries, I agree we should avoid `SET` from the macro name. but we should keep the `_32_` to keep the name meaningful for 32-bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
by Pratikkumar V Prajapati (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Saurabh Mishra. Pratikkumar V Prajapati has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > > yeah, also 32bit is not enforced within macro. x is the variable input. […] oh ya, i see. got confused with the naming of macro. -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 20: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/e185fd24_00eaac09?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > 15:starting LZMA decompress (ignore for x86) -- after starting to load payload > 1050:finished reading kernel from disk > Increase in boot time is observed in the above 2 places . > General observation is reducing PL4 always results in increase in boot time what you have shared in an observation. did you get a chance to root cause or find the reason why the boot time has regressed only during IO bound operation like reading from a block device while reducing the PL4 limit ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 20 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:21:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/6b468cdd_af72321c?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > I do a search and only the existing gpe event disabling functions need to cover GPE1 EN bits if _HAVE_GPE1. By doing this, no _gpe_function needs to be renamed outside of pmclib.c. > > In addition, I delete the GPE event enable functions which one have deleted ? > since not used. CB should not enable these events during boot, anyways. without keeping the GPE enabled bit set, how can we wake the device with various wake sources as defined by the `General Purpose Event 0 Enable [127:96] (GPE0_EN[127:96])` like alarm, lan wake etc? File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/23f279e4_1d64c63e?us… : PS8, Line 321: soc_pmc_disable_std_gpe1(mask); > Subrata, > > In PTL, in the case that we choose not to switch to use GPE1 events (i.e. not include GPE1 in FADT so that kernel won't see GPE1 event and include only ACPI GPE0 event methods in DSDT/SSDT), these GPE1 status bit might still be set by the HW and we need to clear it at boot. We might need to go back to use _HAVE_GPE1 and _USE_GPE1 approach. > > _USE_GPE1: if false: _USE_GEP1: dummy GPE_STS defines. include GPE0 methods. > > if true: add GPE1 blocks to FADT and include GPE1 methods > > _HAVE_GPE1: > define GPE_STS() in SOC. > clear GPE1 STS at boot. > > acpi.c: > fadt->gpe1_blk = CONFIG(_USE_GPE1) ? (pmbase + GPE1_STS(0)) : 0; > > also, in acpi Kconfig > _USE_GPE1 depends on _HAVE_GPE1 as you mentioned in one of comments. > > Any thought prior to https://review.coreboot.org/c/coreboot/+/84103/14 being merged? I am having trouble understanding why we would not use GPE1 if the HW logic would use it for wake functionality. For example, why would we use a GPIO configured as GPE0 for CNVi if GPE1 already has native support? Could you please explain what you mean by "HW will set those bits"? Ideally, HW would only set those bits if the HW logic applies to GPE1 and not GPE0. What would happen if we were using GPE0? Would only the GPE1 status bit be set? Additionally, if we decided not to use GPE1, then we would not be setting the GPE1 Enable PINs. HW logic can only set GPE1 status and not the enable bit. Unless both En and Status are set, there is no GPE event that would trigger. We do not need to even clear the GPE1 status unless we really plan to configure GPE1 enable bits. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:18:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > yeah, also 32bit is not enforced within macro. x is the variable input. what you mean by 32-bit is not enforced ? `1u` itself is telling us that we can shift the `x` by 32-bit. The reason, I have suggested using the flag to specify that we are passing a bit_position and `1U << (bit_position)` shifts the value 1 to the left by the specified . ``` #define SET_32_BIT_FLAG(x) (1u << (x)) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:14:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 20: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/8a1c1018_6b22ccec?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > > >>>>>>Then, it would be good to boot with a static configuration which is safest and generically a […] 15:starting LZMA decompress (ignore for x86) -- after starting to load payload 1050:finished reading kernel from disk Increase in boot time is observed in the above 2 places . General observation is reducing PL4 always results in increase in boot time -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 20 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:10:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: src/soc/intel/common: Add Intel RMT+ support
by Pratikkumar V Prajapati (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Anil Kumar K, Arthur Heymans, Bora Guvendik, Cliff Huang, Gaggery Tsai, Jamie Ryu, Kane Chen, Karthik Ramasubramanian, Krishna P Bhat D, Ronak Kanabar, Subrata Banik, V Sowmya, Wonkyu Kim. Pratikkumar V Prajapati has posted comments on this change by Gaggery Tsai. ( https://review.coreboot.org/c/coreboot/+/77904?usp=email ) Change subject: src/soc/intel/common: Add Intel RMT+ support ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/memory/Kconfig: https://review.coreboot.org/c/coreboot/+/77904/comment/d627a3cf_3a15ff74?us… : PS9, Line 33: config SOC_INTEL_RMT_PLUS : bool : select SOC_INTEL_COMMON_ACPI_BDAT : help : Intel RMT plus is a feature from FSPM. It exports the RMT data from : HOBs with 4 different GUIDs for 4 SAGV points. With this feature : enabled, once the memory training is required, the RMT flag will be : turned on automatically. The RMT data exported from HOBs will pass : through ACPI BDAT table to the OS. : : config SOC_INTEL_RMT_PLUS_IN_DEV_MODE : bool : select SOC_INTEL_COMMON_ACPI_BDAT : help : This is the same with SOC_INTEL_RMT_PLUS but only enables RMT plus : in the DEV mode. instead of multiple bool configs, would it make sense to have just one config and set various types of mode with the single config? -- To view, visit https://review.coreboot.org/c/coreboot/+/77904?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03df4d0a927caa101da3db078b268dcdb4e78550 Gerrit-Change-Number: 77904 Gerrit-PatchSet: 9 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 18:03:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
by Pratikkumar V Prajapati (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Saurabh Mishra, Subrata Banik. Pratikkumar V Prajapati has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > I am not in favor of `SET_32_BIT_FLAG()`. This macro name is confusing to me. […] yeah, also 32bit is not enforced within macro. x is the variable input. -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 17:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/0c30d326_f4de1747?us… : PS8, Line 321: soc_pmc_disable_std_gpe1(mask); Subrata, In PTL, in the case that we choose not to switch to use GPE1 events (i.e. not include GPE1 in FADT so that kernel won't see GPE1 event and include only ACPI GPE0 event methods in DSDT/SSDT), these GPE1 status bit might still be set by the HW and we need to clear it at boot. We might need to go back to use _HAVE_GPE1 and _USE_GPE1 approach. _USE_GPE1: if false: _USE_GEP1: dummy GPE_STS defines. include GPE0 methods. if true: add GPE1 blocks to FADT and include GPE1 methods _HAVE_GPE1: define GPE_STS() in SOC. clear GPE1 STS at boot. acpi.c: fadt->gpe1_blk = CONFIG(_USE_GPE1) ? (pmbase + GPE1_STS(0)) : 0; also, in acpi Kconfig _USE_GPE1 depends on _HAVE_GPE1 as you mentioned in one of comments. Any thought prior to https://review.coreboot.org/c/coreboot/+/84103/14 being merged? https://review.coreboot.org/c/coreboot/+/84104/comment/8fb77c5c_fc6d977c?us… : PS8, Line 330: if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)) same reason for pmc_disable_std_gpe() -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 17:49:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL
by Pratikkumar V Prajapati (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Saurabh Mishra. Pratikkumar V Prajapati has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84178?usp=email ) Change subject: soc/intel/common/block: Include register offsets for POWER_CTL ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Gerrit-Change-Number: 84178 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 17:40:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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