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Change subject: include/console/system76_ec.h: Remove unused <stddef.h>
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Patch Set 2: Code-Review+2
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Change subject: nb/amd/agesa/agesa_helper.h: Remove unused <stddef.h>
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Patch Set 2: Code-Review+2
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Change subject: Introduce a coreboot Control Block (CCB)
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Patch Set 13:
(1 comment)
File 3rdparty/arm-trusted-firmware:
https://review.coreboot.org/c/coreboot/+/77712/comment/f7cad2f3_55990bc2?us… :
PS13, Line 1: Subproject commit 88b2d81345dfd84902aae586a743d00ac5df2f48
Why would this be updating the submodule?
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Change subject: Update arm-trusted-firmware submodule to upstream master
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/965322a0_58b78559?us… :
PS11, Line 241: gpe0_mask
> > Adding GPE1 ref from PTL EDS links for internal device events:
> >
> > PME_B0 events:
> > https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
> >
> > hot plug events:
> > https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
> >
> > PCIe events:
> > https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
>
> @cliff, the question here is what if one design wish to use GPE1, will they have to pass the GPE0 register details to know if the corresponding GPE1 bit is set or not ? My understanding is if GPE1 is being used, we will publish a new sets of GPE events specific for GPE1 and in such case, we will read GPE1 status/en bit and not necessarily try to map GPE0 events against GPE1 events.
>
> if GPE1 is not there, then we use GPE0 and PMC_B0 event muxed for many other internal IPs as well and not as specific as GPE1 bit definition that i have shared.
> The last function is to disable PME_B0 events and its 32-bit mask covers GPE0 std events. With GPE1 events being enabled, their corresponding PME_B0 events in GPE1 needs to be disabled and therefore gpe0_mask is used for SOC GPE1 disable function to clear.
I would expect to read GPE1 status directly and pass that over relying on GPE0 to clean GPE1 event status register.
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/c56cbf85_0423e45c?us… :
PS11, Line 241: gpe0_mask
> Adding GPE1 ref from PTL EDS links for internal device events:
>
> PME_B0 events:
> https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
>
> hot plug events:
> https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
>
> PCIe events:
> https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/…
@cliff, the question here is what if one design wish to use GPE1, will they have to pass the GPE0 register details to know if the corresponding GPE1 bit is set or not ? My understanding is if GPE1 is being used, we will publish a new sets of GPE events specific for GPE1 and in such case, we will read GPE1 status/en bit and not necessarily try to map GPE0 events against GPE1 events.
if GPE1 is not there, then we use GPE0 and PMC_B0 event muxed for many other internal IPs as well and not as specific as GPE1 bit definition that i have shared.
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/443c1551_ade5dc5a?us… :
PS11, Line 241: gpe0_mask
> Adding GPE1 ref from PTL EDS links for internal device events: […]
in src/soc/intel/common/block/smm/smm.c:
static void smm_southbridge_enable(uint16_t pm1_events)
{
uint32_t smi_params = ENABLE_SMI_PARAMS;
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
pmc_enable_pm1(pm1_events);
pmc_disable_std_gpe(PME_B0_EN);
...
The last function is to disable PME_B0 events and its 32-bit mask covers GPE0 std events. With GPE1 events being enabled, their corresponding PME_B0 events in GPE1 needs to be disabled and therefore gpe0_mask is used for SOC GPE1 disable function to clear.
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Change subject: mb/google/brox/variants/brox:remove PL4 value modification
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Patch Set 3:
(1 comment)
Patchset:
PS3:
Taken over the patch, since the Author is no more part of Intel.
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/1d5d566c_ea25c29a?us… :
PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */
: __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
: {
: return NULL;
: }
:
: /* disable the corresponding GPE1 bits based on standard GPE0 bits */
: __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask)
: {
: }
:
: /* enable the corresponding GPE1 bits based on standard GPE0 bits */
: __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
: {
: }
> i just tested removing the weak functions and building a board that selects SOC_INTEL_COMMON_BLOCK_ […]
oh, that SOC_INTEL_COMMON_BLOCK_ should have been SOC_INTEL_COMMON_BLOCK_PMC; not sure where those few chars went
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