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Change subject: toolchain: Add support for sccache
......................................................................
toolchain: Add support for sccache
sccache (https://github.com/mozilla/sccache) is a compiler caching tool
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It also supports distributed compilation through automatic packaging of
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infrastructure on demand more easily.
Change-Id: Ia28e696dfe9eab0fc73ba8c7c6bdfc90cbdb790e
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
M src/Kconfig
M toolchain.mk
3 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83973/3
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Change subject: mb/emulation/qemu-sbsa: Generate PPTT ACPI table
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/emulation/qemu-sbsa/pptt.c:
https://review.coreboot.org/c/coreboot/+/79108/comment/d1305844_bd96afed?usā¦ :
PS7, Line 9: #define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type
: #define CLUSTER_FLAGS 0x11 // physical package, ID invalid, no thread, no leaf, identical impl.
: #define CORE_FLAGS 0x1a // no physical package, ID valid, no thread, leaf, identical impl.
:
: #define CACHE_ATTR_TYPE_DATA (0)
: #define CACHE_ATTR_TYPE_INSTRUCTION (0x1 << 2)
: #define CACHE_ATTR_TYPE_UNIFIED (0x1 << 3)
> Done
You have a struct for the pptt_cache flags. Why use a raw value?
const struct pptt_cache_node_flags cache_flags = {
.size_valid = 1,
.n_sets_valid = 1, ...
};
Same for the cpu flags.
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Change subject: Docs: Fix broken header references
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83976/comment/96928037_4779c150?usā¦ :
PS1, Line 10: lower-case
I think this is called `slug-case`
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Change subject: mb/goog/brya: unlock gpio wake sources
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
@amanda_hwang@compal.corp-partner.google.com will you be able to pick this CL and test if S0ix works and system is able to wake from sleep.
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Hello Martin Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83973?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: toolchain: Add support for sccache
......................................................................
toolchain: Add support for sccache
sccache (https://github.com/mozilla/sccache) is a compiler caching tool
similar to ccache. It has support for multiple cloud and networked
storage backends. This could come in handy so that multiple build
servers share a cache.
It also supports distributed compilation through automatic packaging of
local toolchains. This might come in handy to scale the builder
infrastructure on demand more easily.
Change-Id: Ia28e696dfe9eab0fc73ba8c7c6bdfc90cbdb790e
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
M src/Kconfig
M toolchain.mk
3 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83973/2
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Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83978?usp=email )
Change subject: Doc/mb/starlabs/lite_adl.md: Fix embedded rST syntax
......................................................................
Doc/mb/starlabs/lite_adl.md: Fix embedded rST syntax
MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks,
instead of eval_rst as used previously by recommonmark.
Change-Id: I1f16d594af41a13762ba299b8d4f9d88e59c68ed
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M Documentation/mainboard/starlabs/lite_adl.md
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/83978/2
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Change subject: Doc/mb/starlabs: Rename starlite_adl.md to lite_adl.md
......................................................................
Doc/mb/starlabs: Rename starlite_adl.md to lite_adl.md
The reference in Doc/mb/index.md was to starlabs/lite_adl.md, whereas
the file was actually named starlite_adl.md. Rename the file to fix the
broken reference and match the naming scheme of the markdown files for
the other StarLite systems.
Change-Id: I1922940fd18cc806d9647cbe05ad11b2a70e0d08
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
R Documentation/mainboard/starlabs/lite_adl.md
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83977/1
diff --git a/Documentation/mainboard/starlabs/starlite_adl.md b/Documentation/mainboard/starlabs/lite_adl.md
similarity index 100%
rename from Documentation/mainboard/starlabs/starlite_adl.md
rename to Documentation/mainboard/starlabs/lite_adl.md
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Change subject: Docs: Fix broken header references
......................................................................
Docs: Fix broken header references
As per MyST Parser's documentation, cross references to headers should
match the header text after being converted to lower-case with
punctuation removed and spaces replaced with a dash (not an underscore).
This fixes a few "cross-reference target not found" warnings.
[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#auto-geneā¦
Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M Documentation/mainboard/lenovo/Ivy_Bridge_series.md
M Documentation/northbridge/intel/sandybridge/nri_freq.md
M Documentation/releases/coreboot-4.13-relnotes.md
M Documentation/superio/nuvoton/npcd378.md
4 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/83976/1
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
index 73d38fe..a7893e7 100644
--- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
+++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
@@ -82,7 +82,7 @@
space for the `bios` region. This is usually referred to as *cleaning the ME* or
*stripping the ME*.
After reducing the Intel ME firmware size you must modify the original IFD,
-[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
+[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write
each ROM using an [external programmer].
Have a look at [me_cleaner] for more information.
diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md
index 45cac8d..0732870 100644
--- a/Documentation/northbridge/intel/sandybridge/nri_freq.md
+++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md
@@ -160,7 +160,7 @@
slowest DIMMs' frequency will be selected, to prevent over-clocking it.
The selected frequency gives the PLL multiplier to operate at. In case the PLL
-locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
+locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for
all DIMMs. At this point it's not possible to change the multiplier again,
until the system has been powered off. In case the PLL doesn't lock, the next
smaller multiplier will be used until a working multiplier will be found.
diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md
index 600bf67..29374d1 100644
--- a/Documentation/releases/coreboot-4.13-relnotes.md
+++ b/Documentation/releases/coreboot-4.13-relnotes.md
@@ -214,7 +214,7 @@
In order to minimize the usage of PCI bus mastering, the options we introduced in
this release will be dropped in a future release again. For more details, please
-see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot).
+see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering).
### Resource allocator v3
diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md
index 1cc081b..6e5bf66 100644
--- a/Documentation/superio/nuvoton/npcd378.md
+++ b/Documentation/superio/nuvoton/npcd378.md
@@ -78,7 +78,7 @@
### LDN8
Custom HWM space. It exposes 256 byte of IO config space.
-See [HWM](#HWM) for more details.
+See [HWM](#hwm) for more details.
## HWM
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