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Hello Jérémy Compostella,
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86/Kconfig: Fix linking with LLD
......................................................................
arch/x86/Kconfig: Fix linking with LLD
Somehow the trick for older binutils is also needed for LLD.
Change-Id: I1a6a5ef9dc6d824fa108681689a69df3faefd3c6
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84049/5
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Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83989/comment/b58df698_b6e94885?us… :
PS6, Line 9: To reduce duplicate pad_func of MediaTek SoCs,
: Move the pad_fun to a common directory
> Single paragraph with max 72 chars per line. […]
Done
File src/soc/mediatek/common/flash_controller.c:
https://review.coreboot.org/c/coreboot/+/83989/comment/9b61feea_aed2737f?us… :
PS6, Line 229:
> Remove blank line.
Done
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
soc/mediatek: Move SNFC pad_func into MediaTek common directory
To reduce duplicate pad_func of MediaTek SoCs, move the pad_fun to a common directory.
TEST=Build pass
BUG=b:317009620
Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/flash_controller.c
M src/soc/mediatek/common/include/soc/flash_controller_common.h
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83989/7
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Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
Patch Set 6:
(2 comments)
File src/soc/mediatek/common/flash_controller.c:
https://review.coreboot.org/c/coreboot/+/83989/comment/0baf0243_767ae045?us… :
PS5, Line 239: else
> no need
Done
https://review.coreboot.org/c/coreboot/+/83989/comment/710180c5_e85e65df?us… :
PS5, Line 240: printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__,
: gpio_get_driving(pad_func->gpio));
> decrease indent
Done
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Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83989/comment/3516134d_ed68ec25?us… :
PS6, Line 9: To reduce duplicate pad_func of MediaTek SoCs,
: Move the pad_fun to a common directory
Single paragraph with max 72 chars per line.
```
To reduce duplicate pad_func of MediaTek SoCs, move the pad_fun to a common directory.
```
File src/soc/mediatek/common/flash_controller.c:
https://review.coreboot.org/c/coreboot/+/83989/comment/df0c3248_dcb4ad4f?us… :
PS6, Line 229:
Remove blank line.
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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
soc/mediatek: Move SNFC pad_func into MediaTek common directory
To reduce duplicate pad_func of MediaTek SoCs,
Move the pad_fun to a common directory
TEST=Build pass
BUG=b:317009620
Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/flash_controller.c
M src/soc/mediatek/common/include/soc/flash_controller_common.h
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83989/6
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 12: Code-Review+2
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84021?usp=email )
Change subject: mb/google/nissa/var/nivviks: Correct USB port for PCIE WLAN bluetooth
......................................................................
mb/google/nissa/var/nivviks: Correct USB port for PCIE WLAN bluetooth
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: I0908ff500434401bf89a5313427cf304f32cf929
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
V Sowmya: Looks good to me, approved
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index bf774e2..24c6d61 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -515,7 +515,7 @@
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
- use usb2_port10 as bluetooth_companion
+ use usb2_port8 as bluetooth_companion
device pci 00.0 on
probe WIFI_CATEGORY WIFI_7
end
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Gerrit-Change-Number: 84021
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84020?usp=email )
Change subject: mb/google/nissa/var/riven: Correct USB port for PCIE WLAN bluetooth
......................................................................
mb/google/nissa/var/riven: Correct USB port for PCIE WLAN bluetooth
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
V Sowmya: Looks good to me, approved
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 0481848..6f33f48 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -480,7 +480,7 @@
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
- use usb2_port10 as bluetooth_companion
+ use usb2_port8 as bluetooth_companion
device pci 00.0 on
probe WIFI_TYPE WIFI_PCIE
end
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Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83861?usp=email
to look at the new patch set (#5).
Change subject: soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1
......................................................................
soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1
According to the Intel GPU list [1], these devices have the following
IDs:
8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2]
8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610]
8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3]
8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610]
Allows coreboot to correctly initialize IGD (8086:9ba8) in Intel Celeron
G5905 CPU (ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9).
This can also be verified using devicehunt.com [2,3].
[1] https://web.archive.org/web/20240731152818/https://dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20240731150632/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA8
[3] https://web.archive.org/web/20230928015210/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA4
Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/include/device/pci_ids.h
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/83861/5
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