Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83456?usp=email )
Change subject: mb/starlabs/starbook/cml: Drop superfluous devices from devicetree
......................................................................
mb/starlabs/starbook/cml: Drop superfluous devices from devicetree
In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: I92765b404508901c7e84fad0bca30489cf69abac
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
1 file changed, 0 insertions(+), 36 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Elyes Haouas: Looks good to me, but someone else must approve
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 6f800cb..448fc29 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -51,14 +51,10 @@
# Actual device tree.
device domain 0 on
- device ref system_agent on end
device ref igpu on end
device ref dptf on
register "Device4Enable" = "1"
end
- device ref thermal off end
- device ref ufs off end
- device ref gspi2 off end
device ref xhci on
# Motherboard USB Type C
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
@@ -81,7 +77,6 @@
# Internal Bluetooth
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
end
- device ref xdci off end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
@@ -89,7 +84,6 @@
device generic 0 on end
end
end
- device ref sdxc off end
device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""STAR0001""
@@ -100,15 +94,6 @@
device i2c 2c on end
end
end
- device ref i2c1 off end
- device ref i2c2 off end
- device ref i2c3 off end
- device ref heci1 on end
- device ref heci2 off end
- device ref csme_ider off end
- device ref csme_ktr off end
- device ref heci3 off end
- device ref heci4 off end
device ref sata on
register "SataSalpSupport" = "1"
# Port 1
@@ -116,17 +101,7 @@
register "SataPortsDevSlp[1]" = "1"
end
device ref i2c4 on end
- device ref i2c5 off end
device ref uart2 on end
- device ref emmc off end
- device ref pcie_rp1 off end
- device ref pcie_rp2 off end
- device ref pcie_rp3 off end
- device ref pcie_rp4 off end
- device ref pcie_rp5 off end
- device ref pcie_rp6 off end
- device ref pcie_rp7 off end
- device ref pcie_rp8 off end
device ref pcie_rp9 on # SSD x4
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpEnable[8]" = "1"
@@ -135,13 +110,6 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device ref pcie_rp10 off end
- device ref pcie_rp11 off end
- device ref pcie_rp12 off end
- device ref uart0 off end
- device ref uart1 off end
- device ref gspi0 off end
- device ref gspi1 off end
device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
@@ -172,14 +140,10 @@
device pnp 4e.19 off end # Power Management Channel 5
end
end
- device ref p2sb on end
- device ref pmc hidden end
device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
device ref smbus on end
- device ref fast_spi on end
- device ref gbe off end
end
chip drivers/crb
device mmio 0xfed40000 on end
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Eric Lai has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83456?usp=email )
Change subject: mb/starlabs/starbook/cml: Drop superfluous devices from devicetree
......................................................................
Patch Set 6: Code-Review+2
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Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
Patch Set 3:
(1 comment)
File src/arch/arm64/armv8/mmu.c:
https://review.coreboot.org/c/coreboot/+/83652/comment/cda99e36_add71dce?us… :
PS2, Line 60: /* Func : table_level_name
: * Desc : Get the descriptions table level name from the given size.
: */
> Thanks Paul for pointing this out. […]
Yes, I agree and didn’t mean, that you change it.
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Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83652/comment/99b5ffb7_2090fcdd?us… :
PS2, Line 9: When using format string with "%p", "(nil)" will be printed for address
> I'm curious where you see this? coreboot's `vtxprintf()` doesn't do this as far as I can tell.
See this in unit tests, not on a real ARM device. Let me modify the commit message.
File src/arch/arm64/armv8/mmu.c:
https://review.coreboot.org/c/coreboot/+/83652/comment/43c1a870_a2f7b696?us… :
PS2, Line 60: /* Func : table_level_name
: * Desc : Get the descriptions table level name from the given size.
: */
> The code in this file precedes those style decisions, and until someone has time to update the whole […]
Thanks Paul for pointing this out. I did notice the wrong style in this file when writing this function. However I thought style consistency is more important, so I chose the following the existing style.
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Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83652?usp=email
to look at the new patch set (#3).
Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
arch/arm64/armv8/mmu: Improve log format
Currently we use "%p" to print the address, which results in different
string lengths, depending on the value of the address. To improve
readability of the printed addresses in the log, change the format to
"0x%013lx", so that the length of the printed addresses will be
consistent.
In addition, print the level of the translation table when setting up a
new table.
Example log:
Backing address range [0x0000000000000:0x1000000000000) with new L0 ...
Mapping address range [0x0000000000000:0x0000200000000) as ...
Backing address range [0x0000000000000:0x0008000000000) with new L1 ...
Mapping address range [0x0000000100000:0x0000000130000) as ...
Backing address range [0x0000000000000:0x0000040000000) with new L2
Backing address range [0x0000000000000:0x0000000200000) with new L3
Mapping address range [0x0000000107000:0x0000000108000) as ...
Mapping address range [0x0000000200000:0x0000000300000) as ...
Backing address range [0x0000000000000:0x0000000200000) with new L3 ...
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/arch/arm64/armv8/mmu.c
1 file changed, 30 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83652/3
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,261 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/17
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