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Change subject: soc/intel/xeon_sp: Use pre-processor to define ASL handler names
......................................................................
soc/intel/xeon_sp: Use pre-processor to define ASL handler names
ASL handler name is 4-byte length ACPI name in the scope of \_SB
which is not quite human readable and easy to be mixed with other
methods under \_SB.
Use pre-processor to define human readable handler names so that
they are well managed in \_SB scope.
TEST=Build and boot on intel/archercity CRB
Change-Id: I4134b275143d4f52622b864ed202252b2a150dae
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/acpi/iiostack.asl
A src/soc/intel/xeon_sp/include/soc/asl_handler.h
3 files changed, 19 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82133/8
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/google/brya/variants/teliks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83408/comment/4ffa0345_71377b24?us… :
PS10, Line 378: end
> This part follows anraggar and can work without using FW config distinction.
yeah, bt there will be unwanted device initialize time and then followed by timeout if we are saying both WLAN is present. In such case SOC logic needs to probe both devices to understand which one is actually present, we could improve the boot latency if we introduce FW config for such 2nd BoM source components in future.
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS10:
This part follows anraggar and can work without using FW config distinction.
File src/mainboard/google/brya/variants/teliks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83408/comment/1871a1ad_f851fdba?us… :
PS10, Line 378: end
> don't you need a FW config to probe if case i assume there can't be two WLAN solution in any SKU?
This part follows anraggar and can work without using FW config distinction.
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Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83650?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
......................................................................
soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/soc/mediatek/mt8188/include/soc/memlayout.ld
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Yidi Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index 3dc386e..732b5ba 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -29,7 +29,7 @@
/*
* The L3 is 2MB in total. The bootROM has configured half of the L3 cache as SRAM
- *(SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you
+ * (SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you
* can't reconfigure whole L3 as SRAM).
*/
SRAM_L2C_START(0x00200000)
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Change subject: soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83650/comment/9d76a810_8717e4ad?us… :
PS1, Line 7: Fix
> Add
Done
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Hello Paul Menzel, Yidi Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
......................................................................
soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8188/include/soc/memlayout.ld
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/83650/2
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Change subject: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Should the comment be reworded for the other SOCs too?
Yes we can reword it for mt8192 and mt8195. However this commit is mainly for moving the comment to the right location. I just took the chance to revise the comment. Therefore rewording for other SoCs can be done in separate patches IMO.
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Change subject: mb/google/corsola: Add new board 'Kyogre'
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80136/comment/26b6fb90_ccbab246?us… :
PS1, Line 7: Add new board 'Kyogre'
> Please look at other commits, how to add it. I think, this one should be named *variant*.
This patch is a duplicate of CB:81218 (merged), so it should be abandoned. However unlike ChromiumOS patches, it seems I don't have permission to abandon others' patches. Paul, if you can, please abandon this and its parent patch.
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
File src/mainboard/google/brya/variants/teliks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83408/comment/ebd3abc2_8b921c63?us… :
PS10, Line 378: end
don't you need a FW config to probe if case i assume there can't be two WLAN solution in any SKU?
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