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Change subject: xcompile: Apply -Wextra with temporary exceptions to GCC
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
Patchset:
PS6:
As discussed offline, `xcompile` is the wrong place for this. Its purpose
is to cover differences between the compilers and their versions, not to
add all compiler options here. If the intention is to clean this up later,
go ahead.
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Change subject: skl/kbl mainboards: Move PCIe related settings into their device scope
......................................................................
Patch Set 5: Code-Review+1
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Change subject: emulation/qemu-q35: Remove redefine TSEG_SZ_MASK
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/mainboard/emulation/qemu-q35/romstage.c:
https://review.coreboot.org/c/coreboot/+/83386/comment/9590a74d_70b83a20?us… :
PS1, Line 10: #define TSEG_SZ_MASK (3 << 1)
> Copied from src/mainboard/emulation/qemu-q35/memmap.c. Wasn't aware of the define in the header.
Done
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Change subject: emulation/qemu-q35: Remove redefine TSEG_SZ_MASK
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/emulation/qemu-q35/romstage.c:
https://review.coreboot.org/c/coreboot/+/83386/comment/249441ff_92a82b36?us… :
PS1, Line 10: #define TSEG_SZ_MASK (3 << 1)
> Hmmm. @patrick.rudolph@9elements.com added this here just recently. […]
Copied from src/mainboard/emulation/qemu-q35/memmap.c. Wasn't aware of the define in the header.
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Change subject: skl/kbl mainboards: Move PCIe related settings into their device scope
......................................................................
Patch Set 5: Code-Review+1
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Change subject: Documentation: Use pkgconf over pkg-config
......................................................................
Documentation: Use pkgconf over pkg-config
Change-Id: I3e9a92d019854214a5760f705b9cbe3cabe6d2e8
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83157
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
---
M Documentation/tutorial/part1.md
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Martin L Roth: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md
index 88be6ff..cd22b0b 100644
--- a/Documentation/tutorial/part1.md
+++ b/Documentation/tutorial/part1.md
@@ -30,7 +30,7 @@
Debian based distros:
`sudo apt-get install -y bison build-essential curl flex git gnat
-libncurses-dev libssl-dev zlib1g-dev pkg-config`
+libncurses-dev libssl-dev zlib1g-dev pkgconf`
Arch based distros:
`sudo pacman -S base-devel curl git gcc-ada ncurses zlib`
@@ -206,7 +206,7 @@
* `m4, bison, curl, flex, zlib1g-dev, gcc, gnat` and `g++` or `clang`
are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
of the same version.
-* `libssl-dev, pkg-config` are needed to build coreboot image (Step 6).
+* `libssl-dev, pkgconf` are needed to build coreboot image (Step 6).
In particular, `libcrypto` provided by `libssl-dev` package.
If you started with a different distribution or package management
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 6:
(4 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/4a8350f3_f940878a?us… :
PS5, Line 3: config SOC_INTEL_PANTHERLAKE
> The original name was fine. Please change it back. […]
Done
https://review.coreboot.org/c/coreboot/+/83354/comment/36ecc69c_528232e4?us… :
PS5, Line 4: def_bool y
> This must not be enabled by default. […]
Done
https://review.coreboot.org/c/coreboot/+/83354/comment/fabb2b8f_52b601fa?us… :
PS5, Line 29: if SOC_INTEL_PANTHERLAKE
> ```suggestion […]
Done
File src/soc/intel/pantherlake/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83354/comment/05752dd0_689d086c?us… :
PS5, Line 3: CONFIG_SOC_INTEL_PANTHERLAKE_A0
> ```suggestion […]
Done
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:329787286
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pch.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
13 files changed, 1,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/6
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Change subject: skl/kbl mainboards: Move PCIe related settings into their device scope
......................................................................
Patch Set 5: Code-Review+1
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Change subject: emulation/qemu-q35: Remove redefine TSEG_SZ_MASK
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/mainboard/emulation/qemu-q35/romstage.c:
https://review.coreboot.org/c/coreboot/+/83386/comment/0b288e7d_ef453585?us… :
PS1, Line 10: #define TSEG_SZ_MASK (3 << 1)
Hmmm. @patrick.rudolph@9elements.com added this here just recently. Any reason for that?
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