George Burgess has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email )
Change subject: amdfwtool: adjust sign of constant
......................................................................
amdfwtool: adjust sign of constant
This constant is used in a single place; its use triggers one of Clang's
warnings, which may be promoted to an error:
```
amdfwtool.c:1487:27: error: implicit truncation from 'int' to a one-bit
wide bit-field changes value from 1 to -1
[-Werror,-Wsingle-bit-bitfield-constant-conversion]
1487 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
```
`efs_gen.gen` is a 1-bit `int`, so the two values it can have are -1 and
0. Reflect that in the constant.
TEST=Rebuilt coreboot; no warning was emitted.
Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586
Signed-off-by: George Burgess IV <gbiv(a)google.com>
---
M util/amdfwtool/amdfwtool.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83412/1
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 1dc445c..6d1157d 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -148,7 +148,7 @@
} __attribute__((packed));
#define EFS_SECOND_GEN 0
-#define EFS_BEFORE_SECOND_GEN 1
+#define EFS_BEFORE_SECOND_GEN -1
typedef struct _embedded_firmware {
uint32_t signature; /* 0x55aa55aa */
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Change subject: emulation/qemu-q35: Move QEMU specific macros to "q35.h"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> why? do you want to use those macros some place else?
Those macros
`#define SMRAMC 0x9d
#define G_SMRAME (1 << 3)
#define D_LCK (1 << 4)
#define D_CLS (1 << 5)
#define D_OPEN (1 << 6)
#define ESMRAMC 0x9e
#define T_EN (1 << 0)
#define TSEG_SZ_MASK (3 << 1)
#define H_SMRAME (1 << 7)`
are already defined in "q35.h" file.
and "src/mainboard/emulation/qemu-q35/memmap.c" file includes "q35.h", so why not remove macros redefine and move remaining macros to "q35.h"
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Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
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Patch Set 2: Code-Review+2
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Change subject: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
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Patch Set 2: Code-Review+2
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Change subject: Introduce a coreboot Control Block (CCB)
......................................................................
Patch Set 13:
(1 comment)
File util/cbfstool/cbfstool.c:
https://review.coreboot.org/c/coreboot/+/77712/comment/1da4ed7e_1d95cc78?us… :
PS13, Line 730: cbfs_ccb_set_value
> Search for "bootblock.bin" in makefiles. […]
Which approach is broken?
I have provided CBFS and FMAP options as well. Please take a look.
It doesn't affect RoT though, unless you have a locked system, but in that case you probably don't want someone messing with the binary anyway.
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Change subject: mb/google/drallion: Don't enable DPTF PCI device
......................................................................
mb/google/drallion: Don't enable DPTF PCI device
Enabling the DPTF device causes the cmn/block/dtt driver to generate a
2nd TCPU ACPI device in the SSDT, causing the entire SSDT to be ignored
under Windows, leading to many devices (like touchpad/touchscreen) not
working at all.
TEST=build/boot Win11 on google/drallion, verify SSDT able to be parsed,
no duplicate TCPU device, and touchpad/touchscreen work properly.
Change-Id: Ic0e07d9d64c543121aa51a7cfd63fe3686192825
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/83411/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 302a09e..b83eac0 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -232,7 +232,6 @@
device generic 0 on end
end
end
- device ref dptf on end
device ref thermal on end
device ref ish on
chip drivers/intel/ish
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83410?usp=email )
Change subject: mb/google/puff: Use auto fan control
......................................................................
mb/google/puff: Use auto fan control
Set fan control to AUTO at boot for non-ChromeOS builds.
TEST=build/boot Win11, Linux on google/puff (wyvern), verify fan
speed varies with load/CPU temp as expected.
Change-Id: I478cdb95757671d4ecd9c2d45af2aa1d53b4b833
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/puff/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/83410/1
diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index 0abe53a..16f3cb6 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -14,6 +14,7 @@
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
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Change subject: emulation/qemu-q35: Move QEMU specific macros to "q35.h"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
why? do you want to use those macros some place else?
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Change subject: tree: Change set_msip(int, int) to set_msip(uintptr_t, int)
......................................................................
Patch Set 1: Code-Review-2
(1 comment)
Patchset:
PS1:
hartid is a number, not a pointer
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