Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83401?usp=email )
Change subject: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
......................................................................
soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Myst boards.
TEST=untested, but same change as made for Mendocino
Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/phoenix/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
Fred Reitberger: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index be0a022..03edd43 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -130,7 +130,7 @@
APOB_NV_BASE=$(call _tohex,$(call int-subtract, \
$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START)))
-ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y)
+ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy)
# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE.
# Else use RW_MRC_CACHE. This entry will be added in the RO section.
APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE)
--
To view, visit https://review.coreboot.org/c/coreboot/+/83401?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Gerrit-Change-Number: 83401
Gerrit-PatchSet: 3
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83400?usp=email )
Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
......................................................................
soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Skyrim boards.
TEST=build/boot Skyrim (Frostflow), verify RAM training only
run on first boot after flashing.
Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/mendocino/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Fred Reitberger: Looks good to me, approved
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index a72116e..1b96ff1 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -122,7 +122,7 @@
APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
-ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y)
+ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy)
# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE.
# Else use RW_MRC_CACHE. This entry will be added in the RO section.
APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE)
--
To view, visit https://review.coreboot.org/c/coreboot/+/83400?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Gerrit-Change-Number: 83400
Gerrit-PatchSet: 3
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82762?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: console/i2c_smbus: Allow to send data w/o register offset
......................................................................
console/i2c_smbus: Allow to send data w/o register offset
Not every I2C target requires a register address. Not sending one
for every console char saves us a lot of overhead.
Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/console/Kconfig
M src/drivers/smbus/i2c_smbus_console.c
2 files changed, 16 insertions(+), 3 deletions(-)
Approvals:
Angel Pons: Looks good to me, approved
Elyes Haouas: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 30b2862..db71204 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -318,8 +318,16 @@
help
I2C address of the device which logs the data.
+config CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER
+ bool "Write to a specific data register"
+ default y if SC16IS7XX_INIT
+ help
+ Select this to provide a register address that will
+ be sent before every data byte.
+
config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER
hex "Data register address of the I2C logging device"
+ depends on CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER
default 0x00 if SC16IS7XX_INIT
help
This an 8-bit data register.
diff --git a/src/drivers/smbus/i2c_smbus_console.c b/src/drivers/smbus/i2c_smbus_console.c
index d651790..00b5393 100644
--- a/src/drivers/smbus/i2c_smbus_console.c
+++ b/src/drivers/smbus/i2c_smbus_console.c
@@ -13,7 +13,12 @@
void i2c_smbus_console_tx_byte(unsigned char c)
{
- do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE,
- CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS,
- CONFIG_CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER, c);
+ if (CONFIG(CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER)) {
+ do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE,
+ CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS,
+ CONFIG_CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER, c);
+ } else {
+ do_smbus_send_byte(CONFIG_FIXED_SMBUS_IO_BASE,
+ CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, c);
+ }
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/82762?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c
Gerrit-Change-Number: 82762
Gerrit-PatchSet: 3
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Attention is currently required from: Matt DeVillier.
Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83413?usp=email )
Change subject: Update amd_blobs submodule to upstream main
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83413?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff
Gerrit-Change-Number: 83413
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Comment-Date: Wed, 10 Jul 2024 22:50:32 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Attention is currently required from: Filip Lewiński, Krystian Hebel, Maciej Pijanowski, Martin L Roth, Michał Kopeć, Michał Żygowski.
Felix Singer has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/83385?usp=email )
Change subject: payloads/external/iPXE/Makefile: Build iPXE for EFI target if requested
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83385/comment/57fcc116_ed7a9cc2?us… :
PS1, Line 8:
> Please have a look at the other [patch](https://review.coreboot. […]
I see. I don't see an issue with offering an option to build an EFI binary, but it seems this patch is missing a Kconfig option. See my other comment.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83385?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7f247a59a65aeb18a67475d4d543f519af88aeb9
Gerrit-Change-Number: 83385
Gerrit-PatchSet: 2
Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com>
Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com>
Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com>
Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Gerrit-Comment-Date: Wed, 10 Jul 2024 22:00:06 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Comment-In-Reply-To: Filip Lewiński <filip.lewinski(a)3mdeb.com>
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83358?usp=email )
Change subject: autoport: Drop ioapic, ioapic_irq, and lapic handling for devicetree
......................................................................
autoport: Drop ioapic, ioapic_irq, and lapic handling for devicetree
The ioapic and ioapic_irq keywords are no longer valid tokens as of
commit e84b095d3a23 (util/sconfig: Remove unused ioapic and irq
keywords), and the associated driver had previously been removed in
commit ca5a793ec31c (drivers/generic/ioapic: Drop poor implementation).
Thus, drop them from autoport. Also, the IOAPICIRQs map that this code
relied on to generate ioapic_irq entries never seems to have been
populated by any code in any previous commit, so this appears to have
been dead code since autoport was created.
The lapic keyword was removed from sconfig in commit 15d5183e4af7
(util/sconfig: Remove lapic devices from devicetree parsers) so remove
autoport handling for it as well.
Change-Id: Icf2582594b244cf5f726c722eb3a3c12573a2662
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83358
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M util/autoport/main.go
1 file changed, 1 insertion(+), 17 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 18fb694..21dbbf0 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -96,12 +96,6 @@
SaneVendor string
}
-type IOAPICIRQ struct {
- APICID int
- IRQNO [4]int
-}
-
-var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{}
var KconfigBool map[string]bool = map[string]bool{}
var KconfigComment map[string]string = map[string]string{}
var KconfigString map[string]string = map[string]string{}
@@ -366,7 +360,7 @@
func WriteDev(dt *os.File, offset int, alias string, dev DevTreeNode) {
Offset(dt, offset)
switch dev.Chip {
- case "cpu_cluster", "lapic", "domain", "ioapic":
+ case "cpu_cluster", "domain":
fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev)
writeOn(dt, dev)
case "pci", "pnp":
@@ -391,16 +385,6 @@
fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem)
}
- ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}]
- if dev.Chip == "pci" && ok {
- for pin, irq := range ioapic.IRQNO {
- if irq != 0 {
- Offset(dt, offset+1)
- fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq)
- }
- }
- }
-
keys := []string{}
for reg, _ := range dev.Registers {
keys = append(keys, reg)
--
To view, visit https://review.coreboot.org/c/coreboot/+/83358?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Icf2582594b244cf5f726c722eb3a3c12573a2662
Gerrit-Change-Number: 83358
Gerrit-PatchSet: 4
Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>