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(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter
......................................................................
mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter
Fixes a pmc_mux port mapping error introduced in coreboot
commit 4fa8354
Mithrax and felwinter do not have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connectors and USB muxes to be incorrect. The previous patch
attempted to fix this by changing the custom_pld layout. However
this broke USB usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
2 files changed, 26 insertions(+), 26 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 61cb500..8b5dd0d 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -358,13 +358,13 @@
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
- use usb2_port3 as usb2_port
- use tcss_usb3_port3 as usb3_port
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port2 as usb3_port
device generic 2 alias conn2 on end
end
chip drivers/intel/pmc_mux/conn
- use usb2_port2 as usb2_port
- use tcss_usb3_port2 as usb3_port
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
@@ -377,16 +377,16 @@
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
register "usb_lpm_incapable" = "true"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
end
end
end
@@ -398,15 +398,15 @@
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
- device ref usb2_port2 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 61344d7..70a4423 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -306,13 +306,13 @@
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
- use usb2_port3 as usb2_port
- use tcss_usb3_port3 as usb3_port
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port2 as usb3_port
device generic 2 alias conn2 on end
end
chip drivers/intel/pmc_mux/conn
- use usb2_port2 as usb2_port
- use tcss_usb3_port2 as usb3_port
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
@@ -325,16 +325,16 @@
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "usb_lpm_incapable" = "true"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
end
end
end
@@ -346,15 +346,15 @@
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
- device ref usb2_port2 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
@@ -365,7 +365,7 @@
register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
@@ -379,7 +379,7 @@
register "desc" = ""USB3 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb3_port1 on end
end
end
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Angel Pons has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83196?usp=email )
Change subject: util/superiotool: Add extra selectors support
......................................................................
Patch Set 7: Code-Review+1
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