Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email )
Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code
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Patch Set 1:
(1 comment)
File src/southbridge/intel/i82801gx/azalia.c:
https://review.coreboot.org/c/coreboot/+/83504/comment/8bc6c6d9_937db49f?us… :
PS1, Line 27: 0x0f
Not sure why these only use the first 4 bits as the codec mask (the specification uses 15 bits).
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Change subject: security/vboot: Introduce vbnv_platform_init_cmos()
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Patch Set 3: Code-Review+1
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Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83316?usp=email )
Change subject: soc/intel/common/block/gpio/gpio.c: improve GPIO debug infos
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Patch Set 6:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83316/comment/b528ff54_573ac7eb?us… :
PS6, Line 196: printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n",
Why we need 'zu'? Is it a must for size_t?
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Change subject: soc/intel/common/intelblocks/gpio.h: allow specifying the pad ownership
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Patch Set 6:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83315/comment/e3892213_b3f7ae1f?us… :
PS6, Line 125: uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */
can this be covered by the host_own_reg_0?
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Hello Jérémy Compostella, Paul Menzel, Shuo Liu, build bot (Jenkins), جوكر الطويل,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83314?usp=email
to look at the new patch set (#6).
Change subject: soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
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soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/6
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
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Patch Set 6: Code-Review+1
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