July 2024 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: mb/google/brox: Reduce PL values for booting without battery
by Sowmya Aralguppe (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Deepti Deshatty, Eric Herrmann, Karthik Ramasubramanian, Shelley Chen. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83406?usp=email ) Change subject: mb/google/brox: Reduce PL values for booting without battery ...................................................................... Patch Set 6: (2 comments) This change is ready for review. File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83406/comment/e61afefb_6725e22c?us… : PS2, Line 161: soc_config->tdp_pl4 -= POWER_LIMIT_TUNE; > Yes this intentional . […] Acknowledged File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83406/comment/04066cac_c7401902?us… : PS4, Line 96: * +-------------+-----+------+---------+-------+ : * | Max Power(W)| TDP | PL2 | PsysPL2 | PL3/4 | : * +-------------+-----+------+---------+-------+ : * | 30 | 15 | 17 | 25 | 25 | <--- not working yet : * | 45 | 15 | 26 | 38 | 38 | : * | 60 | 15 | 35 | 51 | 51 | : * | 110 | 15 | 55 | 94 | 96 | : * +-------------+-----+------+---------+-------+ : */ > can you please adjust the table to reflect the updated values below? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83406?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0074bfc97c54f07d0b7257393de7c355e36b262 Gerrit-Change-Number: 83406 Gerrit-PatchSet: 6 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 08:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add Audio descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83554?usp=email ) Change subject: mb/google/brya/var/trulo: Add Audio descriptions ...................................................................... mb/google/brya/var/trulo: Add Audio descriptions This patch adds descriptions for Audio device (Speaker, Jack and Mic) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83554 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index aebd1e79..27156dbb 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -84,6 +84,15 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_sdi_enable[1]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -293,5 +302,13 @@ end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Gerrit-Change-Number: 83554 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add eMMC descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83552?usp=email ) Change subject: mb/google/brya/var/trulo: Add eMMC descriptions ...................................................................... mb/google/brya/var/trulo: Add eMMC descriptions This patch adds descriptions for eMMC device (supported mode and DLL tuning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83552 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 49 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index cf01efb..aebd1e79 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -19,6 +19,55 @@ # Enable CNVi BT register "cnvi_bt_core" = "true" + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + #eMMC DLL tuning parameters + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB) register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/83552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Gerrit-Change-Number: 83552 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add fw_config probe for storage devices
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83553?usp=email ) Change subject: mb/google/brya/var/trulo: Add fw_config probe for storage devices ...................................................................... mb/google/brya/var/trulo: Add fw_config probe for storage devices 1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree, to avoid suspend(s0ix) fail issue. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83553 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/Makefile.mk A src/mainboard/google/brya/variants/trulo/fw_config.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 3 files changed, 69 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/Makefile.mk b/src/mainboard/google/brya/variants/trulo/Makefile.mk index 87f515a..ebeabf4 100644 --- a/src/mainboard/google/brya/variants/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/trulo/Makefile.mk @@ -5,4 +5,6 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/trulo/fw_config.c b/src/mainboard/google/brya/variants/trulo/fw_config.c new file mode 100644 index 0000000..2977cb6 --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/fw_config.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned. Exiting...\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } + } +} diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index d603c137..cf01efb 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field STORAGE 30 31 + option STORAGE_EMMC 0 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + option STORAGE_UNKNOWN 3 + end +end chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -202,14 +210,22 @@ end end #I2C5 device ref heci1 on end - device ref emmc on end + device ref emmc on + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_EMMC + end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 on end end + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS end - device ref ufs on end + device ref ufs on + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS + end device ref uart0 on end device ref pch_espi on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/83553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Gerrit-Change-Number: 83553 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add CNVi descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83551?usp=email ) Change subject: mb/google/brya/var/trulo: Add CNVi descriptions ...................................................................... mb/google/brya/var/trulo: Add CNVi descriptions This patch adds descriptions for CNVi WiFi and BT device to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83551 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index febc1de..d603c137 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -8,6 +8,9 @@ # S0ix enable register "s0ix_enable" = "1" + # Enable CNVi BT + register "cnvi_bt_core" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB) register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera @@ -154,6 +157,14 @@ end end device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/83551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Gerrit-Change-Number: 83551 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add LSIO descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83550?usp=email ) Change subject: mb/google/brya/var/trulo: Add LSIO descriptions ...................................................................... mb/google/brya/var/trulo: Add LSIO descriptions This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx) to the device tree. It also includes entries that will generate ACPI code at runtime with LSIO end-point device. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 98 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 03f7f9e..febc1de 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -24,6 +24,67 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Trackpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + device domain 0 on device ref igpu on end device ref tcss_xhci on @@ -93,6 +154,42 @@ end end device ref shared_sram on end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW1_03" + register "detect" = "1" + device i2c 15 on end + end + end #I2C1 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "generic.stop_delay_ms" = "150" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C5 device ref heci1 on end device ref emmc on end device ref ish on @@ -102,6 +199,7 @@ end end device ref ufs on end + device ref uart0 on end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- To view, visit https://review.coreboot.org/c/coreboot/+/83550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Gerrit-Change-Number: 83550 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add TCSS port descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83548?usp=email ) Change subject: mb/google/brya/var/trulo: Add TCSS port descriptions ...................................................................... mb/google/brya/var/trulo: Add TCSS port descriptions This patch adds descriptions for TCSS port, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. Additionally, implement the TCSS PMC MUX programming. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 56d96ff..03f7f9e 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -17,8 +17,28 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB) + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "0" + device domain 0 on device ref igpu on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on @@ -84,8 +104,20 @@ device ref ufs on end device ref pch_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] device pnp 0c09.0 on end end end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Gerrit-Change-Number: 83548 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add USB2/3 port descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83547?usp=email ) Change subject: mb/google/brya/var/trulo: Add USB2/3 port descriptions ...................................................................... mb/google/brya/var/trulo: Add USB2/3 port descriptions This patch adds descriptions for USB2/3 ports, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 61 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 9fba6ae..56d96ff 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -8,11 +8,70 @@ # S0ix enable register "s0ix_enable" = "1" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 (MLB) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB) device domain 0 on device ref igpu on end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end device ref shared_sram on end device ref heci1 on end device ref emmc on end -- To view, visit https://review.coreboot.org/c/coreboot/+/83547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Gerrit-Change-Number: 83547 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Anil Kumar K. Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81920?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I was comparing ALC 711 and ALC 722 (your CL) and felt that only change between those two drivers are .version, .part_id and .class. Additionally, you can refactor the existing ALC 711 code to accommodate both codec (this will save the coding and review effort as well) 1. ``` static struct soundwire_address alc711_address = { #if CONFIG(DRIVERS_SOUNDWIRE_ALC722) .version = SOUNDWIRE_VERSION_1_2, .class = MIPI_CLASS_SDCA .part_id = MIPI_DEV_ID_REALTEK_ALC722, #elif CONFIG(DRIVERS_SOUNDWIRE_ALC711) .version = SOUNDWIRE_VERSION_1_1, .class = MIPI_CLASS_NONE .part_id = MIPI_DEV_ID_REALTEK_ALC711, #else #error "Select correct codec driver" #endif .manufacturer_id = MIPI_MFG_ID_REALTEK, }; ``` 2. ``` config DRIVERS_SOUNDWIRE_ALC_BASE_7XX bool help Base code for Realtek ALC7xxx Codec Soundwire Driver. config DRIVERS_SOUNDWIRE_ALC711 bool select DRIVERS_SOUNDWIRE_ALC_BASE_7XX Soundwire Driver for Realtek ALC711 device config DRIVERS_SOUNDWIRE_ALC722 bool select DRIVERS_SOUNDWIRE_ALC_BASE_7XX help Soundwire Driver for Realtek ALC722 device ``` 3. ``` ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC_BASE_7XX) += alc711.c ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-CC: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 06:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: vc/intel/fsp: Update twinlake FSP headers from v5142.00 to v5222.01
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Ronak Kanabar, V Sowmya, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83404?usp=email ) Change subject: vc/intel/fsp: Update twinlake FSP headers from v5142.00 to v5222.01 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: why don't we use `upstream/TWL.5261.00` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6 Gerrit-Change-Number: 83404 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 06:18:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add Thermal descriptions
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83565?usp=email ) Change subject: mb/google/brya/var/trulo: Add Thermal descriptions ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/trulo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83565/comment/d997772b_a54fb984?us… : PS1, Line 198: register "policies.active" = "{ > > > We need different setting values to control Fan speed for 6W and 15W design, if 6W system has Fan. > > > > > > Note: this is base CL for N/DOrisa to operational and we can always optimise these numbers once we have board in hand. > > > > > > > > Is 6W design Fan based the system? > > > > Yes, we have fan in all the SKUs > > marking resolved as I hope we have an alignment here thanks Sumeet, hopefully the Trulo reaches Intel office, you can update the thermal settings -- To view, visit https://review.coreboot.org/c/coreboot/+/83565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Gerrit-Change-Number: 83565 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 05:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Anastasios Koutian (Code Review) 22 Jul '24

22 Jul '24

Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83270/comment/4669022e_02a607d6?us… : PS8, Line 12: Tested on ThinkPad T420 with the i7-3940XM. > How can this be tested? Please refer to this comment: https://review.coreboot.org/c/coreboot/+/83270/comment/c41532aa_f71a7182/ I tested this with the i7-3940XM, by running a combined stress test for CPU cores and integrated graphics: `$ stress-ng -c 8 --cpu-method matrixprod` `$ furmark --fullscreen --p1080 --demo furmark-gl` With the PL1 clamp disabled, after several minutes of running the two commands simultaneously, the core frequency is 3.0 GHz, graphics frequency is 650 MHz, and package power consumption levels out at ~42 W. When the PL1 clamp is enabled, for the same stress test, core frequency is 2.7 GHz, graphics are at 540 MHz, and package power stabilises at 35 W. -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 8 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 05:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add PnP descriptions
by Sumeet R Pawnikar (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Sumeet R Pawnikar has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83566?usp=email ) Change subject: mb/google/brya/var/trulo: Add PnP descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03 Gerrit-Change-Number: 83566 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 05:40:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add Thermal descriptions
by Sumeet R Pawnikar (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Sumeet R Pawnikar has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83565?usp=email ) Change subject: mb/google/brya/var/trulo: Add Thermal descriptions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Gerrit-Change-Number: 83565 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 05:39:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yidi Lin (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:57:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yidi Lin (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:56:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by SH Kim (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, YH Lin, YH Lin. SH Kim has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83479/comment/d7b6f863_dbddc2f2?us… : PS7, Line 17: BUG=b:353395811 > Can we get this change merged if we don't have more comment? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:51:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by Sumeet R Pawnikar (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, YH Lin, YH Lin. Sumeet R Pawnikar has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: I've checked bug and other comment details. -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:50:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yu-Ping Wu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:39:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yu-Ping Wu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/mainboard/google/rauru/Kconfig: https://review.coreboot.org/c/coreboot/+/83573/comment/c1b14d7a_cba01499?us… : PS7, Line 8: > Move `select VBOOT_MOCK_SECDATA` to VBOOT section Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:37:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/brox: Enable Class-D calibration
by Terry Cheong (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Paul Menzel, Shelley Chen, Vamshi Krishna Gopal. Hello Shelley Chen, Vamshi Krishna Gopal, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82794?usp=email to look at the new patch set (#6). Change subject: mb/google/brox/var/brox: Enable Class-D calibration ...................................................................... mb/google/brox/var/brox: Enable Class-D calibration DC offset of class-D amplifier is 7mV in Brox which is larger than expectation. Add a section in the verb table to enable class-D calibration based on the updated verb table provided by Realtek in b:342506575 comment#6. This improves the offset to be less than 1mV. BUG=b:342506575 BRANCH=main TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \ playing -100dB sine waves. Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Signed-off-by: Terry Cheong <htcheong(a)chromium.org> --- M src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82794/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/82794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Gerrit-Change-Number: 82794 Gerrit-PatchSet: 6 Gerrit-Owner: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brox: Enable Class-D calibration
by Terry Cheong (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Paul Menzel, Shelley Chen, Vamshi Krishna Gopal. Terry Cheong has posted comments on this change by Terry Cheong. ( https://review.coreboot.org/c/coreboot/+/82794?usp=email ) Change subject: mb/google/brox: Enable Class-D calibration ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82794/comment/0c147957_c5b56104?us… : PS2, Line 10: based : on the updated verb table provided by Realtek > Yes. […] Included the bug and comment number as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/82794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Gerrit-Change-Number: 82794 Gerrit-PatchSet: 5 Gerrit-Owner: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Terry Cheong <htcheong(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/brox: Enable Class-D calibration
by Terry Cheong (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Paul Menzel, Vamshi Krishna Gopal. Terry Cheong has posted comments on this change by Terry Cheong. ( https://review.coreboot.org/c/coreboot/+/82794?usp=email ) Change subject: mb/google/brox: Enable Class-D calibration ...................................................................... Patch Set 5: (3 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/82794/comment/28265e77_503a4e50?us… : PS2, Line 9: DC offset of class-D amplifier is larger than expectation in Brox. > Please add concrete values. Added measured values in commit message. https://review.coreboot.org/c/coreboot/+/82794/comment/bc4210f6_71a83dab?us… : PS2, Line 10: based : on the updated verb table provided by Realtek > Is that a comment in the bug report? Yes. Should I include the comment number in the bug report? File src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h: https://review.coreboot.org/c/coreboot/+/82794/comment/e681efa5_38789aa8?us… : PS3, Line 116: Class D > In the commit message summary you use a hyphen: Class-D. Please find out the official spelling. Done. From the datasheet, it should be hyphenated. -- To view, visit https://review.coreboot.org/c/coreboot/+/82794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Gerrit-Change-Number: 82794 Gerrit-PatchSet: 5 Gerrit-Owner: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:17:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/4eeecd55_1d7d7d57?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > Previous discussed in https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83573?usp=email to look at the new patch set (#9). Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... mb/google/rauru: Add MediaTek MT8196 reference board Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e --- A src/mainboard/google/rauru/Kconfig A src/mainboard/google/rauru/Kconfig.name A src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/board_info.txt A src/mainboard/google/rauru/bootblock.c A src/mainboard/google/rauru/chromeos.c A src/mainboard/google/rauru/chromeos.fmd A src/mainboard/google/rauru/devicetree.cb A src/mainboard/google/rauru/mainboard.c A src/mainboard/google/rauru/memlayout.ld A src/mainboard/google/rauru/reset.c A src/mainboard/google/rauru/romstage.c 12 files changed, 157 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83572?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 334 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: add PsysPmax setting
by Shon Wang (Code Review) 22 Jul '24

22 Jul '24

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: add PsysPmax setting ...................................................................... mb/google/brask/var/bujia: add PsysPmax setting test BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/bujia/Makefile.mk A src/mainboard/google/brya/variants/bujia/ramstage.c 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/1 diff --git a/src/mainboard/google/brya/variants/bujia/Makefile.mk b/src/mainboard/google/brya/variants/bujia/Makefile.mk index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/bujia/Makefile.mk +++ b/src/mainboard/google/brya/variants/bujia/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/bujia/ramstage.c b/src/mainboard/google/brya/variants/bujia/ramstage.c new file mode 100644 index 0000000..6aedd00 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/ramstage.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <fw_config.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 90 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 90 }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, 90 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 90 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 90 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in kuldax, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 8A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 8A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 8A = 120W + * For Type-C 20V, the Psys_pmax should be 20v x 8A = 160W + * For a barrel jack, the Psys_pmax should be 20v x 8A = 160W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 160W. Then IMVP9.1 can calculate the current system + * power = 160W * 5A / 8A = 100W, which is the actual system power. + */ +struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 8000, + .bj_volts_mv = 12000 +}; + +void variant_devtree_update(void) +{ + struct ec_params_adc_read req = { + .adc_channel = 4, + }; + struct ec_response_adc_read info; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_ADC_READ, + .cmd_size_in = sizeof(req), + .cmd_data_in = &req, + .cmd_size_out = sizeof(info), + .cmd_data_out = &info, + }; + google_chromeec_command(&cmd); + + psys_config.bj_volts_mv = info.adc_value; + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rex/variants/screebo: Generate RAM IDs
by Subrata Banik (Code Review) 22 Jul '24

22 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83501?usp=email ) Change subject: mb/google/rex/variants/screebo: Generate RAM IDs ...................................................................... mb/google/rex/variants/screebo: Generate RAM IDs Generate 3 Samsung RAM IDs K3KL9L90CM-MGCT Samsung K3KL6L60GM-MGCT Samsung K3KL8L80CM-MGCT Samsung BUG=b:331539447,b:333145301,b:333220620 TEST=Run part_id_gen tool without any errors Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83501 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/screebo/memory/Makefile.mk M src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt 3 files changed, 9 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk index c46681a..5b38bfc 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk @@ -5,4 +5,6 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068, K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt index be70745..b1172e6 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -8,3 +8,6 @@ H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D2DS-026 WT:B 1 (0001) H58G56BK7BX068 1 (0001) +K3KL9L90CM-MGCT 2 (0010) +K3KL6L60GM-MGCT 3 (0011) +K3KL8L80CM-MGCT 1 (0001) diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt index 303f4f4..5757ad7 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -13,3 +13,6 @@ H9JCNNNBK3MLYR-N6E MT62F1G32D2DS-026 WT:B H58G56BK7BX068 +K3KL9L90CM-MGCT +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/83501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3 Gerrit-Change-Number: 83501 Gerrit-PatchSet: 4 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: YH Lin <yueherngl(a)google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by Eric Lai (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar, YH Lin, YH Lin. Eric Lai has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 02:14:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Shuo Liu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/imc/Kconfig: https://review.coreboot.org/c/coreboot/+/83320/comment/65e419e0_187bbc18?us… : PS3, Line 4: bool > I guess you are using an IMC with an SMBUS in it? Would it be possible to be more explicit on naming […] There was an imc.h, but seems no one is using it. soc/intel/common/block/include/intelblocks/imc.h. I'm not sure if all intel imc is with a smbus controller inside it, or this is indicating a special kind of imc with smbus controller inside. If the former case, maybe to name it generally as SOC_INTEL_COMMON_BLOCK_IMC should be okay, but it would be great to add some comment message to indicate its functionality. File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/addb290b_1381597d?us… : PS7, Line 38: static void spd_read(u8 *spd, u8 addr) maybe this can be moved to a generic spd.c, which is implemented either by smbuslib, or the imc/spd.c -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Mon, 22 Jul 2024 02:01:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/common/systemagent: Improve systemagent
by Shuo Liu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Improve systemagent ...................................................................... Patch Set 7: (7 comments) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/83318/comment/5d42ca0e_97c2b477?us… : PS3, Line 78: return; > Yes because the remaining logics are all depends on the value of CAPID_A register. Done https://review.coreboot.org/c/coreboot/+/83318/comment/fa7dfcd0_cd140e1f?us… : PS3, Line 133: .is_limit = CONFIG(TOUUD_LIMIT), > I think there is no hints, it's specified in EDS. […] Done https://review.coreboot.org/c/coreboot/+/83318/comment/bb2742c1_4b4016cb?us… : PS3, Line 176: value = ALIGN_DOWN(value + entry->align, entry->align); > The lower bits of the registers are read as 0s but should be treated as 1s, thus aligning up works. Done File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/83318/comment/fad1118a_33561ef6?us… : PS7, Line 308: return; maybe no need HAVE_MULTIPLE_DOMAINS and the below logic will work. if (!is_domain0(dev->upstream)) return. File src/soc/intel/common/block/systemagent/systemagent_def.h: https://review.coreboot.org/c/coreboot/+/83318/comment/6d5d15ac_390b3438?us… : PS3, Line 73: * IS_LIMIT = If registers/offset indicates address limit or address limit plus 1. > IS_LIMIT indicates whether the lower bits should be treated as 1s or 0s, although they are read as 0 […] Not sure if below pattern fits for all limit cases or not. value | (align - 1) If yes, we can leave 'IS_LIMIT/is_limit'. Otherwise, maybe a renaming will work, e.g. filling_low_bits P.S. limit will not usually indicate address limit + 1 so I think we could be safe to remove that part in the comment block. File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/83318/comment/cb2f33b0_4495d68d?us… : PS3, Line 133: uint32_t tolud = pci_read_config32(SA_DEV_ROOT, TOLUD); > If calling sa_read_map_entry(), we should pass a device to it, but this function may be called befor […] Done https://review.coreboot.org/c/coreboot/+/83318/comment/4eac69ef_523ba9c5?us… : PS3, Line 161: return ALIGN_DOWN((pci_read_config32(SA_DEV_ROOT, TSEG + 4) + > Yes because the lower bits are read as 0s but should be treated as 1s. Can the process is simplified & clarified as: ALIGN_DOWN(tolud, CONFIG_TOLUD_ALIGNMENT) | (CONFIG_TOLUD_ALIGNMENT - 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 01:45:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos
by Shuo Liu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83316?usp=email ) Change subject: soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos ...................................................................... Patch Set 7: Code-Review+1 (2 comments) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/83316/comment/633f735d_62529920?us… : PS6, Line 196: printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", > zu is used to print unsigned size_t. […] Done https://review.coreboot.org/c/coreboot/+/83316/comment/30989beb_0ac5797f?us… : PS6, Line 399: pcr_read32(comm->port, PAD_CFG_OFFSET(config_offset, i))); /* updated value */ > I moved the printk function after pcr_write so that it can print the value after writting. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5 Gerrit-Change-Number: 83316 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 01:19:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership
by Shuo Liu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83315?usp=email ) Change subject: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/include/intelblocks/gpio.h: https://review.coreboot.org/c/coreboot/+/83315/comment/0ae7893d_2d4c71e9?us… : PS7, Line 124: uint16_t pad_own_reg_0; /* offset to Pad Ownership Reg 0 */ it would be great if adding some comments for pad_own_reg_0 and host_own_reg_0 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/83315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Gerrit-Change-Number: 83315 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 01:14:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership
by Shuo Liu (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83315?usp=email ) Change subject: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/soc/intel/common/block/include/intelblocks/gpio.h: https://review.coreboot.org/c/coreboot/+/83315/comment/eed147f3_4b0765d2?us… : PS6, Line 125: uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ > The pad_own_reg_0 is used to indicate whether this pad is owned by host software or Intel Management […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Gerrit-Change-Number: 83315 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 01:13:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by SH Kim (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, YH Lin, YH Lin. SH Kim has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83479/comment/b8f2d7ba_7c8b9861?us… : PS7, Line 17: BUG=b:353395811 > Done. Can we get this change merged if we don't have more comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 00:44:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
by SH Kim (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Dinesh Gehlot, Edward Doan, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Subrata Banik, YH Lin. SH Kim has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email ) Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT ...................................................................... Patch Set 5: (3 comments) File src/mainboard/google/brya/variants/xol/gpio.c: https://review.coreboot.org/c/coreboot/+/83346/comment/24fe8ec9_b64c1b86?us… : PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG), > I'm not sure where that clip came from, but the GPP_F14 gpio is not locked in mainboard/google/brya/ […] LOCK_CONFIG for GPP_F14 has been removed from baseboard/brya due to this: https://partnerissuetracker.corp.google.com/issues/346917118#comment16 And I removed LOCK_CONFIG from this CL after that comment. File src/mainboard/google/brya/variants/xol/gpio.c: https://review.coreboot.org/c/coreboot/+/83346/comment/f77008a8_76217c13?us… : PS5, Line 128: LEVEL > Isn't this signal active-low? There is no LEVEL_LOW or INVERT option for PAD_CFG_GPI_INT macro. I think OS driver can set it's invert property by refering to the ACPI interrupt property from "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F14)" in overridetree.cb. File src/mainboard/google/brya/variants/xol/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83346/comment/4c1a047f_828b9e2c?us… : PS1, Line 347: register "generic.detect" = "1" > Won't this enable the interrupt? (IIRC, the touchpad is powered directly off of a power rail, so no […] Just had some test for the scenario you mentioned. - Keep making touchpad input during booting with 5 times of "reboot" command and 5 times of ec reset - With/without this change, I couldn't find such issue on my test. From the test result, touchpad interrupt before kernel could be another story with the issue we are focussing on this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/83346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Gerrit-Change-Number: 83346 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Edward Doan <edoan(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jul 2024 00:41:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com>

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[M] Change in coreboot[main]: commonlib/device_tree.c: Add read reg property helper
by Maximilian Brune (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner. Hello Arthur Heymans, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83457?usp=email to look at the new patch set (#6). Change subject: commonlib/device_tree.c: Add read reg property helper ...................................................................... commonlib/device_tree.c: Add read reg property helper Add a helper function to read the reg property from an unflattened device tree. It also factors out the common code into a new function called `read_reg_prop`. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I7846eb8af390d709b0757262025cb819e9988699 --- M src/commonlib/device_tree.c M src/commonlib/include/commonlib/device_tree.h 2 files changed, 73 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83457/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/83457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Gerrit-Change-Number: 83457 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: commonlib/device_tree.c: Add read reg property helper
by Maximilian Brune (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner. Hello Arthur Heymans, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83457?usp=email to look at the new patch set (#5). Change subject: commonlib/device_tree.c: Add read reg property helper ...................................................................... commonlib/device_tree.c: Add read reg property helper Add a helper function to read the reg property from an unflattened device tree. It also factors out the common code into a new function called `read_reg_prop`. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I7846eb8af390d709b0757262025cb819e9988699 --- M src/commonlib/device_tree.c M src/commonlib/include/commonlib/device_tree.h 2 files changed, 73 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83457/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Gerrit-Change-Number: 83457 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: commonlib/device_tree.c: Add read reg property helper
by Maximilian Brune (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83457?usp=email ) Change subject: commonlib/device_tree.c: Add read reg property helper ...................................................................... Patch Set 4: (1 comment) File src/commonlib/device_tree.c: https://review.coreboot.org/c/coreboot/+/83457/comment/49c1c3e9_9f01dc58?us… : PS3, Line 1013: size_t count = prop->prop.size / (4 * addr_cells + 4 * size_cells); > Can we factor out everything starting here into a common function that's used by both (dt and fdt)? like this? -- To view, visit https://review.coreboot.org/c/coreboot/+/83457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Gerrit-Change-Number: 83457 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 21 Jul 2024 21:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: commonlib/device_tree.c: Add read reg property helper
by Maximilian Brune (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Arthur Heymans, Maximilian Brune. Hello Arthur Heymans, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83457?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: commonlib/device_tree.c: Add read reg property helper ...................................................................... commonlib/device_tree.c: Add read reg property helper Add a helper function to read the reg property from an unflattened device tree. It also factors out the common code into a new function called `read_reg_prop`. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I7846eb8af390d709b0757262025cb819e9988699 --- M src/commonlib/device_tree.c M src/commonlib/include/commonlib/device_tree.h 2 files changed, 73 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83457/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Gerrit-Change-Number: 83457 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Elyes Haouas (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella. Elyes Haouas has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 21 Jul 2024 20:44:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Arthur Heymans (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Felix Singer, Jérémy Compostella. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83563/comment/4eb877d2_28bb5f2c?us… : PS2, Line 9: No assembly.inc file is being generated by romcc anymore. > Please also mention "The `-I.` was only used in a single place that […] Done. thx -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 19:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Arthur Heymans (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella. Hello Angel Pons, Jérémy Compostella, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83563?usp=email to look at the new patch set (#3). Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... arch/x86/Makefile.mk: Remove obsolete romcc reference No assembly.inc file is being generated by romcc anymore. The -I. was only used in a single place that can use the common -Isrc instead. Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.mk M src/northbridge/intel/sandybridge/mrc_wrapper.S 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/83563/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yidi Lin (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/rauru/Kconfig: https://review.coreboot.org/c/coreboot/+/83573/comment/f8d41fb8_8d6d1381?us… : PS7, Line 8: > ``` […] Move `select VBOOT_MOCK_SECDATA` to VBOOT section -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 14:52:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Hung-Te Lin (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/16f23587_4cc0a255?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > Approaches should be evaluated and changed. […] Previous discussed in https://review.coreboot.org/c/coreboot/+/58640 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 11:29:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: device/azalia: Clear busy bit after failed verb command
by Nico Huber (Code Review) 21 Jul '24

21 Jul '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83592?usp=email ) Change subject: device/azalia: Clear busy bit after failed verb command ...................................................................... device/azalia: Clear busy bit after failed verb command The spec tells us to clear the busy bit manually after a timeout. Do that and wait immediately, to detect further issues early. Also fix some related comments and prints: Failures shouldn't be debug messa- ges. And we are talking to the PIO interface of the controller, not the codec. So this was never about the codec being ready. Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/azalia_device.c 1 file changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83592/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 4eed489..d39ef51 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -155,10 +155,8 @@ } /* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. + * Wait 50usec for the controller to indicate it is ready. */ - static int wait_for_ready(u8 *base) { struct stopwatch sw; @@ -179,7 +177,6 @@ * Wait for the codec to indicate that it accepted the previous command. * No response would imply that the codec is non-operative. */ - static int wait_for_valid(u8 *base) { struct stopwatch sw; @@ -206,6 +203,16 @@ udelay(1); } + /* + * HDA spec 1.0a "3.4.3 Offset 68h: Immediate Command Status" + * tells us to clear the busy bit explicitly, then poll until + * the controller is ready. + */ + write32(base + HDA_ICII_REG, 0); + if (wait_for_ready(base) < 0) { + printk(BIOS_WARNING, "azalia_audio: controller is unresponsive.\n"); + return -2; + } return -1; } @@ -238,7 +245,7 @@ static bool codec_is_operative(u8 *base, const int addr) { if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, "azalia_audio: codec #%d not ready\n", addr); + printk(BIOS_WARNING, "azalia_audio: controller not ready\n"); return false; } @@ -246,7 +253,7 @@ write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, "azalia_audio: codec #%d not valid\n", addr); + printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr); return false; } return true; -- To view, visit https://review.coreboot.org/c/coreboot/+/83592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06 Gerrit-Change-Number: 83592 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: mb/google/dedede/var/awasuki: Initialise overridetree
by Weimin Wu (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dolan Liu, Eric Lai, Karthik Ramasubramanian, Lawrence Chang. Weimin Wu has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/83496?usp=email ) Change subject: mb/google/dedede/var/awasuki: Initialise overridetree ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/dedede/variants/awasuki/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83496/comment/168420b1_d2040751?us… : PS6, Line 21: #| I2C1 | Disable | : #| I2C2 | Touchscreen | : #| I2C3 | Disable > Also you need to do disable I2C in FSP config like below: […] Done https://review.coreboot.org/c/coreboot/+/83496/comment/656a34d2_a6154df7?us… : PS6, Line 204: device pci 1c.7 on : chip drivers/wifi/generic : register "wake" = "GPE0_DW2_03" : device pci 00.0 on end : end > Does this board also support external/discrete Wifi? You need this only when discrete Wifi is used. Yes, need to support RTL8852BE PCIe Wifi module. -- To view, visit https://review.coreboot.org/c/coreboot/+/83496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Gerrit-Change-Number: 83496 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 09:46:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: mb/google/dedede/var/awasuki: Initialise overridetree
by Weimin Wu (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dolan Liu, Eric Lai, Lawrence Chang, Weimin Wu. Hello Dolan Liu, Eric Lai, Karthik Ramasubramanian, Lawrence Chang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83496?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Dolan Liu, Verified+1 by build bot (Jenkins) Change subject: mb/google/dedede/var/awasuki: Initialise overridetree ...................................................................... mb/google/dedede/var/awasuki: Initialise overridetree Initialise overridetree based on the schematics revision 20240715. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/awasuki/Makefile.mk M src/mainboard/google/dedede/variants/awasuki/overridetree.cb A src/mainboard/google/dedede/variants/awasuki/ramstage.c 4 files changed, 212 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83496/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Gerrit-Change-Number: 83496 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com>

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[XS] Change in coreboot[main]: mb/lenovo/t420: Use vendor default power limits
by Paul Menzel (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Anastasios Koutian. Paul Menzel has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83280?usp=email ) Change subject: mb/lenovo/t420: Use vendor default power limits ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83280/comment/c87e6759_1dca8886?us… : PS6, Line 10: How can users test the effects? File src/mainboard/lenovo/t420/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83280/comment/91015e9d_8b7e7e69?us… : PS6, Line 25: register "pp1_current_limit" = "32" Where did you get the values from? -- To view, visit https://review.coreboot.org/c/coreboot/+/83280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b Gerrit-Change-Number: 83280 Gerrit-PatchSet: 6 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 09:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
by Paul Menzel (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Anastasios Koutian. Paul Menzel has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email ) Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83271/comment/898e5769_b7324b75?us… : PS8, Line 8: Can you elaborate? https://review.coreboot.org/c/coreboot/+/83271/comment/174fd651_1ab16dc5?us… : PS8, Line 10: New message might be logged: printk(BIOS_INFO, "%s: Programmable ratio limit for turbo mode is disabled\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/83271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Gerrit-Change-Number: 83271 Gerrit-PatchSet: 8 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 09:04:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Paul Menzel (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Anastasios Koutian. Paul Menzel has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83270/comment/2f333cac_ecf52c82?us… : PS8, Line 12: Tested on ThinkPad T420 with the i7-3940XM. How can this be tested? -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 8 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 09:02:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Paul Menzel (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/72a53031_ae6eb3bb?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > Certainly, this has been the longstanding MediaTek SOC maintenance approach. […] Approaches should be evaluated and changed. Only because nobody spotted/mentioned/commented this before, doesn’t mean it was the best way. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 07:25:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add Thermal descriptions
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Sumeet R Pawnikar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83565?usp=email ) Change subject: mb/google/brya/var/trulo: Add Thermal descriptions ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/trulo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83565/comment/cfb02f57_72657095?us… : PS1, Line 198: register "policies.active" = "{ > > We need different setting values to control Fan speed for 6W and 15W design, if 6W system has Fan. > > > Note: this is base CL for N/DOrisa to operational and we can always optimise these numbers once we have board in hand. > > > > > Is 6W design Fan based the system? > > Yes, we have fan in all the SKUs marking resolved as I hope we have an alignment here -- To view, visit https://review.coreboot.org/c/coreboot/+/83565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Gerrit-Change-Number: 83565 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 07:15:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled setting
by Felix Singer (Code Review) 21 Jul '24

21 Jul '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82994?usp=email ) Change subject: soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled setting ...................................................................... soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled setting Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82994 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/meteorlake/chip.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 7168369..b75cbba 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -346,7 +346,6 @@ */ uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS]; - uint8_t PmTimerDisabled; /* * SerialIO device mode selection: * PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/82994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Gerrit-Change-Number: 82994 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: [wip C11 to C23] use nullptr & nullptr_t
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Alexander Couzens, Andrey Petrov, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Erik van den Bogaert, Evgeny Zinoviev, Felix Held, Forest Mittelberg, Frans Hendriks, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jeremy Soller, Johnny Lin, Jonathan Zhang, Jonathon Hall, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Philipp Hug, Piotr Król, Ron Minnich, Ronak Kanabar, Sean Rhodes, Shuo Liu, Subrata Banik, Sumeet R Pawnikar, Tarun, Tim Chu, Tim Crawford, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu. Eric Lai has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83585?usp=email ) Change subject: [wip C11 to C23] use nullptr & nullptr_t ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Could you help tear down the change, too many to check one by one. -- To view, visit https://review.coreboot.org/c/coreboot/+/83585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie21b10251d72adee93c25c34ea5387c48d341f01 Gerrit-Change-Number: 83585 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai 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[S] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Use boolean type where applicable
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Martin L Roth, Marvin Evers, Michael Strosche, Subrata Banik, Tarun, Tarun Tuli. Eric Lai has posted comments on this change by Michael Strosche. ( https://review.coreboot.org/c/coreboot/+/77374?usp=email ) Change subject: soc/intel/meteorlake/chip.h: Use boolean type where applicable ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: Echo to Elyes. -- To view, visit https://review.coreboot.org/c/coreboot/+/77374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Gerrit-Change-Number: 77374 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:54:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled setting
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Marvin Evers, Nico Huber, Subrata Banik, Tarun. Eric Lai has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/82994?usp=email ) Change subject: soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled setting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Gerrit-Change-Number: 82994 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:54:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add PnP descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83566?usp=email ) Change subject: mb/google/brya/var/trulo: Add PnP descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03 Gerrit-Change-Number: 83566 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:31:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add Thermal descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83565?usp=email ) Change subject: mb/google/brya/var/trulo: Add Thermal descriptions ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Gerrit-Change-Number: 83565 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:31:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add Audio descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83554?usp=email ) Change subject: mb/google/brya/var/trulo: Add Audio descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Gerrit-Change-Number: 83554 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:31:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add eMMC descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83552?usp=email ) Change subject: mb/google/brya/var/trulo: Add eMMC descriptions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Gerrit-Change-Number: 83552 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:30:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add CNVi descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83551?usp=email ) Change subject: mb/google/brya/var/trulo: Add CNVi descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Gerrit-Change-Number: 83551 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:30:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add LSIO descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83550?usp=email ) Change subject: mb/google/brya/var/trulo: Add LSIO descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Gerrit-Change-Number: 83550 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:30:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add TCSS port descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83548?usp=email ) Change subject: mb/google/brya/var/trulo: Add TCSS port descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Gerrit-Change-Number: 83548 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:29:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add USB2/3 port descriptions
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83547?usp=email ) Change subject: mb/google/brya/var/trulo: Add USB2/3 port descriptions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Gerrit-Change-Number: 83547 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Add fw_config probe for storage devices
by Eric Lai (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83553?usp=email ) Change subject: mb/google/brya/var/trulo: Add fw_config probe for storage devices ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Gerrit-Change-Number: 83553 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:29:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add minimal devicetree entries to boot
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83546?usp=email ) Change subject: mb/google/brya/var/trulo: Add minimal devicetree entries to boot ...................................................................... mb/google/brya/var/trulo: Add minimal devicetree entries to boot This patch adds minimal device entries and chip configs for Trulo overridetree.cb to boot. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 26 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 9285c33..9fba6ae 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,8 +1,32 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_B" + register "pmc_gpe0_dw2" = "GPP_F" + + # S0ix enable + register "s0ix_enable" = "1" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 - device domain 0 on - end + device domain 0 on + device ref igpu on end + device ref shared_sram on end + device ref heci1 on end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83546?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Gerrit-Change-Number: 83546 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brya: Centralize EC configuration in trulo baseboard
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83544?usp=email ) Change subject: mb/google/brya: Centralize EC configuration in trulo baseboard ...................................................................... mb/google/brya: Centralize EC configuration in trulo baseboard This change moves the EC configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h M src/mainboard/google/brya/variants/orisa/include/variant/ec.h 2 files changed, 67 insertions(+), 77 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h index 5ae5064..145035a 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h @@ -7,12 +7,71 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -/* TODO: Set the correct values */ -#define MAINBOARD_EC_SCI_EVENTS 0 -#define MAINBOARD_EC_SMI_EVENTS 0 -#define MAINBOARD_EC_S5_WAKE_EVENTS 0 -#define MAINBOARD_EC_S3_WAKE_EVENTS 0 -#define MAINBOARD_EC_S0IX_WAKE_EVENTS 0 -#define MAINBOARD_EC_LOG_EVENTS 0 +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. AC Connect/Disconnect + * 4. Key press + * 5. Mode change + * 6. Low battery + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ #endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h index 877176c..7a2a6ff 100644 --- a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h @@ -3,75 +3,6 @@ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <variant/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3/S0ix with: - * 1. Lid open - * 2. Power button - * 3. AC Connect/Disconnect - * 4. Key press - * 5. Mode change - * 6. Low battery - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ +#include <baseboard/ec.h> #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Gerrit-Change-Number: 83544 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya: Centralize GPIO configuration in trulo baseboard
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83545?usp=email ) Change subject: mb/google/brya: Centralize GPIO configuration in trulo baseboard ...................................................................... mb/google/brya: Centralize GPIO configuration in trulo baseboard This change moves the GPIO configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h M src/mainboard/google/brya/variants/orisa/include/variant/gpio.h 2 files changed, 13 insertions(+), 20 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h index 9ca9ee7..6bfcc81 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h @@ -6,10 +6,17 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* TODO: Set the correct values */ -#define EC_SCI_GPI 0 -#define GPIO_PCH_WP 0 -#define GPIO_EC_IN_RW 0 -#define GPIO_SLP_S0_GATE 0 +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */ +#define GPE_EC_WAKE GPE0_DW2_17 +/* WP signal to PCH */ +#define GPIO_PCH_WP GPP_E3 +/* EC in RW or RO */ +#define GPIO_EC_IN_RW GPP_F18 +/* GPIO IRQ for tight timestamps, MKBP interrupts */ +#define EC_SYNC_IRQ GPD2_IRQ +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_H18 #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h index c362383..c4fe342 100644 --- a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h @@ -3,20 +3,6 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI -/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */ -#define GPE_EC_WAKE GPE0_DW2_17 -/* WP signal to PCH */ -#define GPIO_PCH_WP GPP_E3 -/* EC in RW or RO */ -#define GPIO_EC_IN_RW GPP_F18 -/* GPIO IRQ for tight timestamps, MKBP interrupts */ -#define EC_SYNC_IRQ GPD2_IRQ -/* Used to gate SoC's SLP_S0# signal */ -#define GPIO_SLP_S0_GATE GPP_H18 +#include <baseboard/gpio.h> #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Gerrit-Change-Number: 83545 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83543?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant ...................................................................... mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as this board design won't stuff MEM strap GPIO hence, sets the static SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/trulo/memory.c 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 95107c9..a5bae12 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -550,6 +550,7 @@ config BOARD_GOOGLE_TRULO select BOARD_GOOGLE_BASEBOARD_TRULO + select SKIP_RAM_ID_STRAPS select SOC_INTEL_TWINLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION @@ -1000,4 +1001,16 @@ int default 33 +config SKIP_RAM_ID_STRAPS + bool + default n + help + Enable this option if the board variant does not rely on MEM Strap GPIOs to determine the SPD ID. + + This is typically the case when the DRAM part is fixed (only one type is used). + In such board designs, enabling this option will bypass the reading of MEM Strap GPIOs + and instead use a static SPD ID number. + + If unsure, leave this option disabled. + endif # BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/variants/trulo/memory.c b/src/mainboard/google/brya/variants/trulo/memory.c index a6f16db..062854e 100644 --- a/src/mainboard/google/brya/variants/trulo/memory.c +++ b/src/mainboard/google/brya/variants/trulo/memory.c @@ -76,6 +76,9 @@ int variant_memory_sku(void) { + if (CONFIG(SKIP_RAM_ID_STRAPS)) + return 0; /* SPD ID: 0 - MT62F512M32D2DR-031 WT:B */ + /* * Memory configuration board straps * GPIO_MEM_CONFIG_0 GPP_E2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054 Gerrit-Change-Number: 83543 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brya/var/trulo: Populate DRAM configuration parameters
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83541?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/trulo: Populate DRAM configuration parameters ...................................................................... mb/google/brya/var/trulo: Populate DRAM configuration parameters This patch adds key DRAM configuration parameters as below: - Rcomp - DQ byte map - DQS CPU<>DRAM map - ECT - CCC Mapping - SPD Index Source: Trulo Schematics Rev0.5 (dated June'24) BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/trulo/Makefile.mk A src/mainboard/google/brya/variants/trulo/memory.c 2 files changed, 113 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/Makefile.mk b/src/mainboard/google/brya/variants/trulo/Makefile.mk index c3c135b..87f515a 100644 --- a/src/mainboard/google/brya/variants/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/trulo/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/trulo/memory.c b/src/mainboard/google/brya/variants/trulo/memory.c new file mode 100644 index 0000000..a6f16db --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/memory.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E2 + * GPIO_MEM_CONFIG_1 GPP_E1 + * GPIO_MEM_CONFIG_2 GPP_E12 + * GPIO_MEM_CONFIG_3 NC + */ + gpio_t spd_gpios[] = { + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051 Gerrit-Change-Number: 83541 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031)
by Subrata Banik (Code Review) 21 Jul '24

21 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83539?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031) ...................................................................... mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031) This patch adds Micron Technology LPDDR5 DRAM (part: MT62F512M32D2DR-031) for Trulo. Make use of spd_tools to generate SPD file after following the below steps: 1. make -C util/spd_tools 2. ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt Output files are: 1. dram_id.generated.txt 2. Makefile.mk BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Id35f6b57b716375abb66db187413f0f82361d962 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/trulo/memory/Makefile.mk M src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 3 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk b/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk index 850a62c..5cb4476 100644 --- a/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build204585115/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt index 8ce2480..8790f22 100644 --- a/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build204585115/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt index 2499005..fc41c85 100644 --- a/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/83539?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id35f6b57b716375abb66db187413f0f82361d962 Gerrit-Change-Number: 83539 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add minimal devicetree entries to boot
by Dinesh Gehlot (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83546?usp=email ) Change subject: mb/google/brya/var/trulo: Add minimal devicetree entries to boot ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83546?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Gerrit-Change-Number: 83546 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 20 Jul 2024 22:40:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya: Centralize EC configuration in trulo baseboard
by Dinesh Gehlot (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Amanda Huang, Kapil Porwal, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83544?usp=email ) Change subject: mb/google/brya: Centralize EC configuration in trulo baseboard ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Gerrit-Change-Number: 83544 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 20 Jul 2024 22:39:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya: Centralize GPIO configuration in trulo baseboard
by Dinesh Gehlot (Code Review) 21 Jul '24

21 Jul '24

Attention is currently required from: Amanda Huang, Kapil Porwal, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83545?usp=email ) Change subject: mb/google/brya: Centralize GPIO configuration in trulo baseboard ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Gerrit-Change-Number: 83545 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Amanda Huang <jadequeen0820(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 20 Jul 2024 22:37:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: [wip C11 to C23] use nullptr & nullptr_t
by Elyes Haouas (Code Review) 20 Jul '24

20 Jul '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83585?usp=email ) Change subject: [wip C11 to C23] use nullptr & nullptr_t ...................................................................... [wip C11 to C23] use nullptr & nullptr_t Change-Id: Ie21b10251d72adee93c25c34ea5387c48d341f01 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/coreinfo/bootlog_module.c M payloads/coreinfo/cbfs_module.c M payloads/coreinfo/coreinfo.c M payloads/coreinfo/cpuinfo_module.c M payloads/coreinfo/timestamps_module.c M payloads/libpayload/Makefile M payloads/libpayload/arch/arm/main.c M payloads/libpayload/arch/arm/virtual.c M payloads/libpayload/arch/arm64/main.c M payloads/libpayload/arch/arm64/mmu.c M payloads/libpayload/arch/x86/main.c M payloads/libpayload/curses/PDCurses/curses.h M payloads/libpayload/curses/PDCurses/demos/newdemo.c M payloads/libpayload/curses/PDCurses/demos/testcurs.c M payloads/libpayload/curses/PDCurses/demos/tui.c M payloads/libpayload/curses/PDCurses/demos/tuidemo.c M payloads/libpayload/curses/PDCurses/demos/worm.c M payloads/libpayload/curses/PDCurses/doc/manext.c M payloads/libpayload/curses/PDCurses/dos/pdcclip.c M payloads/libpayload/curses/PDCurses/dos/pdcscrn.c M payloads/libpayload/curses/PDCurses/os2/pdcclip.c M payloads/libpayload/curses/PDCurses/os2/pdckbd.c M payloads/libpayload/curses/PDCurses/os2/pdcscrn.c M payloads/libpayload/curses/PDCurses/pdcurses/bkgd.c M payloads/libpayload/curses/PDCurses/pdcurses/border.c M payloads/libpayload/curses/PDCurses/pdcurses/getyx.c M payloads/libpayload/curses/PDCurses/pdcurses/inch.c M payloads/libpayload/curses/PDCurses/pdcurses/initscr.c M payloads/libpayload/curses/PDCurses/pdcurses/kernel.c M payloads/libpayload/curses/PDCurses/pdcurses/mouse.c M payloads/libpayload/curses/PDCurses/pdcurses/pad.c M payloads/libpayload/curses/PDCurses/pdcurses/panel.c M payloads/libpayload/curses/PDCurses/pdcurses/scanw.c M payloads/libpayload/curses/PDCurses/pdcurses/scr_dump.c M payloads/libpayload/curses/PDCurses/pdcurses/slk.c M payloads/libpayload/curses/PDCurses/pdcurses/terminfo.c M payloads/libpayload/curses/PDCurses/pdcurses/util.c M payloads/libpayload/curses/PDCurses/pdcurses/window.c M payloads/libpayload/curses/PDCurses/sdl1/pdcclip.c M payloads/libpayload/curses/PDCurses/sdl1/pdcscrn.c M payloads/libpayload/curses/PDCurses/win32/pdcclip.c M payloads/libpayload/curses/PDCurses/win32/pdcscrn.c M payloads/libpayload/curses/PDCurses/x11/ScrollBox.c M payloads/libpayload/curses/PDCurses/x11/ScrollBox.h M payloads/libpayload/curses/PDCurses/x11/pdckbd.c M payloads/libpayload/curses/PDCurses/x11/pdcscrn.c M payloads/libpayload/curses/PDCurses/x11/x11.c M payloads/libpayload/curses/curses.h M payloads/libpayload/curses/curses.priv.h M payloads/libpayload/curses/form/fld_arg.c M payloads/libpayload/curses/form/fld_def.c M payloads/libpayload/curses/form/fld_dup.c M payloads/libpayload/curses/form/fld_ftlink.c M payloads/libpayload/curses/form/fld_link.c M payloads/libpayload/curses/form/fld_newftyp.c M payloads/libpayload/curses/form/fld_type.c M payloads/libpayload/curses/form/fld_user.c M payloads/libpayload/curses/form/form.priv.h M payloads/libpayload/curses/form/frm_def.c M payloads/libpayload/curses/form/frm_driver.c M payloads/libpayload/curses/form/frm_hook.c M payloads/libpayload/curses/form/frm_req_name.c M payloads/libpayload/curses/form/frm_user.c M payloads/libpayload/curses/form/fty_alnum.c M payloads/libpayload/curses/form/fty_alpha.c M payloads/libpayload/curses/form/fty_enum.c M payloads/libpayload/curses/form/fty_generic.c M payloads/libpayload/curses/form/fty_int.c M payloads/libpayload/curses/form/fty_ipv4.c M payloads/libpayload/curses/form/fty_num.c M payloads/libpayload/curses/form/fty_regex.c M payloads/libpayload/curses/keyboard.c M payloads/libpayload/curses/menu/m_hook.c M payloads/libpayload/curses/menu/m_item_cur.c M payloads/libpayload/curses/menu/m_item_nam.c M payloads/libpayload/curses/menu/m_item_new.c M payloads/libpayload/curses/menu/m_item_opt.c M payloads/libpayload/curses/menu/m_item_use.c M payloads/libpayload/curses/menu/m_items.c M payloads/libpayload/curses/menu/m_new.c M payloads/libpayload/curses/menu/m_opts.c M payloads/libpayload/curses/menu/m_pattern.c M payloads/libpayload/curses/menu/m_req_name.c M payloads/libpayload/curses/menu/m_sub.c M payloads/libpayload/curses/menu/m_userptr.c M payloads/libpayload/curses/menu/m_win.c M payloads/libpayload/curses/pdcurses-backend/pdckbd.c M payloads/libpayload/curses/pdcurses-backend/pdcscrn.c M payloads/libpayload/curses/tinycurses.c M payloads/libpayload/drivers/cbmem_console.c M payloads/libpayload/drivers/hid.c M payloads/libpayload/drivers/i8042/i8042.c M payloads/libpayload/drivers/i8042/keyboard.c M payloads/libpayload/drivers/mouse_cursor.c M payloads/libpayload/drivers/options.c M payloads/libpayload/drivers/serial/ipq40xx.c M payloads/libpayload/drivers/serial/qcs405.c M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/storage/ata.c M payloads/libpayload/drivers/storage/atapi.c M payloads/libpayload/drivers/storage/nvme.c M payloads/libpayload/drivers/storage/storage.c M payloads/libpayload/drivers/udc/chipidea.c M payloads/libpayload/drivers/udc/dwc2.c M payloads/libpayload/drivers/udc/udc.c M payloads/libpayload/drivers/usb/dwc2.c M payloads/libpayload/drivers/usb/dwc2_rh.c M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/generic_hub.c M payloads/libpayload/drivers/usb/ohci.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/drivers/usb/uhci_rh.c M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/drivers/usb/usb_dev.c M payloads/libpayload/drivers/usb/usbhid.c M payloads/libpayload/drivers/usb/usbhub.c M payloads/libpayload/drivers/usb/usbinit.c M payloads/libpayload/drivers/usb/usbmsc.c M payloads/libpayload/drivers/usb/xhci.c M payloads/libpayload/drivers/usb/xhci_debug.c M payloads/libpayload/drivers/usb/xhci_devconf.c M payloads/libpayload/drivers/usb/xhci_rh.c M payloads/libpayload/drivers/video/font8x16.c M payloads/libpayload/drivers/video/graphics.c M payloads/libpayload/include/arm/arch/types.h M payloads/libpayload/include/arm64/arch/types.h M payloads/libpayload/include/cbfs.h M payloads/libpayload/include/getopt.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/mock/arch/types.h M payloads/libpayload/include/queue.h M payloads/libpayload/include/x86/arch/types.h M payloads/libpayload/libc/args.c M payloads/libpayload/libc/getopt_long.c M payloads/libpayload/libc/lib.c M payloads/libpayload/libc/malloc.c M payloads/libpayload/libc/printf.c M payloads/libpayload/libc/readline.c M payloads/libpayload/libc/string.c M payloads/libpayload/libc/time.c M payloads/libpayload/libcbfs/cbfs.c M payloads/libpayload/liblz4/lz4_wrapper.c M payloads/libpayload/libpci/libpci.c M payloads/libpayload/tests/Makefile.mk M payloads/libpayload/tests/cbfs-x86-test.c M payloads/libpayload/tests/drivers/speaker-test.c M payloads/libpayload/tests/libc/fmap_locate_area-test.c M payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c M payloads/libpayload/tests/libcbfs/cbfs-verification-test.c M payloads/linuxcheck/linuxcheck.c M payloads/nvramcui/nvramcui.c M src/acpi/acpi.c M src/acpi/acpi_gic.c M src/acpi/acpi_pptt.c M src/acpi/acpigen.c M src/acpi/acpigen_dsm.c M src/acpi/acpigen_pci_root_resource_producer.c M src/acpi/acpigen_ps2_keybd.c M src/acpi/device.c M src/acpi/gnvs.c M src/arch/arm/fit_payload.c M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/exception.c M src/arch/arm64/bl31.c M src/arch/arm64/fit_payload.c M src/arch/arm64/smc.c M src/arch/riscv/arch_timer.c M src/arch/riscv/fit_payload.c M src/arch/riscv/smp.c M src/arch/x86/acpi_bert_storage.c M src/arch/x86/breakpoint.c M src/arch/x86/cpu.c M src/arch/x86/ebda.c M src/arch/x86/include/arch/cpu.h M src/arch/x86/null_breakpoint.c M src/arch/x86/postcar_loader.c M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/elog.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/bsd/lz4_wrapper.c M src/commonlib/device_tree.c M src/commonlib/fsp_relocate.c M src/commonlib/include/commonlib/iobuf.h M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/include/commonlib/region.h M src/commonlib/iobuf.c M src/commonlib/mem_pool.c M src/commonlib/region.c M src/commonlib/storage/mmc.c M src/commonlib/storage/pci_sdhci.c M src/commonlib/storage/sd.c M src/commonlib/storage/sd_mmc.c M src/commonlib/storage/sdhci.c M src/commonlib/storage/sdhci_adma.c M src/commonlib/storage/storage.c M src/commonlib/storage/storage_erase.c M src/commonlib/storage/storage_write.c M src/console/console.c M src/console/printk.c M src/console/vtxprintf.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/backup_default_smm.c M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/smi_trigger.c M src/cpu/x86/smm/pci_resource_store.c M src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/tseg_region.c M src/device/cardbus_device.c M src/device/cpu_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/dram/spd.c M src/device/gpio.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/x86emu/debug.c M src/device/oprom/x86emu/decode.c M src/device/oprom/x86emu/ops2.c M src/device/oprom/x86emu/sys.c M src/device/oprom/yabel/biosemu.h M src/device/oprom/yabel/compat/functions.c M src/device/oprom/yabel/interrupt.c M src/device/oprom/yabel/io.c M src/device/oprom/yabel/vbe.c M src/device/pci_class.c M src/device/pci_device.c M src/device/pci_ops.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pnp_device.c M src/device/resource_allocator_common.c M src/device/resource_allocator_v4.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/heapmanager.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/state_machine.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_main.c M src/drivers/aspeed/common/ast_mode.c M src/drivers/crb/tis.c M src/drivers/efi/efivars.c M src/drivers/efi/efivars.h M src/drivers/elog/elog.c M src/drivers/emulation/qemu/bochs.c M src/drivers/generic/cbfs-uuid/cbfs-uuid.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/i2c/designware/dw_i2c.h M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/fsp_relocate.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp1_1/temp_ram_exit.c M src/drivers/intel/fsp1_1/vbt.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_if.c M src/drivers/ipmi/ipmi_ops.c M src/drivers/ipmi/ipmi_ops_premem.c M src/drivers/ipmi/ocp/ipmi_ocp_romstage.c M src/drivers/ipmi/ocp/ipmi_sel.c M src/drivers/ipmi/supermicro_oem.c M src/drivers/mrc_cache/mrc_cache.c M src/drivers/net/atl1e.c M src/drivers/net/r8168.c M src/drivers/ocp/dmi/smbios.c M src/drivers/pc80/pc/keyboard.c M src/drivers/pc80/rtc/option.c M src/drivers/pc80/tpm/tis.c M src/drivers/pc80/vga/vga.c M src/drivers/pc80/vga/vga_palette.c M src/drivers/pcie/generic/generic.c M src/drivers/pcie/rtd3/device/chip.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/smmstore/store.c M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc5682/alc5682.c M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/cs42l42/cs42l42.c M src/drivers/soundwire/max98363/max98363.c M src/drivers/soundwire/max98373/max98373.c M src/drivers/spi/boot_device_rw_nommap.c M src/drivers/spi/cbfs_spi.c M src/drivers/spi/issi.c M src/drivers/spi/spi-generic.c M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_sdcard.c M src/drivers/spi/spiconsole.c M src/drivers/spi/sst.c M src/drivers/spi/tpm/tis.c M src/drivers/spi/tpm/tpm.c M src/drivers/spi/winbond.c M src/drivers/tpm/ppi.c M src/drivers/tpm/ppi_stub.c M src/drivers/tpm/tpm.c M src/drivers/usb/acpi/usb_acpi.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/gadget.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd.h M src/drivers/wifi/generic/acpi.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/51nb/npce985la0dx/npce985la0dx.c M src/ec/compal/ene932/ec.c M src/ec/dasharo/ec/dasharo_ec.h M src/ec/dell/mec5035/mec5035.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_acpi.c M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/ec_spi.c M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.c M src/ec/google/wilco/ec.h M src/ec/kontron/it8516e/ec.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/roda/it8518/ec.c M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c M src/ec/system76/ec/system76_ec.h M src/include/acpi/acpi_gnvs.h M src/include/acpi/acpigen.h M src/include/boot/tables.h M src/include/bootmem.h M src/include/bootstate.h M src/include/cbfs.h M src/include/cbmem.h M src/include/cpu/intel/microcode.h M src/include/device/device.h M src/include/device/dram/ddr2.h M src/include/device/dram/ddr3.h M src/include/device/i2c_bus.h M src/include/device/resource.h M src/include/fw_config.h M src/include/gpio.h M src/include/imd.h M src/include/memory_info.h M src/include/memrange.h M src/include/metadata_hash.h M src/include/nhlt.h M src/include/spi_flash.h M src/include/stdbool.h M src/include/string.h M src/include/vbe.h M src/lib/asan.c M src/lib/bmp_logo.c M src/lib/boot_device.c M src/lib/bootblock.c M src/lib/bootmem.c M src/lib/cbfs.c M src/lib/cbmem_console.c M src/lib/cbmem_stage_cache.c M src/lib/coreboot_table.c M src/lib/edid_fill_fb.c M src/lib/ext_stage_cache.c M src/lib/fit.c M src/lib/fit_payload.c M src/lib/fmap.c M src/lib/fw_config.c M src/lib/gcov-glue.c M src/lib/gcov-io.c M src/lib/gcov-io.h M src/lib/gpio.c M src/lib/hardwaremain.c M src/lib/imd.c M src/lib/imd_cbmem.c M src/lib/jpeg.c M src/lib/libgcov.c M src/lib/malloc.c M src/lib/memchr.c M src/lib/memrange.c M src/lib/metadata_hash.c M src/lib/nhlt.c M src/lib/prog_loaders.c M src/lib/reg_script.c M src/lib/rmodule.c M src/lib/romstage_handoff.c M src/lib/selfboot.c M src/lib/smbios.c M src/lib/smbios_defaults.c M src/lib/spd_bin.c M src/lib/spd_cache.c M src/lib/string.c M src/lib/thread.c M src/lib/timer_queue.c M src/lib/timestamp.c M src/lib/ux_locales.c M src/lib/xxhash.c M src/mainboard/amd/pademelon/fan_init.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/apple/macbook21/mptable.c M src/mainboard/asus/p2b/variants/p2b-d/mptable.c M src/mainboard/asus/p2b/variants/p2b-ds/mptable.c M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/dell/optiplex_9020/mainboard.c M src/mainboard/dell/snb_ivb_workstations/mainboard.c M src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-sbsa/mainboard.c M src/mainboard/facebook/fbg1701/board_mboot.h M src/mainboard/facebook/fbg1701/board_verified_boot.c M src/mainboard/getac/p470/mptable.c M src/mainboard/google/asurada/mainboard.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/fw_config.c M src/mainboard/google/brox/variants/brox/gpio.c M src/mainboard/google/brya/variants/anahera/fw_config.c M src/mainboard/google/brya/variants/anahera4es/fw_config.c M src/mainboard/google/brya/variants/aurash/fw_config.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c M src/mainboard/google/brya/variants/baseboard/trulo/memory.c M src/mainboard/google/brya/variants/brask/fw_config.c M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/constitution/variant.c M src/mainboard/google/brya/variants/felwinter/fw_config.c M src/mainboard/google/brya/variants/gimble/fw_config.c M src/mainboard/google/brya/variants/gimble4es/fw_config.c M src/mainboard/google/brya/variants/hades/gpio.c M src/mainboard/google/brya/variants/kano/fw_config.c M src/mainboard/google/brya/variants/kuldax/fw_config.c M src/mainboard/google/brya/variants/marasov/fw_config.c M src/mainboard/google/brya/variants/marasov/variant.c M src/mainboard/google/brya/variants/moli/fw_config.c M src/mainboard/google/brya/variants/omnigul/variant.c M src/mainboard/google/brya/variants/orisa/gpio.c M src/mainboard/google/brya/variants/osiris/fw_config.c M src/mainboard/google/brya/variants/primus/fw_config.c M src/mainboard/google/brya/variants/redrix/fw_config.c M src/mainboard/google/brya/variants/redrix4es/fw_config.c M src/mainboard/google/brya/variants/skolas/fw_config.c M src/mainboard/google/brya/variants/skolas/gpio.c M src/mainboard/google/brya/variants/skolas4es/fw_config.c M src/mainboard/google/brya/variants/skolas4es/gpio.c M src/mainboard/google/brya/variants/taeko/fw_config.c M src/mainboard/google/brya/variants/taeko4es/fw_config.c M src/mainboard/google/brya/variants/taniks/fw_config.c M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/volmar/fw_config.c M src/mainboard/google/brya/variants/xol/ramstage.c M src/mainboard/google/brya/variants/yaviks/variant.c M src/mainboard/google/brya/variants/zydron/fw_config.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/corsola/panel_starmie.c M src/mainboard/google/corsola/panel_wugtrio.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/daisy/memory.c M src/mainboard/google/dedede/fw_config.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/bugzzy/gpio.c M src/mainboard/google/dedede/variants/bugzzy/ramstage.c M src/mainboard/google/dedede/variants/cappy2/gpio.c M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/variant.c M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/ramstage.c M src/mainboard/google/dedede/variants/magolor/gpio.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/gale/mmu.c M src/mainboard/google/geralt/panel.c M src/mainboard/google/geralt/panel_ciri.c M src/mainboard/google/geralt/panel_geralt.c M src/mainboard/google/glados/mainboard.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/kukui/panel_anx7625.c M src/mainboard/google/kukui/panel_flapjack.c M src/mainboard/google/kukui/panel_kakadu.c M src/mainboard/google/kukui/panel_katsu.c M src/mainboard/google/kukui/panel_kodama.c M src/mainboard/google/kukui/panel_krane.c M src/mainboard/google/kukui/panel_kukui.c M src/mainboard/google/kukui/panel_ps8640.c M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/myst/variants/baseboard/fw_config.c M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/romstage.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bobba/variant.c M src/mainboard/google/octopus/variants/dood/variant.c M src/mainboard/google/octopus/variants/fleex/variant.c M src/mainboard/google/octopus/variants/foob/gpio.c M src/mainboard/google/octopus/variants/foob/variant.c M src/mainboard/google/octopus/variants/garg/variant.c M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/variant.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/poppy/mainboard.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/puff/romstage.c M src/mainboard/google/puff/variants/baseboard/gpio.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/reef/variants/coral/mainboard.c M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c M src/mainboard/google/rex/variants/deku/ramstage.c M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/storm/mmu.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/drobit/gpio.c M src/mainboard/google/volteer/variants/eldrid/gpio.c M src/mainboard/google/volteer/variants/elemi/gpio.c M src/mainboard/google/volteer/variants/halvor/gpio.c M src/mainboard/google/volteer/variants/malefor/gpio.c M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/trondo/gpio.c M src/mainboard/google/volteer/variants/voema/gpio.c M src/mainboard/google/volteer/variants/volet/gpio.c M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/voxel/gpio.c M src/mainboard/google/volteer/variants/voxel/variant.c M src/mainboard/google/zork/mainboard.c M src/mainboard/google/zork/variants/baseboard/dalboz/fsps.c M src/mainboard/google/zork/variants/baseboard/dalboz/gpio.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c M src/mainboard/google/zork/variants/dalboz/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c M src/mainboard/google/zork/variants/trembyle/gpio.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/ibm/sbp1/ramstage.c M src/mainboard/intel/adlrvp/fw_config.c M src/mainboard/intel/coffeelake_rvp/mainboard.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/intel/glkrvp/mainboard.c M src/mainboard/intel/harcuvar/hsio.c M src/mainboard/intel/harcuvar/ramstage.c M src/mainboard/intel/harcuvar/romstage.c M src/mainboard/intel/kblrvp/ramstage.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/mtlrvp/fw_config.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/inventec/transformers/ipmi.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c M src/mainboard/opencellular/elgon/mainboard.c M src/mainboard/pcengines/apu2/OemCustomize.c M src/mainboard/prodrive/atlas/vpd.c M src/mainboard/prodrive/atlas/vpd.h M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/protectli/vault_cml/mainboard.c M src/mainboard/protectli/vault_ehl/romstage.c M src/mainboard/purism/librem_cnl/romstage.c M src/mainboard/roda/rk886ex/mptable.c M src/mainboard/siemens/fa_ehl/mainboard.c M src/mainboard/siemens/fa_ehl/variants/fa_ehl/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/mainboard/sifive/hifive-unleashed/media.c M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c M src/mainboard/sifive/hifive-unmatched/fixup_fdt.c M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/x4x/northbridge.c M src/security/intel/stm/SmmStm.c M src/security/intel/stm/SmmStm.h M src/security/intel/stm/StmPlatformResource.c M src/security/intel/txt/common.c M src/security/intel/txt/getsec.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/lockdown/lockdown.c M src/security/memory/memory_clear.c M src/security/tpm/tis.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/log-tpm1.c M src/security/tpm/tspi/log-tpm2.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tss.c M src/security/tpm/tss1.h M src/security/vboot/bootmode.c M src/security/vboot/common.c M src/security/vboot/secdata_tpm2.c M src/security/vboot/vbnv_cmos.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_loader.c M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/xhci.h M src/soc/amd/cezanne/mca.c M src/soc/amd/cezanne/smihandler.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/acpi/madt.c M src/soc/amd/common/block/acpi/pm_state.c M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/cpu/cpu.c M src/soc/amd/common/block/cpu/smm/finalize.c M src/soc/amd/common/block/cpu/smm/smi_apmc.c M src/soc/amd/common/block/cpu/update_microcode.c M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/gpio/gpio.c M src/soc/amd/common/block/graphics/graphics.c M src/soc/amd/common/block/i2c/i2c.c M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/include/amdblocks/apob_cache.h M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/common/block/pci/pci_routing_info.c M src/soc/amd/common/block/pci/pcie_gpp.c M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/spl_fuse.c M src/soc/amd/common/block/stb/stb.c M src/soc/amd/common/block/uart/uart.c M src/soc/amd/common/fsp/dmi.c M src/soc/amd/common/fsp/fsp-acpi.c M src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c M src/soc/amd/common/fsp/pci/pci_routing_info.c M src/soc/amd/common/fsp/pci/pcie_clk_req.c M src/soc/amd/common/fsp/preload_fsps.c M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/common/pi/amd_late_init.c M src/soc/amd/common/pi/amd_resume_final.c M src/soc/amd/common/pi/def_callouts.c M src/soc/amd/common/pi/heapmanager.c M src/soc/amd/common/pi/image.c M src/soc/amd/common/pi/refcode_loader.c M src/soc/amd/common/pi/s3_resume.c M src/soc/amd/common/psp_verstage/boot_dev.c M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/common/psp_verstage/vboot_crypto.c M src/soc/amd/genoa_poc/domain.c M src/soc/amd/genoa_poc/mca.c M src/soc/amd/genoa_poc/smihandler.c M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/fsp_m_params.c M src/soc/amd/glinda/mca.c M src/soc/amd/glinda/psp_verstage/chipset.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/fch.c M src/soc/amd/mendocino/fsp_m_params.c M src/soc/amd/mendocino/fsp_misc_data_hob.c M src/soc/amd/mendocino/include/soc/xhci.h M src/soc/amd/mendocino/manifest.c M src/soc/amd/mendocino/mca.c M src/soc/amd/mendocino/psp_verstage/chipset.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/fch.c M src/soc/amd/phoenix/fsp_m_params.c M src/soc/amd/phoenix/include/soc/xhci.h M src/soc/amd/phoenix/mca.c M src/soc/amd/phoenix/pci_irq_routing.c M src/soc/amd/phoenix/psp_verstage/chipset.c M src/soc/amd/phoenix/smihandler.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/acpi_crat.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/fsp_s_params.c M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/picasso/soc_util.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/fch.c M src/soc/amd/stoneyridge/mca.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/soc.c M src/soc/example/min86/chip.c M src/soc/ibm/power9/rom_media.c M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/elog.c M src/soc/intel/alderlake/finalize.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/hsphy.c M src/soc/intel/alderlake/include/soc/pci_devs.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/alderlake/xhci.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/refcode.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/pch/elog.c M src/soc/intel/broadwell/pch/me.c M src/soc/intel/broadwell/pch/me_status.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/ramstage.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/basecode/debug/debug_feature.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/acpi/acpi_wake_source.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/cse/cse_spec.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/graphics/early_graphics.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/irq/irq.c M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/common/block/pcie/pcie_rp.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/vtd/vtd.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/mma.c M src/soc/intel/common/nhlt.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/common/vbt.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/fiamux.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/hob_display.c M src/soc/intel/denverton_ns/hob_mem.c M src/soc/intel/denverton_ns/include/soc/hob_mem.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/elkhartlake/include/soc/pci_devs.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pci_devs.h M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/elog.c M src/soc/intel/meteorlake/finalize.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/include/soc/pci_devs.h M src/soc/intel/meteorlake/meminit.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/meteorlake/systemagent.c M src/soc/intel/meteorlake/xhci.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/crashlog_lib.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/tigerlake/xhci.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/hob_display.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/ebg/soc_xhci.c M src/soc/intel/xeon_sp/finalize.c M src/soc/intel/xeon_sp/gnr/cpu.c M src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/hob_display.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/smmrelocate.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/cpu.c M src/soc/intel/xeon_sp/spr/hob_display.c M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c M src/soc/mediatek/common/display.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/memory.c M src/soc/mediatek/common/msdc.c M src/soc/mediatek/common/mt6315.c M src/soc/mediatek/common/mt6359p.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/pmif.c M src/soc/mediatek/common/rtc_mt6359p.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/spi.c M src/soc/mediatek/mt8188/gpio.c M src/soc/mediatek/mt8188/spi.c M src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8192/gpio.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8192/spi.c M src/soc/mediatek/mt8195/gpio.c M src/soc/mediatek/mt8195/spi.c M src/soc/nvidia/tegra/software_i2c.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/include/soc/console_uart.h M src/soc/nvidia/tegra210/include/soc/funitcfg.h M src/soc/nvidia/tegra210/include/soc/mipi_dsi.h M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/mtc.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/spi.c M src/soc/qualcomm/common/mmu.c M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/common/qspi.c M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/common/qupv3_i2c.c M src/soc/qualcomm/common/qupv3_spi.c M src/soc/qualcomm/common/storage/sdhci_msm.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/include/soc/iomap.h M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/qcs405/include/soc/iomap.h M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sc7180/display/dsi.c M src/soc/qualcomm/sc7180/soc.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/sdhci.c M src/soc/qualcomm/sc7280/soc.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3399/display.c M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/gpio.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/gpio.c M src/soc/samsung/exynos5420/spi.c M src/soc/ti/am335x/gpio.c M src/soc/ti/am335x/mmc.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/pci.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/bd82x6x/me_smm.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/smihandler.c M src/superio/aspeed/ast2400/superio.c M src/superio/common/ssdt.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f81803a/fan_control.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8629e/superio.c M src/superio/ite/it8659e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8784e/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5539d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6687d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/smsc/sch555x/ramstage.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c M tests/Makefile.common M tests/acpi/acpigen-test.c M tests/commonlib/bsd/gcd-test.c M tests/commonlib/bsd/helpers-test.c M tests/commonlib/bsd/ipchksum-test.c M tests/commonlib/bsd/string-test.c M tests/commonlib/device_tree-test.c M tests/commonlib/list-test.c M tests/commonlib/rational-test.c M tests/commonlib/region-test.c M tests/console/routing-test.c M tests/device/ddr4-test.c M tests/device/i2c-test.c M tests/drivers/efivars.c M tests/lib/b64_decode-test.c M tests/lib/bootmem-test.c M tests/lib/cbfs-lookup-test.c M tests/lib/cbfs-verification-test.c M tests/lib/cbmem_console-test.c M tests/lib/cbmem_stage_cache-test.c M tests/lib/coreboot_table-test.c M tests/lib/crc_byte-test.c M tests/lib/dimm_info_util-test.c M tests/lib/edid-test.c M tests/lib/fmap-test.c M tests/lib/hexstrtobin-test.c M tests/lib/imd-test.c M tests/lib/imd_cbmem-test.c M tests/lib/lib-test.c M tests/lib/libgcc-test.c M tests/lib/lzma-test.c M tests/lib/malloc-test.c M tests/lib/memchr-test.c M tests/lib/memcmp-test.c M tests/lib/memcpy-test.c M tests/lib/memmove-test.c M tests/lib/memrange-test.c M tests/lib/memset-test.c M tests/lib/region_file-test.c M tests/lib/rtc-test.c M tests/lib/spd_cache-test.c M tests/lib/stack-test.c M tests/lib/string-test.c M tests/lib/timestamp-test.c M tests/lib/uuid-test.c M tests/lib/ux_locales-test.c M util/cbfstool/Makefile.mk M util/cbfstool/lz4/lib/Makefile D util/crossgcc/tarballs/.empty M util/nvidia/Makefile.mk M util/superiotool/Makefile 1,161 files changed, 4,479 insertions(+), 4,477 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/83585/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie21b10251d72adee93c25c34ea5387c48d341f01 Gerrit-Change-Number: 83585 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nico Huber (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Paul Menzel. Nico Huber has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email ) Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83504/comment/300c706d_8df4c2e9?us… : PS3, Line 12: The southbridge's codect_detect() was written a long time ago and : mentions that it was "not working yet" in the commit message. Therefore, : I believe that the differences was due to it being a rough : implementation and did not follow the specification exactly in some : places (e.g. only using 4 bits for codec_mask instead of 15 bits). > Thanks, you're right this commit message was made without much merit. I will remove it. […] Ah, thanks, but maybe dropped a bit too much. I think Paul is right, you should mention differences. IMO it's enough to say that there are some(*). Just don't try to justify them. (* if somebody is looking through the log for potential regressions, they should be able to spot this change, that's all) -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 18:18:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

1 0

[XS] Change in coreboot[main]: [wip]crossgcc: Upgrade CMake from 3.28.3 to 3.30.1
by Elyes Haouas (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83007?usp=email ) Change subject: [wip]crossgcc: Upgrade CMake from 3.28.3 to 3.30.1 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0bb1a2a84d81ec03c4468955926f3f0c94276203 Gerrit-Change-Number: 83007 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 13:54:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nicholas Sudsgaard (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nico Huber, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email ) Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83504/comment/da5ec929_3963965d?us… : PS3, Line 12: The southbridge's codect_detect() was written a long time ago and : mentions that it was "not working yet" in the commit message. Therefore, : I believe that the differences was due to it being a rough : implementation and did not follow the specification exactly in some : places (e.g. only using 4 bits for codec_mask instead of 15 bits). > Just digged a little deeper. The BKDG references relate […] Thanks, you're right this commit message was made without much merit. I will remove it. For the record, I was referring to commit a8e1168064 in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 20 Jul 2024 13:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nicholas Sudsgaard (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Paul Menzel. Hello Felix Singer, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83504?usp=email to look at the new patch set (#4). Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... southbridge/intel: Use azalia_audio_init() instead of duplicating code Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c 3 files changed, 3 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83504/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nico Huber (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Paul Menzel. Nico Huber has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email ) Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83504/comment/77055219_e8ae068b?us… : PS3, Line 12: The southbridge's codect_detect() was written a long time ago and : mentions that it was "not working yet" in the commit message. Therefore, : I believe that the differences was due to it being a rough : implementation and did not follow the specification exactly in some : places (e.g. only using 4 bits for codec_mask instead of 15 bits). > This awfully sounds like you are making excuses for changing the […] Just digged a little deeper. The BKDG references relate to [1] (except the copy-pasta ones). And the procedure was first corrected in commit 4505948f. Just to add some background. I think this commit should just go in (without a wrong text wall). [1] https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/program… -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 09:55:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nico Huber (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Paul Menzel. Nico Huber has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email ) Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83504/comment/87da0cf1_6e6718c3?us… : PS3, Line 12: The southbridge's codect_detect() was written a long time ago and : mentions that it was "not working yet" in the commit message. Therefore, : I believe that the differences was due to it being a rough : implementation and did not follow the specification exactly in some : places (e.g. only using 4 bits for codec_mask instead of 15 bits). This awfully sounds like you are making excuses for changing the code. That shouldn't be necessary. The code may have been added with these words, but it's running on some of the most prominent coreboot platforms, hence I'd expect we'd know by now if it wasn't working. Also, what commit message? Reading it, I see nothing too rough. The generic code, OTOH, looks wrong and overengineered. The additional wait loop seems to go back to commit be61a173. Probably was just mimicking the other loop. Both implementations seem to be missing all the delays around reset (de-)assertion btw. That might actually be what the mentioned BKDG had in mind... The effective codec mask is given in each chip's datasheet btw. -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 09:27:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yu-Ping Wu (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/rauru/Kconfig: https://review.coreboot.org/c/coreboot/+/83573/comment/ff54f14d_c6d4162b?us… : PS7, Line 8: ``` WARNING: unmet direct dependencies detected for VBOOT_MOCK_SECDATA Depends on [n]: VBOOT [=n] Selected by [y]: - BOARD_SPECIFIC_OPTIONS [=y] && VENDOR_GOOGLE [=y] && BOARD_GOOGLE_RAURU_COMMON [=y] ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 08:37:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nicholas Sudsgaard (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nico Huber, Paul Menzel. Hello Felix Singer, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83504?usp=email to look at the new patch set (#3). Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... southbridge/intel: Use azalia_audio_init() instead of duplicating code There are some differences between the southbridge's codec_detect() removed in this patch and the one in device/azalia_device.c. The southbridge's codect_detect() was written a long time ago and mentions that it was "not working yet" in the commit message. Therefore, I believe that the differences was due to it being a rough implementation and did not follow the specification exactly in some places (e.g. only using 4 bits for codec_mask instead of 15 bits). Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c 3 files changed, 3 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83504/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nicholas Sudsgaard (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nico Huber, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83504?usp=email ) Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/i82801gx/azalia.c: https://review.coreboot.org/c/coreboot/+/83504/comment/5cd1ce31_cec551a8?us… : PS1, Line 27: 0x0f > Just mention the difference in the commit message? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 20 Jul 2024 04:21:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[M] Change in coreboot[main]: southbridge/intel: Use azalia_audio_init() instead of duplicating code
by Nicholas Sudsgaard (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Nico Huber. Hello Felix Singer, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83504?usp=email to look at the new patch set (#2). Change subject: southbridge/intel: Use azalia_audio_init() instead of duplicating code ...................................................................... southbridge/intel: Use azalia_audio_init() instead of duplicating code There are some differences between the southbridge's codec_detect() removed in this patch and the one in device/azalia_device.h. The southbridge's codect_detect() was written a long time ago and mentions that it was "not working yet" in the commit message. Therefore, I believe that the differences was due to it being a rough implementation and did not follow the specification exactly in some places (e.g. only using 4 bits for codec_mask instead of 15 bits). Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c 3 files changed, 3 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83504/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie174ba29c115e3a3419362602d3e3175c9a03708 Gerrit-Change-Number: 83504 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Subrata Banik (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Nico Huber, Rishika Raj, Tarun. Subrata Banik has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/85bfb18c_64191711?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > > > Why the 32KiB? this makes it sound like coreboot would need that much. > > > Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB > > > would provide enough margin (unless something is wrong with the 512). > > > > The CAR stack defined in coreboot is also used by coreboot to fill up the FSP-M UPDs. It is evident that the existing romstage stack size (1KB) is too small to fulfill its intended purpose, as the 1KB reserved for coreboot's portion of the stack cannot even accommodate the stack-allocated FSPM_UPD structure itself. > > I see. Didn't expect this on the stack. Is that reasonable? Shouldn't that > be linked into .bss or something? > > It's about 4KiB AFAICS, is that correct? FSP-M upd is around 4kb? > > > > > Based on our debugging, we have observed instances where the vboot structure is also linked into CAR. As a result, we believe that 32KB is a reasonable size for us, given all of the factors involved. > > I don't understand this, how would a vboot structure linked into CAR affect > the stack? What structure are you referring to specifically? struct vb2_context variables -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 03:31:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/f963e1eb_a476255c?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > Is it really that different? Please mention it in the commit message, and also reference the datashe […] Certainly, this has been the longstanding MediaTek SOC maintenance approach. I think there is no need to explicitly mention it in the message. And the datasheet will also be referenced in the code. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 02:57:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/rauru/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83573/comment/93e11e1f_61ea9515?us… : PS6, Line 1: all-y += memlayout.ld > src/mainboard/google/rauru/Makefile.mk has no recognized SPDX identifier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 02:27:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83572/comment/f325e9f1_831d4856?us… : PS5, Line 1: ## SPDX-License-Identifier: GPL-2.0-only > one blank line below Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 02:27:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83572?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 329 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Jarried Lin, Yidi Lin. Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83573?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified-1 by build bot (Jenkins) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... mb/google/rauru: Add MediaTek MT8196 reference board Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e --- A src/mainboard/google/rauru/Kconfig A src/mainboard/google/rauru/Kconfig.name A src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/board_info.txt A src/mainboard/google/rauru/bootblock.c A src/mainboard/google/rauru/chromeos.c A src/mainboard/google/rauru/chromeos.fmd A src/mainboard/google/rauru/devicetree.cb A src/mainboard/google/rauru/mainboard.c A src/mainboard/google/rauru/memlayout.ld A src/mainboard/google/rauru/reset.c A src/mainboard/google/rauru/romstage.c 12 files changed, 157 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Paul Menzel (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/2fd6f09d_1abe7796?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > Due to different SoCs architectures, register addresses, and driver parameters, if there are common […] Is it really that different? Please mention it in the commit message, and also reference the datasheet name and revision. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 20:16:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Paul Menzel (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Rishika Raj, Subrata Banik, Tarun. Paul Menzel has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/43f0fcf4_fbbb8307?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > Commit message is a bit wordy. Can you make it shorter? […] Do you mean the summary/title? I think your proposal is too general. meteorlake to mtl is a good way to make it a little shorter though. -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 20:15:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[S] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Use boolean type where applicable
by Elyes Haouas (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Martin L Roth, Marvin Evers, Michael Strosche, Subrata Banik, Tarun, Tarun Tuli. Elyes Haouas has posted comments on this change by Michael Strosche. ( https://review.coreboot.org/c/coreboot/+/77374?usp=email ) Change subject: soc/intel/meteorlake/chip.h: Use boolean type where applicable ...................................................................... Patch Set 8: Code-Review+1 (6 comments) File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/77374/comment/89861d50_a1697958?us… : PS8, Line 212: 1:Enable, 0:Disable update the comment https://review.coreboot.org/c/coreboot/+/77374/comment/8683b413_c9cdb288?us… : PS8, Line 235: * Default 0. Setting this to 1 disables update https://review.coreboot.org/c/coreboot/+/77374/comment/5c976987_7e2a3400?us… : PS8, Line 301: 1b:Enabled, 0b:Disabled update https://review.coreboot.org/c/coreboot/+/77374/comment/1c28b499_d4c2bc98?us… : PS8, Line 451: Default 0. Setting this to 1 disables th update https://review.coreboot.org/c/coreboot/+/77374/comment/cede8b49_61be5871?us… : PS8, Line 456: Enable(1)/Disable(0) update https://review.coreboot.org/c/coreboot/+/77374/comment/175fffad_6b292d8c?us… : PS8, Line 457: Default 0. Setting this to 1 update -- To view, visit https://review.coreboot.org/c/coreboot/+/77374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Gerrit-Change-Number: 77374 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 19:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: tree: Use boolean for "eist_enable"
by Felix Singer (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Erik van den Bogaert, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Crawford, Werner Zeh. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83575?usp=email ) Change subject: tree: Use boolean for "eist_enable" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I would like to get in CB:77374 and others in first. Once that is done we can use a reproducible way for moving over the boolean options to true/false keywords. -- To view, visit https://review.coreboot.org/c/coreboot/+/83575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Gerrit-Change-Number: 83575 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 19 Jul 2024 19:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
by Nick Vaccaro (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Edward Doan, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, SH Kim, Subrata Banik, YH Lin. Nick Vaccaro has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email ) Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/brya/variants/xol/gpio.c: https://review.coreboot.org/c/coreboot/+/83346/comment/ed7d3c37_7529ac5b?us… : PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG), > Acknowledged I'm not sure where that clip came from, but the GPP_F14 gpio is not locked in mainboard/google/brya/variants/baseboard/brya/gpio.c File src/mainboard/google/brya/variants/xol/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83346/comment/a0f56820_1ddcdefc?us… : PS1, Line 347: register "generic.detect" = "1" > Acknowledged Won't this enable the interrupt? (IIRC, the touchpad is powered directly off of a power rail, so no independent way to disable interrupt for it. If it enables the interrupt but there's no handler in coreboot for it / interrupt handler is in the kernel, couldn't that cause a problem if the touchpad interrupts before kernel is loaded? -- To view, visit https://review.coreboot.org/c/coreboot/+/83346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Gerrit-Change-Number: 83346 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Edward Doan <edoan(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 18:59:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
by Nick Vaccaro (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Edward Doan, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, SH Kim, YH Lin. Nick Vaccaro has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/xol/gpio.c: https://review.coreboot.org/c/coreboot/+/83346/comment/52f01646_e940ec29?us… : PS5, Line 128: LEVEL Isn't this signal active-low? -- To view, visit https://review.coreboot.org/c/coreboot/+/83346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Gerrit-Change-Number: 83346 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Edward Doan <edoan(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 18:47:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: xcompile: Drop CC_RT_EXTRA_GCC for PPC64
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Martin L Roth, Michał Żygowski, Nico Huber. Arthur Heymans has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/83577?usp=email ) Change subject: xcompile: Drop CC_RT_EXTRA_GCC for PPC64 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b Gerrit-Change-Number: 83577 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 18:06:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
by Felix Singer (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jonathon Hall, Martin L Roth, Nico Huber, Paul Menzel. Felix Singer has posted comments on this change by Jonathon Hall. ( https://review.coreboot.org/c/coreboot/+/83476?usp=email ) Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled ...................................................................... Patch Set 2: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/83476/comment/21a302f4_8b0c4513?us… : PS2, Line 507: default 0x400000 if BOOTSPLASH Why not adding this as another default to src/Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/83476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4348d39effbc16c1b42ab01bcf1e4ec5d652fa9 Gerrit-Change-Number: 83476 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nigel Tao <nigeltao(a)golang.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Fri, 19 Jul 2024 17:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/dedede/var/awasuki: Initialise overridetree
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eric Lai, Lawrence Chang, Weimin Wu. Karthik Ramasubramanian has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/83496?usp=email ) Change subject: mb/google/dedede/var/awasuki: Initialise overridetree ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/dedede/variants/awasuki/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83496/comment/65e4fc2b_d45ec0b0?us… : PS6, Line 21: #| I2C1 | Disable | : #| I2C2 | Touchscreen | : #| I2C3 | Disable Also you need to do disable I2C in FSP config like below: ``` register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" ``` https://review.coreboot.org/c/coreboot/+/83496/comment/08e25591_3278a218?us… : PS6, Line 204: device pci 1c.7 on : chip drivers/wifi/generic : register "wake" = "GPE0_DW2_03" : device pci 00.0 on end : end Does this board also support external/discrete Wifi? You need this only when discrete Wifi is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/83496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Gerrit-Change-Number: 83496 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/dedede/var/awasuki: Add initial GPIOs config
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83449?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/awasuki: Add initial GPIOs config ...................................................................... mb/google/dedede/var/awasuki: Add initial GPIOs config Configure GPIOs according to schematics revision 20240712. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/awasuki/Makefile.mk A src/mainboard/google/dedede/variants/awasuki/gpio.c 2 files changed, 66 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/awasuki/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/Makefile.mk new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/awasuki/gpio.c b/src/mainboard/google/dedede/variants/awasuki/gpio.c new file mode 100644 index 0000000..dfe14cd --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/gpio.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H1 : EN_PP3300_SD_U */ + PAD_NC(GPP_H1, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Gerrit-Change-Number: 83449 Gerrit-PatchSet: 8 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/awasuki: Generate 3 RAM IDs
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83427?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/awasuki: Generate 3 RAM IDs ...................................................................... mb/google/dedede/var/awasuki: Generate 3 RAM IDs Vendor DRAM Part Name Type SAMSUNG K4U6E3S4AB-MGCL LP4X SAMSUNG K4UBE3D4AB-MGCL LP4X MICRON MT53E1G32D2NP-046 WT:B LP4X BUG=b:351968527 TEST=Run part_id_gen tool without any errors Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427 Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk M src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt 3 files changed, 17 insertions(+), 2 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk index eace2e4..5348e2f 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/awasuki/memory src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt index fa24790..495df98 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/awasuki/memory src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt index 2499005..ca9e5c1 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name + +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/83427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Gerrit-Change-Number: 83427 Gerrit-PatchSet: 10 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/dedede: Create awasuki variant
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83376?usp=email ) Change subject: mb/google/dedede: Create awasuki variant ...................................................................... mb/google/dedede: Create awasuki variant Create the awasuki variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:351968527 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_AWASUKI Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/awasuki/data.vbt A src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h A src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h A src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk A src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/awasuki/overridetree.cb 9 files changed, 86 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Dolan Liu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 7c42120..f0ab1f5 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -34,6 +34,12 @@ select SOC_INTEL_JASPERLAKE select SPI_FLASH_SMM +config BOARD_GOOGLE_AWASUKI + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP + select SOC_INTEL_COMMON_BLOCK_IPU + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 def_bool n select BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -336,6 +342,7 @@ default "Taranza" if BOARD_GOOGLE_TARANZA default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "Awasuki" if BOARD_GOOGLE_AWASUKI config MAX_CPUS int @@ -380,6 +387,7 @@ default "taranza" if BOARD_GOOGLE_TARANZA default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "awasuki" if BOARD_GOOGLE_AWASUKI endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 6c1bf76..b470824 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -99,3 +99,6 @@ config BOARD_GOOGLE_WADDLEDOO bool "-> Waddledoo" + +config BOARD_GOOGLE_AWASUKI + bool "-> Awasuki" diff --git a/src/mainboard/google/dedede/variants/awasuki/data.vbt b/src/mainboard/google/dedede/variants/awasuki/data.vbt new file mode 100644 index 0000000..d082b19 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/data.vbt Binary files differ diff --git a/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h b/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h b/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/83376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Gerrit-Change-Number: 83376 Gerrit-PatchSet: 16 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Paul Menzel, Rishika Raj, Subrata Banik, Tarun. Nico Huber has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/c4ed6f96_5d0ef547?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > > Why the 32KiB? this makes it sound like coreboot would need that much. > > Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB > > would provide enough margin (unless something is wrong with the 512). > > The CAR stack defined in coreboot is also used by coreboot to fill up the FSP-M UPDs. It is evident that the existing romstage stack size (1KB) is too small to fulfill its intended purpose, as the 1KB reserved for coreboot's portion of the stack cannot even accommodate the stack-allocated FSPM_UPD structure itself. I see. Didn't expect this on the stack. Is that reasonable? Shouldn't that be linked into .bss or something? It's about 4KiB AFAICS, is that correct? > > Based on our debugging, we have observed instances where the vboot structure is also linked into CAR. As a result, we believe that 32KB is a reasonable size for us, given all of the factors involved. I don't understand this, how would a vboot structure linked into CAR affect the stack? What structure are you referring to specifically? -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Give PSP verstage 4K more space
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83564?usp=email ) Change subject: soc/amd/cezanne: Give PSP verstage 4K more space ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/psp_verstage_addr.h: https://review.coreboot.org/c/coreboot/+/83564/comment/9ced0144_cdf2b00b?us… : PS2, Line 20: #define PSP_VERSTAGE_STACK_START 0x42000 : #define PSP_VERSTAGE_STACK_SIZE (36K) The stack size and start address is a contract between PSP Bootloader and Verstage. So changing it here alone will break that contract. I am wondering if there are any clang compiler settings that can satisfy the memory layout requirements. Since we need to fix the original issue, let us just do ` cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);` in vbnv_platform_init_cmos for now and revisit switching to cmos_init(0) later. -- To view, visit https://review.coreboot.org/c/coreboot/+/83564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f53a45d67782d3e425f423d0715a45482b2edea Gerrit-Change-Number: 83564 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:38:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by YH Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar, YH Lin. YH Lin has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83479/comment/ec0ad43e_8e52815f?us… : PS7, Line 17: BUG=b:353395811 > Add me in bug to understand the background of this change. Thanks. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:35:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[XS] Change in coreboot[main]: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jérémy Compostella, Paul Menzel, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83537?usp=email ) Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6122201914c40604f86dcca6025b55c595ef609e Gerrit-Change-Number: 83537 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:29:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Subrata Banik (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Nico Huber, Paul Menzel, Rishika Raj, Tarun. Subrata Banik has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/d38adda1_1ee6782d?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > Why the 32KiB? this makes it sound like coreboot would need that much. > Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB > would provide enough margin (unless something is wrong with the 512). The CAR stack defined in coreboot is also used by coreboot to fill up the FSP-M UPDs. It is evident that the existing romstage stack size (1KB) is too small to fulfill its intended purpose, as the 1KB reserved for coreboot's portion of the stack cannot even accommodate the stack-allocated FSPM_UPD structure itself. Based on our debugging, we have observed instances where the vboot structure is also linked into CAR. As a result, we believe that 32KB is a reasonable size for us, given all of the factors involved. -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: xcompile: Drop CC_RT_EXTRA_GCC for PPC64
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Michał Żygowski. Hello Michał Żygowski, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83577?usp=email to review the following change. Change subject: xcompile: Drop CC_RT_EXTRA_GCC for PPC64 ...................................................................... xcompile: Drop CC_RT_EXTRA_GCC for PPC64 It looks like some unused artifact: The PPC64 Makefile.mk doesn't pick it up. Also, the only other architecture using this (x86) has linker flags there, not compiler flags. Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/xcompile/xcompile 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83577/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3948811..b3012b5 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -415,7 +415,6 @@ TWIDTH="64" TSUPP="ppc64" TABI="linux-gnu" # there is no generic ABI on ppc64 - CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } # Right now, the clang reference toolchain is not building compiler-rt builtins -- To view, visit https://review.coreboot.org/c/coreboot/+/83577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b Gerrit-Change-Number: 83577 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/41d450b8_ccd35649?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. > > How would that look like? it's not just one linker script, right? […] So we'd have to duplicate that file for x86? Hmmm, looking through Makefiles, couldn't we just do something like ``` LDFLAGS_x86_32 += --oformat elf-i386 LDFLAGS_x86_64 += --oformat elf-x86-64 ``` ? `toolchain.mk` should add that to the respective stages (all on x86, I guess). -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 15:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve FSP MMIO high window
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email ) Change subject: soc/intel/xeon_sp: Reserve FSP MMIO high window ...................................................................... Patch Set 1: (6 comments) Patchset: PS1: > Some critical log diffs: […] Just for the future, please disable CONSOLE_USE_ANSI_ESCAPES and use triple backticks \`\`\` for quote blocks. Also, what you pasted is not the MTRR assignment but the requirements. Commit Message: https://review.coreboot.org/c/coreboot/+/83538/comment/edaa428b_6c4eb88b?us… : PS1, Line 7: soc/intel/xeon_sp: Reserve FSP MMIO high window Only for SPR, right? btw. why? https://review.coreboot.org/c/coreboot/+/83538/comment/0de08812_32eaf051?us… : PS1, Line 9: Xeon-SP supports MMIO high window, a.k.a. MMIO window above 4G. TBH, I don't know what this means; or what platform doesn't support it? https://review.coreboot.org/c/coreboot/+/83538/comment/58821c4e_7aa00c89?us… : PS1, Line 19: is especially important : on systems with 2 or more sockets, where each socket has multiple : domains. How so? In what scenario is this important? What part of coreboot or your payload has such requirements? File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/83538/comment/d10ee5ad_5e0830c5?us… : PS1, Line 368: * Add MMIO high window. That's what the code says. Please don't state the obvious in comments. What a reader needs to know here is *why* we do it here in set_resources(). https://review.coreboot.org/c/coreboot/+/83538/comment/231d4481_8bfd6293?us… : PS1, Line 375: index++; This not stable because mmapvtd_read_resources() mixes generic PCI resources and the static ones counted from 0. The latter start at 0x10, IIRC. Does the `mmapvtd` device really have standard PCI resources? If so, I would choose some higher constant and document that. -- To view, visit https://review.coreboot.org/c/coreboot/+/83538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Gerrit-Change-Number: 83538 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 14:47:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: superio/ite: Enable common driver for GPIO and LED configuration
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83468?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: superio/ite: Enable common driver for GPIO and LED configuration ...................................................................... superio/ite: Enable common driver for GPIO and LED configuration Enables the driver for ITE SIOs supporting the GPIO register layout (confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs with unavailable datasheets are unmodified). Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM and must then provide the number of GPIO sets specific to a chip via SUPERIO_ITE_COMMON_NUM_GPIO_SETS. Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/superio/ite/it8613e/Kconfig M src/superio/ite/it8659e/Kconfig M src/superio/ite/it8712f/Kconfig M src/superio/ite/it8718f/Kconfig M src/superio/ite/it8720f/Kconfig M src/superio/ite/it8721f/Kconfig M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8783ef/Kconfig M src/superio/ite/it8784e/Kconfig M src/superio/ite/it8786e/Kconfig 11 files changed, 90 insertions(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..cc709ae 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -3,9 +3,18 @@ config SUPERIO_ITE_IT8613E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8613E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8659e/Kconfig b/src/superio/ite/it8659e/Kconfig index 92ee4c1..43b8c95 100644 --- a/src/superio/ite/it8659e/Kconfig +++ b/src/superio/ite/it8659e/Kconfig @@ -3,8 +3,17 @@ config SUPERIO_ITE_IT8659E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + + +if SUPERIO_ITE_IT8659E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8712f/Kconfig b/src/superio/ite/it8712f/Kconfig index 0dfa524..81b3c62 100644 --- a/src/superio/ite/it8712f/Kconfig +++ b/src/superio/ite/it8712f/Kconfig @@ -3,3 +3,11 @@ config SUPERIO_ITE_IT8712F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + +if SUPERIO_ITE_IT8712F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 5 + +endif diff --git a/src/superio/ite/it8718f/Kconfig b/src/superio/ite/it8718f/Kconfig index 65fcdab..c17bf41 100644 --- a/src/superio/ite/it8718f/Kconfig +++ b/src/superio/ite/it8718f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8718F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8718F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig index 338ed21..3625ef6 100644 --- a/src/superio/ite/it8720f/Kconfig +++ b/src/superio/ite/it8720f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8720F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8720F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index ec22a2d..8c2e676 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -3,7 +3,15 @@ config SUPERIO_ITE_IT8721F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8721F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index be16a2d..c85e94a 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8728F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + +if SUPERIO_ITE_IT8728F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 8e9af54..6d7cf39 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED select SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8772F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8783ef/Kconfig b/src/superio/ite/it8783ef/Kconfig index e1d993f..da47e45 100644 --- a/src/superio/ite/it8783ef/Kconfig +++ b/src/superio/ite/it8783ef/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8783EF bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8783EF + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8784e/Kconfig b/src/superio/ite/it8784e/Kconfig index 66dd6c9..ba19459 100644 --- a/src/superio/ite/it8784e/Kconfig +++ b/src/superio/ite/it8784e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8784E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8784E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 216d6f5..ab4a92f 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8786E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8786E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798 Gerrit-Change-Number: 83468 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: superio/ite/common: Add common driver for GPIO and LED configuration
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83355?usp=email ) Change subject: superio/ite/common: Add common driver for GPIO and LED configuration ...................................................................... superio/ite/common: Add common driver for GPIO and LED configuration Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The driver supports most ITE SuperIOs, except Embedded Controllers. The driver allows configuring every GPIO property with pin granularity. Verified against datasheets of all ITE SIOs currently supported by coreboot, except IT8721F (assumed to be the same as IT8720F), IT8623E and IT8629E. Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355 Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/superio/ite/Makefile.mk M src/superio/ite/common/Kconfig A src/superio/ite/common/gpio.c A src/superio/ite/common/ite_gpio.h 4 files changed, 297 insertions(+), 0 deletions(-) Approvals: Nicholas Sudsgaard: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk index 678ea95..afbce8a 100644 --- a/src/superio/ite/Makefile.mk +++ b/src/superio/ite/Makefile.mk @@ -4,11 +4,15 @@ bootblock-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c +bootblock-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c +romstage-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c + ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c ## include generic ite driver to smm to control S3-relevant functions smm-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c +smm-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c subdirs-y += it8528e subdirs-y += it8613e diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 4701056..c5eeec6 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -5,6 +5,33 @@ config SUPERIO_ITE_COMMON_PRE_RAM bool +config SUPERIO_ITE_COMMON_GPIO_PRE_RAM + bool + help + Enable generic pre-ram driver for configuring ITE SIO GPIOs. + It applies only to ITE SIOs not ITE ECs using LDN 7 (typically) + to configure GPIO Simple I/O mode. + +if SUPERIO_ITE_COMMON_GPIO_PRE_RAM + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + int + help + The maximum number of GPIO sets supported by ITE SIO chip. + Each SIO chip must set this config option to a proper values + if it intends to enable SUPERIO_ITE_COMMON_GPIO_PRE_RAM. + +config SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT + bool + default n + help + Selected ITE SIOs control the GPIO LED frequency using 5 bits + instead of two. The LED register layout is also different for + these chips. Select this if the SIO GP LED Frequency control + field has 5 bits and support duty cycle as well. + +endif + # Generic ITE environment controller driver config SUPERIO_ITE_ENV_CTRL bool diff --git a/src/superio/ite/common/gpio.c b/src/superio/ite/common/gpio.c new file mode 100644 index 0000000..11c02ba --- /dev/null +++ b/src/superio/ite/common/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "ite.h" +#include "ite_gpio.h" + +/* Catch ITE SIOs that enable the driver but do not configure the number of sets */ +#if CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS == 0 +#error "Maximum number of ITE SIO GPIO sets not provided" +#endif + +#if CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS > 10 +#error "ITE SIO GPIO drivers only support up to 10 GPIO sets" +#endif + +/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ +#define ITE_GPIO_REG_POLARITY(x) \ + (((x) > 8) ? (0xd1 + ((x) - 9) * 5) \ + : (0xb0 + ((x) - 1)) \ + ) + +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ +#define ITE_GPIO_REG_PULLUP(x) \ + (((x) > 8) ? (0xd4 + ((x) - 9) * 5) \ + : (0xb8 + ((x) - 1)) \ + ) + +/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ +#define ITE_GPIO_REG_FN_SELECT(x) \ + (((x) > 8) ? (0xd3 + ((x) - 9) * 5) \ + : (0xc0 + ((x) - 1)) \ + ) + +/* GPIO Mode: 0: input mode, 1: output mode */ +#define ITE_GPIO_REG_OUTPUT(x) \ + (((x) > 8) ? (0xd2 + ((x) - 9) * 5) \ + : (0xc8 + ((x) - 1)) \ + ) + +/* GPIO LED pin mapping register */ +#define ITE_GPIO_REG_LED_PINMAP(x) (0xf8 + ((x) & 1) * 2) +#define ITE_GPIO_LED_PIN_LOC(set, pin) ((((set) & 7) << 3) | ((pin) & 7)) +#define ITE_GPIO_LED_PIN_LOC_MASK 0x3f +/* GPIO LED control register */ +#define ITE_GPIO_REG_LED_CONTROL(x) (0xf9 + ((x) & 1) * 2) +#define ITE_GPIO_LED_OUTPUT_LOW (1 << 0) +#define ITE_GPIO_LED_PINMAP_CLEAR (1 << 4) +#define ITE_GPIO_LED_SHORT_LOW_PULSE \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) ? (1 << 5) \ + : (1 << 3) \ + ) +#define ITE_GPIO_LED_FREQ_SEL(x) \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) \ + ? ((((x) & 0x18) << 3) | (((x) & 0x7) << 1)) \ + : (((x) & 0x3) << 1) \ + ) +#define ITE_GPIO_LED_FREQ_SEL_MASK \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) ? 0xce : 0x06) + +static bool ite_has_gpio_fn_select_reg(u8 set) +{ + /* IT8718F has all registers for all sets. */ + if (CONFIG(SUPERIO_ITE_IT8718F)) + return true; + + /* Typically ITE GPIO sets 6 to 8 don't have enable and polarity registers. */ + if (set < 6 || set > 8) + return true; + + return false; +} + +static bool ite_has_gpio_polarity_reg(u8 set) +{ + /* IT8718F has all registers for all sets. */ + if (CONFIG(SUPERIO_ITE_IT8718F)) + return true; + + /* IT8720F/IT8721F has polarity register for all GPIO sets */ + if (CONFIG(SUPERIO_ITE_IT8720F) || CONFIG(SUPERIO_ITE_IT8721F)) + return true; + + /* Typically ITE GPIO sets 6 to 8 don't have enable and polarity registers. */ + if (set < 6 || set > 8) + return true; + + return false; +} + +static bool ite_has_gpio_pullup_reg(u8 set) +{ + /* IT8718F/IT8720F does not have pull-up register for set 2 */ + if ((CONFIG(SUPERIO_ITE_IT8718F) || CONFIG(SUPERIO_ITE_IT8720F)) && (set == 2)) + return false; + + /* IT8783E/F does not have pull-up register for set 6 */ + if (CONFIG(SUPERIO_ITE_IT8783EF) && (set == 6)) + return false; + + /* + * ITE GPIO Sets 7 and 8 don't have a pullup register. + * See IT8786/IT8625 datasheet section 8.10.10. + * Also applies to IT8728F. + */ + if (set != 7 && set != 8) + return true; + + return false; +} + +/* + * Configures a single GPIO given its number as gpio_num, direction ("in_out" + * parameter) and properties, such as polarity and pull ("gpio_ctrl" + * parameter). The "enable" parameter can configure the GPIO in Simple I/O + * mode when set or Alternate function mode when clear. Some chips may also + * not support configuring all properties for a particular GPIO. It is left to + * the implementer to check if GPIO settings are valid for given gpio_num. + */ +void ite_gpio_setup(pnp_devfn_t gpiodev, u8 gpio_num, enum ite_gpio_direction in_out, + enum ite_gpio_mode enable, u8 gpio_ctrl) +{ + u8 set = (gpio_num / 10); + u8 pin = (gpio_num % 10); + + /* Number of configurable sets is chip dependent, 8 pins each */ + if (gpio_num < 10 || set > CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS || pin > 7) + return; + + pnp_enter_conf_state(gpiodev); + pnp_set_logical_device(gpiodev); + + if (ite_has_gpio_fn_select_reg(set)) + pnp_unset_and_set_config(gpiodev, ITE_GPIO_REG_FN_SELECT(set), + 1 << pin, (enable & 1) << pin); + + if (ite_has_gpio_polarity_reg(set)) + pnp_unset_and_set_config(gpiodev, ITE_GPIO_REG_POLARITY(set), + 1 << pin, + (gpio_ctrl & ITE_GPIO_POL_INVERT) ? 1 << pin : 0); + + + pnp_unset_and_set_config(gpiodev, ITE_GPIO_REG_OUTPUT(set), 1 << pin, (in_out & 1) << pin); + + if (ite_has_gpio_pullup_reg(set)) + pnp_unset_and_set_config(gpiodev, ITE_GPIO_REG_PULLUP(set), 1 << pin, + (gpio_ctrl & ITE_GPIO_PULLUP_ENABLE) ? 1 << pin : 0); + + pnp_exit_conf_state(gpiodev); +} + +void ite_gpio_setup_led(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_led led_no, + enum ite_led_frequency freq, + u8 led_ctrl) +{ + u8 set = (gpio_num / 10); + u8 pin = (gpio_num % 10); + u8 reg = 0; + + /* Number of configurable sets is chip dependent, 8 pins each */ + if (gpio_num < 10 || set > CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS || pin > 7) + return; + + /* LED is available only for GPIO sets 1-5 */ + if (set > 5) + return; + + pnp_enter_conf_state(gpiodev); + pnp_set_logical_device(gpiodev); + + /* Pinmap clear bit is only available when frequency is controlled with 5 bits */ + if (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) && (led_ctrl & ITE_LED_PINMAP_CLEAR)) + reg |= ITE_GPIO_LED_PINMAP_CLEAR; + + if (led_ctrl & ITE_LED_OUTPUT_LOW) + reg |= ITE_GPIO_LED_OUTPUT_LOW; + + if (led_ctrl & ITE_LED_SHORT_LOW_PULSE) + reg |= ITE_GPIO_LED_SHORT_LOW_PULSE; + + reg |= ITE_GPIO_LED_FREQ_SEL(freq); + pnp_write_config(gpiodev, ITE_GPIO_REG_LED_CONTROL(led_no), reg); + + reg = ITE_GPIO_LED_PIN_LOC(set, pin); + pnp_write_config(gpiodev, ITE_GPIO_REG_LED_PINMAP(led_no), reg); + + pnp_exit_conf_state(gpiodev); +} diff --git a/src/superio/ite/common/ite_gpio.h b/src/superio/ite/common/ite_gpio.h new file mode 100644 index 0000000..ca1b209 --- /dev/null +++ b/src/superio/ite/common/ite_gpio.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_COMMON_GPIO_PRE_RAM_H +#define SUPERIO_ITE_COMMON_GPIO_PRE_RAM_H + +#include <device/pnp_type.h> +#include <stdint.h> + +#define ITE_GPIO_REG_SELECT(x) (0x25 + (x)) + +enum ite_gpio_control { + ITE_GPIO_CONTROL_DEFAULT = 0, + ITE_GPIO_POL_INVERT = (1 << 0), + ITE_GPIO_PULLUP_ENABLE = (1 << 1), +}; + +enum ite_gpio_direction { + ITE_GPIO_INPUT, + ITE_GPIO_OUTPUT +}; + +enum ite_gpio_mode { + ITE_GPIO_ALT_FN_MODE, + ITE_GPIO_SIMPLE_IO_MODE +}; + +/* There are two GP LED blink register sets */ +enum ite_gpio_led { + ITE_GPIO_LED_1, + ITE_GPIO_LED_2 +}; + +enum ite_led_control { + ITE_LED_CONTROL_DEFAULT = 0, + ITE_LED_SHORT_LOW_PULSE = (1 << 0), + ITE_LED_OUTPUT_LOW = (1 << 1), + /* + * Only for ITE SIOs with 5-bit frequency selection. + * When enabled, the LED pin mapping register is cleared when PANSWH# is low for over 4s. + */ + ITE_LED_PINMAP_CLEAR = (1 << 2), +}; + +enum ite_led_frequency { + /* Most ITE SIOs have 2-bit frequency selection */ + ITE_LED_FREQ_4HZ = 0, + ITE_LED_FREQ_1HZ = 1, + ITE_LED_FREQ_0P25HZ = 2, + ITE_LED_FREQ_0P125HZ = 3, + /* ITE SIOs with 5-bit frequency selection: IT8625, IT8613 */ + ITE_LED_FREQ_4HZ_DUTY_50 = 0, + ITE_LED_FREQ_1HZ_DUTY_50 = 1, + ITE_LED_FREQ_0P25HZ_DUTY_50 = 2, + ITE_LED_FREQ_2HZ_DUTY_50 = 3, + ITE_LED_FREQ_0P25HZ_DUTY_25 = 4, + ITE_LED_FREQ_0P25HZ_DUTY_75 = 5, + ITE_LED_FREQ_0P125HZ_DUTY_25 = 6, + ITE_LED_FREQ_0P125HZ_DUTY_75 = 7, + ITE_LED_FREQ_0P4HZ_DUTY_20 = 8, + ITE_LED_FREQ_0P5HZ_DUTY_50 = 16, + ITE_LED_FREQ_0P125HZ_DUTY_50 = 24, +}; + +void ite_gpio_setup(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_direction output, + enum ite_gpio_mode enable, + u8 gpio_ctrl); + +void ite_gpio_setup_led(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_led led_no, + enum ite_led_frequency freq, + u8 led_ctrl); + + +#endif /* SUPERIO_ITE_COMMON_PRE_RAM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Gerrit-Change-Number: 83355 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email ) Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83356/comment/37b187e0_dc93d74f?us… : PS3, Line 14: of > drop one `of`, and missing line break Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Gerrit-Change-Number: 83356 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 14:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83356?usp=email to look at the new patch set (#4). Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ...................................................................... soc/intel/alderlake/tcss: Add definition of IOM_READY bit Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit for about 2 seconds before FSP Silicon Init to have USB functionality. ME is supposed to start fetching and executing the TCSS IPs FW right after DRAM Init Done message, which happens after MRC. For most platforms the time interval between the end of MemoryInit and start of SiliconInit is enough for IOM_READY to get set. TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci. Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/include/soc/tcss.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83356/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Gerrit-Change-Number: 83356 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email ) Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > Wild thought, because you mentioned fetching fw: Is your flash fast enough? e.g. […] ifdtool says: FLCOMP 0x093030f5 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read eSPI/EC Bus Frequency: 20MHz Component 2 Density: UNUSED Component 1 Density: 16MB So, I think fast read is configured well. -- To view, visit https://review.coreboot.org/c/coreboot/+/83356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Gerrit-Change-Number: 83356 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 14:34:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Julius Werner, Jérémy Compostella, Nico Huber, Philipp Hug, Ron Minnich. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/3f60c9bc_561f61c4?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. > How would that look like? it's not just one linker script, right? > > Actually, it feels like this is xcompile's job. It looks like ARM and ARM64 feature this. Something like: OUTPUT_FORMAT(elf32-i386) OUTPUT_ARCH(i386) needs to be added to header.ld of multiple arch. -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 14:21:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/rauru/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83573/comment/a3ad9c40_363ac0b1?us… : PS6, Line 1: all-y += memlayout.ld src/mainboard/google/rauru/Makefile.mk has no recognized SPDX identifier. -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:56:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83572/comment/573b533a_2334dbb6?us… : PS5, Line 1: ## SPDX-License-Identifier: GPL-2.0-only one blank line below -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:54:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MediaTek common directory
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Xi Chen. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83570?usp=email ) Change subject: soc/mediatek: Move symbols.h into MediaTek common directory ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:52:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Dinesh Gehlot (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Paul Menzel, Rishika Raj, Subrata Banik, Tarun. Dinesh Gehlot has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/df293a85_d424d853?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements Commit message is a bit wordy. Can you make it shorter? ``` soc/intel/mtl: Adjust CAR STACK_SIZE for coreboot compatibility ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
by Jonathon Hall (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Martin L Roth, Nico Huber, Paul Menzel. Jonathon Hall has posted comments on this change by Jonathon Hall. ( https://review.coreboot.org/c/coreboot/+/83476?usp=email ) Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Do we have an example file in the archive to be able to reproduce with QEMU? It's this bootsplash: https://github.com/linuxboot/heads/blob/master/branding/Heads/d-wid-ThePlex… Failure to show the bootsplash was reproducible in qemu from Heads with this. What's the archive, should I upload this somewhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/83476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4348d39effbc16c1b42ab01bcf1e4ec5d652fa9 Gerrit-Change-Number: 83476 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nigel Tao <nigeltao(a)golang.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:20:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Subrata Banik. Nico Huber has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ...................................................................... Patch Set 3: Code-Review+2 (2 comments) Patchset: PS1: > Unfortunately I didn't find documentation of this bit in the Core and Uncore specification. […] Wild thought, because you mentioned fetching fw: Is your flash fast enough? e.g. fast reads allowed in the flash descriptor etc.? Commit Message: https://review.coreboot.org/c/coreboot/+/83356/comment/3d21e0a7_30dbfc95?us… : PS3, Line 14: of drop one `of`, and missing line break -- To view, visit https://review.coreboot.org/c/coreboot/+/83356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Gerrit-Change-Number: 83356 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 13:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/8cf0f144_a3d38121?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. > > Would be nice to do this in smaller steps, e.g. one patch to drop --oformat, […] How would that look like? it's not just one linker script, right? Actually, it feels like this is xcompile's job. -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 12:57:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer. Nico Huber has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I don't like this rule at all. […] I didn't mean this as a general rule. Just for people who want to do bulk style changes without hurting the project. Style changes in general are not bad. It's just bulk changes to adapt to ones own liking that cause trouble. Of course people can just adapt and be done with it. But there are deeper psychological aspects, e.g. somebody who just had to adapt due to bikeshedding might just give up when they are hit by controversial bulk changes on top. With that in mind, I think it just needs balance, a trade-off between cleaning things up and creative work. Please keep in mind that a lot of the creative coreboot work is done unpaid. And unpaid people can just choose not to update their changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 12:45:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: lib/smbios: Create SMBIOS type 4 entry
by Lean Sheng Tan (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83331?usp=email ) Change subject: lib/smbios: Create SMBIOS type 4 entry ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Gerrit-Change-Number: 83331 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 12:36:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Maximilian Brune (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer. Maximilian Brune has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > And now I saw a merge conflict because of this. Please always keep in […] I don't like this rule at all. None one will comply to this and even if they would it would only cause people to not do style changes/enhancements in the first place. You shouldn't care too much about other patches. Just rebase your patches (that is not hard) in case of merge conflicts and be done with it. No need to make it unnecessary complicated -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 12:35:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: arch/x86: Decouple socket type from SoC type
by Lean Sheng Tan (Code Review) 19 Jul '24

19 Jul '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83330?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86: Decouple socket type from SoC type ...................................................................... arch/x86: Decouple socket type from SoC type Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83330 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/smbios.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4fa8612..97d5f24 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -52,16 +52,16 @@ return PROCESSOR_UPGRADE_SOCKET_MPGA604; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) return PROCESSOR_UPGRADE_SOCKET_LGA775; - if (CONFIG(SOC_INTEL_ALDERLAKE)) + if (CONFIG(CPU_INTEL_SOCKET_LGA1700)) return PROCESSOR_UPGRADE_SOCKET_LGA1700; - if (CONFIG(SOC_INTEL_METEORLAKE)) - return PROCESSOR_UPGRADE_OTHER; - if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; - if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + if (CONFIG(CPU_INTEL_SOCKET_LGA4189)) return PROCESSOR_UPGRADE_SOCKET_LGA4189; - if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)) + if (CONFIG(CPU_INTEL_SOCKET_LGA4677)) return PROCESSOR_UPGRADE_SOCKET_LGA4677; + if (CONFIG(CPU_INTEL_SOCKET_LGA3647_1)) + return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; + if (CONFIG(CPU_INTEL_SOCKET_OTHER)) + return PROCESSOR_UPGRADE_OTHER; return PROCESSOR_UPGRADE_UNKNOWN; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Gerrit-Change-Number: 83330 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: cpu/intel: Add socket types
by Lean Sheng Tan (Code Review) 19 Jul '24

19 Jul '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83329?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/intel: Add socket types ...................................................................... cpu/intel: Add socket types Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677. Select the socket type for different boards. For the socket types which are not defined in SMBIOS type4, CPU_INTEL_SOCKET_OTHER could be used. Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83329 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.mk A src/cpu/intel/socket_LGA1700/Kconfig A src/cpu/intel/socket_LGA3647_1/Kconfig A src/cpu/intel/socket_LGA4189/Kconfig A src/cpu/intel/socket_LGA4677/Kconfig A src/cpu/intel/socket_OTHER/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/archercity_crb/Kconfig M src/mainboard/intel/cedarisland_crb/Kconfig M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/ocp/tiogapass/Kconfig 12 files changed, 25 insertions(+), 0 deletions(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 0bbaf02..f28bbdb 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -25,6 +25,11 @@ source "src/cpu/intel/socket_mPGA604/Kconfig" source "src/cpu/intel/socket_441/Kconfig" source "src/cpu/intel/socket_LGA775/Kconfig" +source "src/cpu/intel/socket_LGA1700/Kconfig" +source "src/cpu/intel/socket_LGA3647_1/Kconfig" +source "src/cpu/intel/socket_LGA4189/Kconfig" +source "src/cpu/intel/socket_LGA4677/Kconfig" +source "src/cpu/intel/socket_OTHER/Kconfig" # Architecture specific features source "src/cpu/intel/fit/Kconfig" source "src/cpu/intel/turbo/Kconfig" diff --git a/src/cpu/intel/Makefile.mk b/src/cpu/intel/Makefile.mk index bc8f537..77b4618 100644 --- a/src/cpu/intel/Makefile.mk +++ b/src/cpu/intel/Makefile.mk @@ -17,5 +17,10 @@ subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1700) += socket_LGA1700 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA3647_1) += socket_LGA3647_1 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA4189) += socket_LGA4189 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA4677) += socket_LGA4677 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_OTHER) += socket_OTHER subdirs-y += common diff --git a/src/cpu/intel/socket_LGA1700/Kconfig b/src/cpu/intel/socket_LGA1700/Kconfig new file mode 100644 index 0000000..7597a74 --- /dev/null +++ b/src/cpu/intel/socket_LGA1700/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA1700 + bool diff --git a/src/cpu/intel/socket_LGA3647_1/Kconfig b/src/cpu/intel/socket_LGA3647_1/Kconfig new file mode 100644 index 0000000..a4d3e59 --- /dev/null +++ b/src/cpu/intel/socket_LGA3647_1/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA3647_1 + bool diff --git a/src/cpu/intel/socket_LGA4189/Kconfig b/src/cpu/intel/socket_LGA4189/Kconfig new file mode 100644 index 0000000..39b8be4 --- /dev/null +++ b/src/cpu/intel/socket_LGA4189/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA4189 + bool diff --git a/src/cpu/intel/socket_LGA4677/Kconfig b/src/cpu/intel/socket_LGA4677/Kconfig new file mode 100644 index 0000000..321a0ab --- /dev/null +++ b/src/cpu/intel/socket_LGA4677/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA4677 + bool diff --git a/src/cpu/intel/socket_OTHER/Kconfig b/src/cpu/intel/socket_OTHER/Kconfig new file mode 100644 index 0000000..b544af1 --- /dev/null +++ b/src/cpu/intel/socket_OTHER/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_OTHER + bool diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 5ee091b..0171ebc 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_INTEL_ADLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_LGA1700 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98373 diff --git a/src/mainboard/intel/archercity_crb/Kconfig b/src/mainboard/intel/archercity_crb/Kconfig index 200fa49..4d864d1 100644 --- a/src/mainboard/intel/archercity_crb/Kconfig +++ b/src/mainboard/intel/archercity_crb/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4677 select CONSOLE_OVERRIDE_LOGLEVEL select IPMI_KCS select IPMI_KCS_ROMSTAGE diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig b/src/mainboard/intel/cedarisland_crb/Kconfig index 4e3a1cc..8006667 100644 --- a/src/mainboard/intel/cedarisland_crb/Kconfig +++ b/src/mainboard/intel/cedarisland_crb/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4189 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index bbff4aa..84ebade 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_INTEL_MTLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_OTHER select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index cbfb5c8..f20940f 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_LGA3647_1 select HAVE_ACPI_TABLES select IPMI_KCS select IPMI_KCS_ROMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/83329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Gerrit-Change-Number: 83329 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Julius Werner, Jérémy Compostella, Nico Huber, Philipp Hug, Ron Minnich. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/f4f45fa8_17137a5b?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. > Would be nice to do this in smaller steps, e.g. one patch to drop --oformat, > one to drop LIBGCC_FILE_NAME_ (this one looks like a merge artifact after > switching to COMPILER_RT_ in November 2014 oO). > > And now I just realized why we don't need the `--oformat`. It's because we > use separate toolchains now? i.e. the x86_64 one doesn't support i386 any > more. But wouldn't this break compiling with a host toolchain? I think defining the format in the linker script would be a clean solution to that. -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:58:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Paul Menzel, Rishika Raj, Subrata Banik, Tarun. Nico Huber has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/4d447b27_8427bc79?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements Why the 32KiB? this makes it sound like coreboot would need that much. Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB would provide enough margin (unless something is wrong with the 512). -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rex/variants/screebo: Generate RAM IDs
by Dinesh Gehlot (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Kun Liu, Paul Menzel, Tarun. Dinesh Gehlot has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83501?usp=email ) Change subject: mb/google/rex/variants/screebo: Generate RAM IDs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3 Gerrit-Change-Number: 83501 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:10:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:09:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek: Move memmory macros into MediaTek common directory
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83571?usp=email ) Change subject: soc/mediatek: Move memmory macros into MediaTek common directory ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Gerrit-Change-Number: 83571 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:07:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MediaTek common directory
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83570?usp=email ) Change subject: soc/mediatek: Move symbols.h into MediaTek common directory ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 11:06:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > I think the patch order should be (bottom-up) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 10:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/1fe9781f_5f660b9b?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. > What is the difference to `MT8195` that code cannot be shared? Due to different SoCs architectures, register addresses, and driver parameters, if there are common parts, they will be placed in a common location. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 10:37:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: arch/x86: Build all stages using the same function
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83562?usp=email ) Change subject: arch/x86: Build all stages using the same function ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83562/comment/b1be146e_083cb9a5?us… : PS3, Line 66: $$(COMPILER_RT_FLAGS_$(1)) > *what breaks PPC64* It looks like these are actually linker flags (at least on x86) and the PPC64 options in xcompile are unused atm. -- To view, visit https://review.coreboot.org/c/coreboot/+/83562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Gerrit-Change-Number: 83562 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 10:26:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer. Nico Huber has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: And now I saw a merge conflict because of this. Please always keep in mind that style changes are easily merged but can make the work on actual functional changes that are harder to get merged even harder. I suggest you make a rule of this: Please attend / take over unmerged patches before you do style changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 10:11:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: tree: Use boolean for "eist_enable"
by Elyes Haouas (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Erik van den Bogaert, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Crawford, Werner Zeh. Hello Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Erik van den Bogaert, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83575?usp=email to look at the new patch set (#2). Change subject: tree: Use boolean for "eist_enable" ...................................................................... tree: Use boolean for "eist_enable" Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 47 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/83575/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Gerrit-Change-Number: 83575 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Paul Menzel (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83572/comment/ecc17d4e_0b633fa6?us… : PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'. What is the difference to `MT8195` that code cannot be shared? -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 10:05:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: tree: Use boolean for "eist_enable"
by Elyes Haouas (Code Review) 19 Jul '24

19 Jul '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83575?usp=email ) Change subject: tree: Use boolean for "eist_enable" ...................................................................... tree: Use boolean for "eist_enable" Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/tigerlake/chip.h 43 files changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/83575/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a33ee18..e489e25 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 8999aa3..21661f9 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -36,7 +36,7 @@ subsystemid 0x1025 0x1037 inherit device ref system_agent on # Enable "Enhanced Intel SpeedStep" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 97C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 92e4ba7..59e297c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -4,7 +4,7 @@ register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index f078cdf..11a8749 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -17,7 +17,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index bb896aa..ac4ec46 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -16,7 +16,7 @@ # FSP Configuration register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 7330862..ad735ed 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -19,7 +19,7 @@ register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" # "Intel SpeedStep Technology" - register "eist_enable" = "1" + register "eist_enable" = "true" # DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index db843f5..c0779c6 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -19,7 +19,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25b8d9f..2976deb 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Mapping of USB port # to device #+----------------+-------+-----------------------------------+ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f94e93..97b0c20 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -10,7 +10,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 74780d0..3b07bf7 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -5,7 +5,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ }" - register "eist_enable" = "1" + register "eist_enable" = "true" device domain 0 on subsystemid 0x103c 0x2b5e inherit diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index e6655b5..51d3b26 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -6,7 +6,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9599cec..4f7d7eb 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -7,7 +7,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index f0c8d2d..792a144 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 65ba314..9542049 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index bc000c7..317de80 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -108,7 +108,7 @@ register "s0ix_enable" = "0" # Enable Turbo - register "eist_enable" = "1" + register "eist_enable" = "true" register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index ccfe118..613ecbf 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937..df0dbdf 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ }" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502..9b0357f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "eist_enable" = "1" + register "eist_enable" = "true" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index cc1433d..dfacdea 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index c992c4f..f8e494a 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake - register "eist_enable" = "1" + register "eist_enable" = "true" register "s0ix_enable" = "0" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 80c497b..e26e6b2 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -21,7 +21,7 @@ register "s0ix_enable" = "0" - register "eist_enable" = "1" + register "eist_enable" = "true" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 01ae0f2..5b448f9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -18,7 +18,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index d386397..311d96c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -5,7 +5,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index bbc428e..cf07211 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -15,7 +15,7 @@ register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 6f800cb..f35fe12 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 42047b2..1bf8b47 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 7a3f9fb..64cd913 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -4,7 +4,7 @@ register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" register "enable_c1e" = "1" register "disable_dynamic_tccold_handshake" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c29d7c9..4e8b417 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # Not used but timings left for reference diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 2a4a21a..f5b7a1f 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index c73bef2c..3dcc4ce 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index dee0bf5..3a99ab4 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index aaffd4e..ed0a520 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index ba88a71..5760e66 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index e4658a7..9251440 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 4eea043..cc3c619 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c198ea9..7e3ef0c 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 34105fc..4f5c72d 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 58a4fcf..2bda9dc 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -12,7 +12,7 @@ # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # CPU (soc/intel/tigerlake/cpu.c) # Power limits diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d7a527a..d96249d 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -12,7 +12,7 @@ # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable s0ix, required for TGL-U register "s0ix_enable" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 53d5943..1c5d720 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5330f22..23a3b15 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -259,7 +259,7 @@ uint8_t Heci3Enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable; /* * SerialIO device mode selection: diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 7168369..32a7910 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -297,7 +297,7 @@ uint8_t skip_ext_gfx_scan; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable; /* * When enabled, this feature makes the SoC throttle when the power diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f8d4d49..35c0159 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -287,7 +287,7 @@ uint8_t SkipExtGfxScan; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable; /* Enable C6 DRAM */ uint8_t enable_c6dram; -- To view, visit https://review.coreboot.org/c/coreboot/+/83575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Gerrit-Change-Number: 83575 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: Makefile.mk: Reorganize CFLAGS_common
by Elyes Haouas (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer, Martin L Roth, Nico Huber. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83452?usp=email ) Change subject: Makefile.mk: Reorganize CFLAGS_common ...................................................................... Patch Set 6: (1 comment) File Makefile.mk: https://review.coreboot.org/c/coreboot/+/83452/comment/52f785eb_05c8a9db?us… : PS4, Line 543: CFLAGS_common += -g > Why? I mean, there are more added below. So this is not the end. `gcc -O2 -g -o myprogram mysource.c` here, `O2` and `-g` flags are applied to the mysource.c file. If we place `-g` before lake this: `gcc -g -O2 -o myprogram mysource.c`, the `-O2` flag would override the `-g` flag for the mysource.c file, and debugging information would not be generated. note: I'm thinking about using something like "if debug use -g flag"... -- To view, visit https://review.coreboot.org/c/coreboot/+/83452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3216ef2e0b3cd25f343939d5b9ef932f2f91e56c Gerrit-Change-Number: 83452 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[S] Change in coreboot[main]: arch/x86: Build all stages using the same function
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83562?usp=email ) Change subject: arch/x86: Build all stages using the same function ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83562/comment/8f62489e_7448f13a?us… : PS3, Line 66: $$(COMPILER_RT_FLAGS_$(1)) > I'm guessing this is what PPC64 in the end of the patch train. Is this needed? […] *what breaks PPC64* -- To view, visit https://review.coreboot.org/c/coreboot/+/83562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Gerrit-Change-Number: 83562 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:46:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: arch/x86: Build all stages using the same function
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83562?usp=email ) Change subject: arch/x86: Build all stages using the same function ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83562/comment/e5edc145_c180ac26?us… : PS3, Line 66: $$(COMPILER_RT_FLAGS_$(1)) I'm guessing this is what PPC64 in the end of the patch train. Is this needed? After all, it's compiler flags. -- To view, visit https://review.coreboot.org/c/coreboot/+/83562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Gerrit-Change-Number: 83562 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:45:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/rauru/Makefile.inc: PS2: > Makefile. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:39:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83573?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... mb/google/rauru: Add MediaTek MT8196 reference board Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e --- A src/mainboard/google/rauru/Kconfig A src/mainboard/google/rauru/Kconfig.name A src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/board_info.txt A src/mainboard/google/rauru/bootblock.c A src/mainboard/google/rauru/chromeos.c A src/mainboard/google/rauru/chromeos.fmd A src/mainboard/google/rauru/devicetree.cb A src/mainboard/google/rauru/mainboard.c A src/mainboard/google/rauru/memlayout.ld A src/mainboard/google/rauru/reset.c A src/mainboard/google/rauru/romstage.c 12 files changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > yes, we need CB:83569 before this patch. I think the patch order should be (bottom-up) - mb/google/rauru: Add MediaTek MT8196 reference board - soc/mediatek/mt8196: Add a stub implementation o - util/mtkheader: Add gfh header for mt8196 bootblock code - soc/mediatek: Move memmory macros into MediaTek common directory - soc/mediatek: Move symbols.h into MediaTek common directory -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:38:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: azalia: Get rid of "return {-1,0}
by Elyes Haouas (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Elyes Haouas. Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83503?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: azalia: Get rid of "return {-1,0} ...................................................................... azalia: Get rid of "return {-1,0} Use 'enum cb_err' instead of {-1,0}. Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/soc/intel/common/hda_verb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.c 9 files changed, 36 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/83503/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/83503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e Gerrit-Change-Number: 83503 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 4: (2 comments) Patchset: PS2: > Does this patch depend on CB:83569? yes, we need CB:83569 before this patch. File src/soc/mediatek/mt8196/Makefile.inc: https://review.coreboot.org/c/coreboot/+/83572/comment/722b3e5f_c7e3e02d?us… : PS1, Line 4: ../common/timer_prepare.c > no need. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/2bd695b5_bd48cc4a?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. Would be nice to do this in smaller steps, e.g. one patch to drop --oformat, one to drop LIBGCC_FILE_NAME_ (this one looks like a merge artifact after switching to COMPILER_RT_ in November 2014 oO). And now I just realized why we don't need the `--oformat`. It's because we use separate toolchains now? i.e. the x86_64 one doesn't support i386 any more. But wouldn't this break compiling with a host toolchain? -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: superio/ite,mb: Switch to new ITE GPIO driver
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Matt DeVillier, Nico Huber, Paul Menzel. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83469?usp=email ) Change subject: superio/ite,mb: Switch to new ITE GPIO driver ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83469/comment/e1150894_df6bcc27?us… : PS2, Line 11: > not at all, please do @paulepanter@mailbox.org I think we can resolve this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/83469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Gerrit-Change-Number: 83469 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:31:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/Makefile.inc: PS2: Makefile.mk -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:30:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83572?usp=email to look at the new patch set (#4). Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 328 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: superio/ite,mb: Switch to new ITE GPIO driver
by Michał Żygowski (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Michał Żygowski, Nico Huber, Paul Menzel. Hello Matt DeVillier, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83469?usp=email to look at the new patch set (#5). Change subject: superio/ite,mb: Switch to new ITE GPIO driver ...................................................................... superio/ite,mb: Switch to new ITE GPIO driver Refactor mainboards' code to use the new GPIO driver. TEST=Put Google Jecht to S3 sleep and check if the LED blinks. Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/jecht/led.c M src/mainboard/hp/pro_3500_series/led.c M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c 6 files changed, 72 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83469/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Gerrit-Change-Number: 83469 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83563/comment/dce3d7c3_849bbc73?us… : PS2, Line 9: No assembly.inc file is being generated by romcc anymore. Please also mention "The `-I.` was only used in a single place that can use the common `-Isrc` instead.". -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86: Build all stages using the same function
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83562?usp=email ) Change subject: arch/x86: Build all stages using the same function ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/arch/x86/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83562/comment/416917aa_671eb288?us… : PS1, Line 314: # The rmodule_link definition creates an elf file with .rmod extension. > > Why drop this? […] Oh, right, it's using an implicit rule now... -- To view, visit https://review.coreboot.org/c/coreboot/+/83562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Gerrit-Change-Number: 83562 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:16:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 3: (3 comments) File src/mainboard/google/rauru/Kconfig: https://review.coreboot.org/c/coreboot/+/83573/comment/ba7e556f_e271b6a1?us… : PS1, Line 5: def_bool n > def_bool BOARD_GOOGLE_RAURU Done File src/mainboard/google/rauru/Kconfig.name: https://review.coreboot.org/c/coreboot/+/83573/comment/1fbef90a_98c6f512?us… : PS1, Line 1: comment "Rauru" > ``` […] Done https://review.coreboot.org/c/coreboot/+/83573/comment/bda760d1_0e43038b?us… : PS1, Line 5: select BOARD_GOOGLE_RAURU_COMMON > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:14:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: arch/x86: Link ramstage in one step
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/71910?usp=email ) Change subject: arch/x86: Link ramstage in one step ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d Gerrit-Change-Number: 71910 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:14:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 3: (4 comments) File src/soc/mediatek/mt8196/Kconfig: https://review.coreboot.org/c/coreboot/+/83572/comment/5bd6ab54_6a6183bb?us… : PS1, Line 1: config SOC_MEDIATEK_MT8196 > add SPDX identifier. Done File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/83572/comment/f803ca2d_c7eb4fa6?us… : PS2, Line 5: #include <symbols.h> > I think we need CB:83570 before this patch to have symbols.h. Acknowledged File src/soc/mediatek/mt8196/timer.c: https://review.coreboot.org/c/coreboot/+/83572/comment/0d55f397_47478ed2?us… : PS1, Line 6: #include <soc/timer_common.h> > no need Done https://review.coreboot.org/c/coreboot/+/83572/comment/05afd5ea_e1fdd581?us… : PS1, Line 10: timer_prepare(); > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:14:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83572?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 328 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83573?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified-1 by build bot (Jenkins) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... mb/google/rauru: Add MediaTek MT8196 reference board Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e --- A src/mainboard/google/rauru/Kconfig A src/mainboard/google/rauru/Kconfig.name A src/mainboard/google/rauru/Makefile.inc A src/mainboard/google/rauru/board_info.txt A src/mainboard/google/rauru/bootblock.c A src/mainboard/google/rauru/chromeos.c A src/mainboard/google/rauru/chromeos.fmd A src/mainboard/google/rauru/devicetree.cb A src/mainboard/google/rauru/mainboard.c A src/mainboard/google/rauru/memlayout.ld A src/mainboard/google/rauru/reset.c A src/mainboard/google/rauru/romstage.c 12 files changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: Makefile.mk: Mark stack as not executable
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83560?usp=email ) Change subject: Makefile.mk: Mark stack as not executable ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481 Gerrit-Change-Number: 83560 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:11:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Makefile.mk: Remove linker warning on RWX segments
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83559?usp=email ) Change subject: Makefile.mk: Remove linker warning on RWX segments ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4 Gerrit-Change-Number: 83559 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 09:10:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/83572/comment/975a57c6_56c66cc0?us… : PS2, Line 5: #include <symbols.h> I think we need CB:83570 before this patch to have symbols.h. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:58:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Does this patch depend on CB:83569? -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 2: (2 comments) File src/soc/mediatek/mt8196/Makefile.inc: PS1: > Makefiles should be Makefile.mk not Makefile. […] Done https://review.coreboot.org/c/coreboot/+/83572/comment/b977965b_bf52f353?us… : PS1, Line 1: ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y) > src/soc/mediatek/mt8196/Makefile.inc has no recognized SPDX identifier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move memmory macros into MediaTek common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83571?usp=email ) Change subject: soc/mediatek: Move memmory macros into MediaTek common directory ...................................................................... Patch Set 2: (1 comment) Commit Message: PS1: > Same comments as in CB:83570. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Gerrit-Change-Number: 83571 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:43:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MediaTek common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83570?usp=email ) Change subject: soc/mediatek: Move symbols.h into MediaTek common directory ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83570/comment/28168a72_24dac058?us… : PS1, Line 7: MTK > MediaTek Done https://review.coreboot.org/c/coreboot/+/83570/comment/bdd8be35_e3aacd1d?us… : PS1, Line 9: Because the declaration of MTK SOCs are gernerally the same. : Share a common soc/symbols.h. > To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory […] Done https://review.coreboot.org/c/coreboot/+/83570/comment/d2dd7278_f3c1f220?us… : PS1, Line 13: rauru > There's no such thing (yet). For this patch the test should be something like "Build asurada". Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:42:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83572?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 329 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MediaTek common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Xi Chen, Yidi Lin. Hello Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83570?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: Move symbols.h into MediaTek common directory ...................................................................... soc/mediatek: Move symbols.h into MediaTek common directory To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. BUG=b:317009620 TEST=Build geralt pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/symbols.h D src/soc/mediatek/mt8173/include/soc/symbols.h D src/soc/mediatek/mt8183/include/soc/symbols.h D src/soc/mediatek/mt8186/include/soc/symbols.h D src/soc/mediatek/mt8188/include/soc/symbols.h D src/soc/mediatek/mt8192/include/soc/symbols.h D src/soc/mediatek/mt8195/include/soc/symbols.h 7 files changed, 10 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83570/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move memmory macros into MediaTek common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83571?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: Move memmory macros into MediaTek common directory ...................................................................... soc/mediatek: Move memmory macros into MediaTek common directory To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld 6 files changed, 28 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83571/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Gerrit-Change-Number: 83571 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/rauru/Kconfig: https://review.coreboot.org/c/coreboot/+/83573/comment/0e90b443_41f4bea4?us… : PS1, Line 5: def_bool n def_bool BOARD_GOOGLE_RAURU File src/mainboard/google/rauru/Kconfig.name: https://review.coreboot.org/c/coreboot/+/83573/comment/219ec912_8e570b2d?us… : PS1, Line 1: comment "Rauru" ``` ## SPDX-License-Identifier: GPL-2.0-only ``` https://review.coreboot.org/c/coreboot/+/83573/comment/cfd34768_e6cc92b9?us… : PS1, Line 5: select BOARD_GOOGLE_RAURU_COMMON remove -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 1: (4 comments) File src/soc/mediatek/mt8196/Kconfig: https://review.coreboot.org/c/coreboot/+/83572/comment/a1523a7d_8a220554?us… : PS1, Line 1: config SOC_MEDIATEK_MT8196 add SPDX identifier. File src/soc/mediatek/mt8196/Makefile.inc: https://review.coreboot.org/c/coreboot/+/83572/comment/12bb41ad_88e62a7b?us… : PS1, Line 4: ../common/timer_prepare.c no need. File src/soc/mediatek/mt8196/timer.c: https://review.coreboot.org/c/coreboot/+/83572/comment/8089a53a_fcf680c4?us… : PS1, Line 6: #include <soc/timer_common.h> no need https://review.coreboot.org/c/coreboot/+/83572/comment/5c351bba_fe93ecfb?us… : PS1, Line 10: timer_prepare(); remove -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Angel Pons (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella. Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/sandybridge/mrc_wrapper.S: https://review.coreboot.org/c/coreboot/+/83563/comment/2b788bea_76c758a5?us… : PS2, Line 35: #include <cpu/x86/64bit/prot2long.inc> I guess this change is needed because of the removed `-I` directive -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:24:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Angel Pons (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella. Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:23:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_...
by Angel Pons (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83195?usp=email ) Change subject: soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domain ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf Gerrit-Change-Number: 83195 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:23:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/mtkheader: Add gfh header for mt8196 bootblock code
by Yidi Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83569?usp=email ) Change subject: util/mtkheader: Add gfh header for mt8196 bootblock code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida203a72c23b94b1848418c9727a5788df421eea Gerrit-Change-Number: 83569 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:23:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:09:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/mt8196/Makefile.inc: PS1: Makefiles should be Makefile.mk not Makefile.inc https://review.coreboot.org/c/coreboot/+/83572/comment/63cdc8da_10be87ac?us… : PS1, Line 1: ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y) src/soc/mediatek/mt8196/Makefile.inc has no recognized SPDX identifier. -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:08:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Move memmory macros into MTK common directory
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83571?usp=email ) Change subject: soc/mediatek: Move memmory macros into MTK common directory ...................................................................... Patch Set 1: (1 comment) Commit Message: PS1: Same comments as in CB:83570. -- To view, visit https://review.coreboot.org/c/coreboot/+/83571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Gerrit-Change-Number: 83571 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MTK common directory
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Xi Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83570?usp=email ) Change subject: soc/mediatek: Move symbols.h into MTK common directory ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83570/comment/1bbd77ea_f83857d4?us… : PS1, Line 7: MTK MediaTek https://review.coreboot.org/c/coreboot/+/83570/comment/4b6d4d21_7f075659?us… : PS1, Line 9: Because the declaration of MTK SOCs are gernerally the same. : Share a common soc/symbols.h. To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. https://review.coreboot.org/c/coreboot/+/83570/comment/2032b140_3c380112?us… : PS1, Line 13: rauru There's no such thing (yet). For this patch the test should be something like "Build asurada". -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/mtkheader: Add gfh header for mt8196 bootblock code
by Yu-Ping Wu (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83569?usp=email ) Change subject: util/mtkheader: Add gfh header for mt8196 bootblock code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida203a72c23b94b1848418c9727a5788df421eea Gerrit-Change-Number: 83569 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 08:01:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Makefile.mk: Mark stack as not executable
by Felix Singer (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Nico Huber. Felix Singer has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83560?usp=email ) Change subject: Makefile.mk: Mark stack as not executable ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481 Gerrit-Change-Number: 83560 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 07:54:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Makefile.mk: Remove linker warning on RWX segments
by Felix Singer (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Nico Huber. Felix Singer has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83559?usp=email ) Change subject: Makefile.mk: Remove linker warning on RWX segments ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4 Gerrit-Change-Number: 83559 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 19 Jul 2024 07:54:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Angel Pons, Felix Singer, Jérémy Compostella. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83563?usp=email ) Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83563/comment/48ee7a9e_e0c756ed?us… : PS1, Line 7: arch/x86/Makefile.inc: Remove obsolete romcc reference > Makefile. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 07:49:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: Makefile.mk: Mark stack as not executable
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer, Nico Huber. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83560?usp=email ) Change subject: Makefile.mk: Mark stack as not executable ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83560/comment/a2caef7c_dc99917e?us… : PS2, Line 7: Makefile.inc: Mark stack as not executable > Makefile. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481 Gerrit-Change-Number: 83560 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 07:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: Makefile.mk: Remove linker warning on RWX segments
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Singer, Nico Huber. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83559?usp=email ) Change subject: Makefile.mk: Remove linker warning on RWX segments ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83559/comment/81c444dd_9e30e9a4?us… : PS2, Line 7: Makefile.inc: Remove linker warning on RWX segments > Makefile. […] Done File Makefile.mk: https://review.coreboot.org/c/coreboot/+/83559/comment/10e52e65_db14ba50?us… : PS1, Line 606: ons > *on* Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4 Gerrit-Change-Number: 83559 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 07:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Hello Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83574?usp=email to look at the new patch set (#2). Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Makefile.mk: Add a common link_stage function and use it A few differences with the original link targets: - 'libs' is now supported on all arch even though only x86 uses it - compiler_rt is included on arch that previously did not (arm). This however has no impact as there compiler_rt is not defined for those arch in xcompile - LIBGCC_FILE_NAME_bootblock is not included, but this was not defined anywhere so this is a noop - the x86 --oformat is dropped as it is not needed. Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk M src/arch/arm/Makefile.mk M src/arch/arm64/Makefile.mk M src/arch/ppc64/Makefile.mk M src/arch/riscv/Makefile.mk M src/arch/x86/Makefile.mk 6 files changed, 30 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83574/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

1 0

[M] Change in coreboot[main]: Makefile.inc: Add a common link_stage function and use it
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.inc: Add a common link_stage function and use it ...................................................................... Makefile.inc: Add a common link_stage function and use it A few differences with the original link targets: - 'libs' is now supported on all arch even though only x86 uses it - compiler_rt is included on arch that previously did not (arm). This however has no impact as there compiler_rt is not defined for those arch in xcompile - LIBGCC_FILE_NAME_bootblock is not included, but this was not defined anywhere so this is a noop - the x86 --oformat is dropped as it is not needed. Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk M src/arch/arm/Makefile.mk M src/arch/arm64/Makefile.mk M src/arch/ppc64/Makefile.mk M src/arch/riscv/Makefile.mk M src/arch/x86/Makefile.mk 6 files changed, 30 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83574/1 diff --git a/Makefile.mk b/Makefile.mk index e9ad2cc..ac09712 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1317,6 +1317,15 @@ fi endif # CONFIG_CBFS_VERIFICATION +define link_stage +# $1 stage name + +$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) + @printf " LINK $$(subst $$(obj)/,,$$(@))\n" + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE)) + +endef + ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf diff --git a/src/arch/arm/Makefile.mk b/src/arch/arm/Makefile.mk index b18b137..3f8232f 100644 --- a/src/arch/arm/Makefile.mk +++ b/src/arch/arm/Makefile.mk @@ -43,13 +43,8 @@ bootblock-y += clock.c bootblock-y += stages.c -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group - -$(objcbfs)/decompressor.debug: $$(decompressor-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,decompressor,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group +$(eval $(call link_stage,bootblock)) +$(eval $(call link_stage,decompressor)) endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -59,9 +54,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $$(verstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(call src-to-obj,verstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group +$(eval $(call link_stage,verstage)) verstage-y += boot.c verstage-y += div0.c @@ -92,9 +85,7 @@ rmodules_arm-y += memmove.S rmodules_arm-y += eabi_compat.c -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group +$(eval $(call link_stage,romstage)) endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -122,8 +113,6 @@ rmodules_arm-y += eabi_compat.c ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group +$(eval $(call link_stage,ramstage)) endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk index cb43897..f4ca29b 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -43,13 +43,8 @@ # Build the bootblock -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) - -$(objcbfs)/decompressor.debug: $$(decompressor-objs) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group -T $(call src-to-obj,decompressor,$(CONFIG_MEMLAYOUT_LD_FILE)) +$(eval $(call link_stage,bootblock)) +$(eval $(call link_stage,decompressor)) endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -59,9 +54,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $$(verstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group -T $(call src-to-obj,verstage,$(CONFIG_MEMLAYOUT_LD_FILE)) +$(eval $(call link_stage,verstage)) verstage-y += boot.c verstage-y += div0.c @@ -103,9 +96,7 @@ rmodules_arm64-y += memmove.S rmodules_arm64-y += eabi_compat.c -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) +$(eval $(call link_stage,romstage)) endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -144,9 +135,7 @@ # Build the ramstage -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) +$(eval $(call link_stage,ramstage)) # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/ppc64/Makefile.mk b/src/arch/ppc64/Makefile.mk index 92b1e39..4299e74 100644 --- a/src/arch/ppc64/Makefile.mk +++ b/src/arch/ppc64/Makefile.mk @@ -21,11 +21,7 @@ bootblock-generic-ccopts += $(ppc64_flags) -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ - $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) +$(eval $(call link_stage,bootblock)) endif @@ -48,9 +44,7 @@ # Build the romstage -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) +$(eval $(call link_stage,romstage)) romstage-c-ccopts += $(ppc64_flags) romstage-S-ccopts += $(ppc64_asm_flags) @@ -81,9 +75,7 @@ # Build the ramstage -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) +$(eval $(call link_stage,ramstage)) ramstage-c-ccopts += $(ppc64_flags) ramstage-S-ccopts += $(ppc64_asm_flags) diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index d5defea..f6b210a 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -75,11 +75,7 @@ bootblock-y = bootblock.S -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ - $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) +$(eval $(call link_stage,bootblock)) bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) @@ -100,9 +96,7 @@ # Build the romstage -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) +$(eval $(call link_stage,romstage)) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -131,9 +125,7 @@ # Build the ramstage -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) +$(eval $(call link_stage,ramstage)) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk index 2832ac3..43c7bd4 100644 --- a/src/arch/x86/Makefile.mk +++ b/src/arch/x86/Makefile.mk @@ -51,19 +51,6 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA ############################################################################### -# common support for early assembly includes -############################################################################### - -define x86_stage -# $1 stage name -# $2 oformat - -$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) - @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE)) --oformat $(2) -endef - -############################################################################### # bootblock ############################################################################### @@ -91,11 +78,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -$(eval $(call x86_stage,bootblock,elf32-i386)) -else -$(eval $(call x86_stage,bootblock,elf64-x86-64)) -endif +$(eval $(call link_stage,bootblock)) ifeq ($(CONFIG_BOOTBLOCK_IN_CBFS),y) add_bootblock = \ @@ -144,11 +127,7 @@ verstage-libs ?= -ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y) -$(eval $(call x86_stage,verstage,elf32-i386)) -else -$(eval $(call x86_stage,verstage,elf64-x86-64)) -endif +$(eval $(call link_stage,verstage)) endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 @@ -183,11 +162,7 @@ romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) -$(eval $(call x86_stage,romstage,elf32-i386)) -else -$(eval $(call x86_stage,romstage,elf64-x86-64)) -endif +$(eval $(call link_stage,romstage)) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -g0 @@ -225,11 +200,7 @@ LDFLAGS_postcar += -Map $(objcbfs)/postcar.map -ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) -$(eval $(call x86_stage,postcar,elf32-i386)) -else -$(eval $(call x86_stage,postcar,elf64-x86-64)) -endif +$(eval $(call link_stage,postcar)) $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ @@ -308,11 +279,7 @@ ramstage-libs ?= -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call x86_stage,ramstage,elf32-i386)) -else -$(eval $(call x86_stage,ramstage,elf64-x86-64)) -endif +$(eval $(call link_stage,ramstage)) $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[XS] Change in coreboot[main]: Makefile.mk: Remove linker warning on RWX segments
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83559?usp=email to look at the new patch set (#3). Change subject: Makefile.mk: Remove linker warning on RWX segments ...................................................................... Makefile.mk: Remove linker warning on RWX segments Silence a linker warnings about segments with RWX. Having one segment for all sections is a good design choice as it makes parsing the elf into a loadable binary simpler. Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83559/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4 Gerrit-Change-Number: 83559 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

[XS] Change in coreboot[main]: Makefile.mk: Mark stack as not executable
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83560?usp=email to look at the new patch set (#3). Change subject: Makefile.mk: Mark stack as not executable ...................................................................... Makefile.mk: Mark stack as not executable Suppress the warning: missing .note.GNU-stack section implies executable stack NOTE: This behaviour is deprecated and will be removed in a future version of the linker Since we don't need an executable stack this is fine. Some newer linkers like LLD even default to this. Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83560/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481 Gerrit-Change-Number: 83560 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

[XS] Change in coreboot[main]: arch/x86/Makefile.mk: Remove obsolete romcc reference
by Arthur Heymans (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Angel Pons, Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83563?usp=email to look at the new patch set (#2). Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference ...................................................................... arch/x86/Makefile.mk: Remove obsolete romcc reference No assembly.inc file is being generated by romcc anymore. Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.mk M src/northbridge/intel/sandybridge/mrc_wrapper.S 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/83563/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Gerrit-Change-Number: 83563 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

1 0

[M] Change in coreboot[main]: mb/google/rauru: Add MediaTek MT8196 reference board
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83573?usp=email ) Change subject: mb/google/rauru: Add MediaTek MT8196 reference board ...................................................................... mb/google/rauru: Add MediaTek MT8196 reference board Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e --- A src/mainboard/google/rauru/Kconfig A src/mainboard/google/rauru/Kconfig.name A src/mainboard/google/rauru/Makefile.inc A src/mainboard/google/rauru/board_info.txt A src/mainboard/google/rauru/bootblock.c A src/mainboard/google/rauru/chromeos.c A src/mainboard/google/rauru/chromeos.fmd A src/mainboard/google/rauru/devicetree.cb A src/mainboard/google/rauru/mainboard.c A src/mainboard/google/rauru/memlayout.ld A src/mainboard/google/rauru/reset.c A src/mainboard/google/rauru/romstage.c 12 files changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/1 diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig new file mode 100644 index 0000000..338e048 --- /dev/null +++ b/src/mainboard/google/rauru/Kconfig @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_RAURU_COMMON + def_bool n + +if BOARD_GOOGLE_RAURU_COMMON + +config VBOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8196 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default "google/rauru" + +config MAINBOARD_PART_NUMBER + string + default "Rauru" if BOARD_GOOGLE_RAURU +endif diff --git a/src/mainboard/google/rauru/Kconfig.name b/src/mainboard/google/rauru/Kconfig.name new file mode 100644 index 0000000..eb9444ba --- /dev/null +++ b/src/mainboard/google/rauru/Kconfig.name @@ -0,0 +1,5 @@ +comment "Rauru" + +config BOARD_GOOGLE_RAURU + bool "-> Rauru" + select BOARD_GOOGLE_RAURU_COMMON diff --git a/src/mainboard/google/rauru/Makefile.inc b/src/mainboard/google/rauru/Makefile.inc new file mode 100644 index 0000000..32ef50c --- /dev/null +++ b/src/mainboard/google/rauru/Makefile.inc @@ -0,0 +1,9 @@ +all-y += memlayout.ld +all-y += chromeos.c +all-y += reset.c + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/rauru/board_info.txt b/src/mainboard/google/rauru/board_info.txt new file mode 100644 index 0000000..4b86043 --- /dev/null +++ b/src/mainboard/google/rauru/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Rauru MediaTek MT8196 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c new file mode 100644 index 0000000..97d363f --- /dev/null +++ b/src/mainboard/google/rauru/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ + /* TODO: add mainboard init for bootblock */ +} diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c new file mode 100644 index 0000000..4555b90 --- /dev/null +++ b/src/mainboard/google/rauru/chromeos.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + /* TODO: add ChromeOS specific gpios */ +} diff --git a/src/mainboard/google/rauru/chromeos.fmd b/src/mainboard/google/rauru/chromeos.fmd new file mode 100644 index 0000000..5b2234d --- /dev/null +++ b/src/mainboard/google/rauru/chromeos.fmd @@ -0,0 +1,46 @@ +# Firmware Layout Description for ChromeOS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_GSCVD 8K + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb new file mode 100644 index 0000000..d2288f4 --- /dev/null +++ b/src/mainboard/google/rauru/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8196 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c new file mode 100644 index 0000000..af12d21 --- /dev/null +++ b/src/mainboard/google/rauru/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ + /* TODO: add mainboard init */ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/rauru/memlayout.ld b/src/mainboard/google/rauru/memlayout.ld new file mode 100644 index 0000000..0f1fcec --- /dev/null +++ b/src/mainboard/google/rauru/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/rauru/reset.c b/src/mainboard/google/rauru/reset.c new file mode 100644 index 0000000..3eb1390 --- /dev/null +++ b/src/mainboard/google/rauru/reset.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ + /* TODO: add reset function when gpio is ready */ +} diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c new file mode 100644 index 0000000..0db6fd2 --- /dev/null +++ b/src/mainboard/google/rauru/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> + +void platform_romstage_main(void) +{ + /* TODO: add romstage main function */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Gerrit-Change-Number: 83573 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email ) Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC ...................................................................... soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8196/Kconfig A src/soc/mediatek/mt8196/Makefile.inc A src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/emi.h A src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/include/soc/spi.h A src/soc/mediatek/mt8196/include/soc/timer.h A src/soc/mediatek/mt8196/soc.c A src/soc/mediatek/mt8196/spi.c A src/soc/mediatek/mt8196/timer.c 13 files changed, 328 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83572/1 diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig new file mode 100644 index 0000000..76a2fbc --- /dev/null +++ b/src/soc/mediatek/mt8196/Kconfig @@ -0,0 +1,20 @@ +config SOC_MEDIATEK_MT8196 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + select SOC_MEDIATEK_COMMON + select ARM64_USE_ARCH_TIMER + +if SOC_MEDIATEK_MT8196 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8196/Makefile.inc b/src/soc/mediatek/mt8196/Makefile.inc new file mode 100644 index 0000000..27157c4 --- /dev/null +++ b/src/soc/mediatek/mt8196/Makefile.inc @@ -0,0 +1,22 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y) + +all-$(CONFIG_SPI_FLASH) += spi.c +all-y += timer.c ../common/timer_prepare.c +all-y += ../common/uart.c + +bootblock-y += bootblock.c +bootblock-y += ../common/mmu_operations.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c + +ramstage-y += emi.c +ramstage-y += soc.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c new file mode 100644 index 0000000..f48e78c --- /dev/null +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} diff --git a/src/soc/mediatek/mt8196/emi.c b/src/soc/mediatek/mt8196/emi.c new file mode 100644 index 0000000..62f5ff1 --- /dev/null +++ b/src/soc/mediatek/mt8196/emi.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 3.7 + */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h new file mode 100644 index 0000000..b95e0ea --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C000000, + MCUPM_CFG_BASE = 0x0C240000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE, +}; + +enum { + CKSYS_BASE = IO_PHYS + 0x00000000, + APMIXED_BASE = IO_PHYS + 0x00000800, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + CKSYS_GP2_BASE = IO_PHYS + 0x0000C000, + APMIXEDSYS_GP2_BASE = IO_PHYS + 0x0000C800, + BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, + BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, + GPIO_BASE = IO_PHYS + 0x0002D000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + EMI0_BASE = IO_PHYS + 0x00469000, + EMI0_MPU_BASE = IO_PHYS + 0x00468000, + EMI1_BASE = IO_PHYS + 0x00569000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, + DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, + DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, + DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, + IOCFG_RT_BASE = IO_PHYS + 0x02000000, + IOCFG_RM1_BASE = IO_PHYS + 0x02020000, + IOCFG_RM2_BASE = IO_PHYS + 0x02040000, + IOCFG_RB_BASE = IO_PHYS + 0x02060000, + IOCFG_BM1_BASE = IO_PHYS + 0x02820000, + IOCFG_BM2_BASE = IO_PHYS + 0x02840000, + IOCFG_BM3_BASE = IO_PHYS + 0x02860000, + IOCFG_LT_BASE = IO_PHYS + 0x03000000, + IOCFG_LM1_BASE = IO_PHYS + 0x03020000, + IOCFG_LM2_BASE = IO_PHYS + 0x03040000, + MIPITX0_BASE = IO_PHYS + 0x030b0000, + IOCFG_LB1_BASE = IO_PHYS + 0x030f0000, + IOCFG_LB2_BASE = IO_PHYS + 0x03110000, + EFUSEC_BASE = IO_PHYS + 0x03260000, + IOCFG_TM1_BASE = IO_PHYS + 0x03800000, + IOCFG_TM2_BASE = IO_PHYS + 0x03820000, + IOCFG_TM3_BASE = IO_PHYS + 0x03860000, + THERM_CTRL_BASE = IO_PHYS + 0x04414000, + UART0_BASE = IO_PHYS + 0x06000000, + SPI0_BASE = IO_PHYS + 0x06110000, + SPI1_BASE = IO_PHYS + 0x06130000, + SPI2_BASE = IO_PHYS + 0x06150000, + SPI3_BASE = IO_PHYS + 0x06170000, + SPI4_BASE = IO_PHYS + 0x06190000, + SPI5_BASE = IO_PHYS + 0x061B0000, + SPI6_BASE = IO_PHYS + 0x0619D000, + SPI7_BASE = IO_PHYS + 0x061F0000, + SFLASH_REG_BASE = IO_PHYS + 0x06340000, + PERICFG_AO_BASE = IO_PHYS + 0x06640000, + SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00, + SSUSB_SIF_BASE = IO_PHYS + 0x06730300, + UFSHCI_BASE = IO_PHYS + 0x06810000, + SCP_BASE = IO_PHYS + 0x0C004000, + SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, + RGU_BASE = IO_PHYS + 0x0C010000, + GPT_BASE = IO_PHYS + 0x0C015000, + PMIF_SPMI_P_BASE = IO_PHYS + 0x0C018000, + PMIF_SPMI_BASE = IO_PHYS + 0x0C01A000, + SPMI_MST_BASE = IO_PHYS + 0x0C01C000, + SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, + SYSTIMER_BASE = IO_PHYS + 0x0C400000, + EINT_BASE = IO_PHYS + 0x0C54A000, + DSI0_BASE = IO_PHYS + 0x22490000, + DISP_DVO0 = IO_PHYS + 0x224C0000, + EDP_BASE = IO_PHYS + 0x2EC40000, +}; + +#endif diff --git a/src/soc/mediatek/mt8196/include/soc/emi.h b/src/soc/mediatek/mt8196/include/soc/emi.h new file mode 100644 index 0000000..b7944d9 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/emi.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef SOC_MEDIATEK_MT8196_EMI_H +#define SOC_MEDIATEK_MT8196_EMI_H + +#include <stddef.h> + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8196_EMI_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld new file mode 100644 index 0000000..e0975c7 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/memlayout.h> + +SECTIONS +{ + /* MT8196 has 256KB SRAM. */ + SRAM_START(0x00100000) + /* Regions that need to stay in SRAM. */ + TTB(0x00100000, 28K) + DMA_COHERENT(0x00107000, 4K) + STACK(0x00108000, 15K) + WATCHDOG_TOMBSTONE(0x0010bc00, 4) + /* EMPTY(0x0010bc04, 29K - 4) */ + /* + * MCUPM exchanges data with kernel driver using SRAM 0x00113000 ~ + * 0x0011ffff. The address is hardcoded in MCUPM image. + */ + REGION(mcufw_reserved, 0x00113000, 52K, 4K) + /* End of regions that need to stay in SRAM. */ + /* Regions can be moved to SRAM_L2C. */ + CBFS_MCACHE(0x00120000, 16k) + VBOOT2_WORK(0x00124000, 12K) + FMAP_CACHE(0x00127000, 2k) + TPM_LOG(0x00127800, 2k) + TIMESTAMP(0x00128000, 1k) + /* End of regions that can also be moved to SRAM_L2C. */ + /* EMPTY(0x00128400, 95K) */ + SRAM_END(0x00140000) + + /* + * The L3 (can be used as SRAM_L2C) currently using is 2MB. + * The BootROM has configured all cache as SRAM so we can't use them + * unless if we disable L2C and reconfigure. + */ + SRAM_L2C_START(0x02000000) + #if ENV_ROMSTAGE + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x02000000, 600K) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ + #else + BOOTBLOCK(0x02001000, 60K) + #endif + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) + PRERAM_CBFS_CACHE(0x020DA000, 48K) + PRERAM_CBMEM_CONSOLE(0x020E6000, 340K) + SRAM_L2C_END(0x02200000) + + DRAM_START(0x80000000) + DRAM_DMA(0x80000000, 1M) + POSTRAM_CBFS_CACHE(0x80100000, 2M) + RAMSTAGE(0x80300000, 2M) + + BL31(0x94600000, 0x200000) +} diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h new file mode 100644 index 0000000..6c06f80 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8196_PLL_H +#define SOC_MEDIATEK_MT8196_PLL_H + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* SOC_MEDIATEK_MT8196_PLL_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/spi.h b/src/soc/mediatek/mt8196/include/soc/spi.h new file mode 100644 index 0000000..dffaa7e --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 5.8 + */ + +#ifndef SOC_MEDIATEK_MT8196_SPI_H +#define SOC_MEDIATEK_MT8196_SPI_H + +#include <spi-generic.h> + +#endif diff --git a/src/soc/mediatek/mt8196/include/soc/timer.h b/src/soc/mediatek/mt8196/include/soc/timer.h new file mode 100644 index 0000000..d6422c5 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8196_TIMER_H +#define SOC_MEDIATEK_MT8196_TIMER_H + +#include <soc/timer_v2.h> + +#endif diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c new file mode 100644 index 0000000..b77735c --- /dev/null +++ b/src/soc/mediatek/mt8196/soc.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = noop_set_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8196_ops = { + .name = "SOC Mediatek MT8196", + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c new file mode 100644 index 0000000..fd38fd6 --- /dev/null +++ b/src/soc/mediatek/mt8196/spi.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 5.8 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/spi.h> + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c new file mode 100644 index 0000000..00aaa40 --- /dev/null +++ b/src/soc/mediatek/mt8196/timer.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <soc/timer_common.h> + +void init_timer(void) +{ + timer_prepare(); + + raw_write_cntfrq_el0(13 * MHz); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Gerrit-Change-Number: 83572 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move memmory macros into MTK common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83571?usp=email ) Change subject: soc/mediatek: Move memmory macros into MTK common directory ...................................................................... soc/mediatek: Move memmory macros into MTK common directory Because the memory macros of MTK SOCs are gernerally the same. Share a common memlayout.h. TEST=rauru build pass. BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld 6 files changed, 28 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83571/1 diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h new file mode 100644 index 0000000..f51c2a1 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/memlayout.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 64K) + +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + +#define EARLY_INIT(addr, size) \ + REGION(early_init_data, addr, size, 4) diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 224dbda..c593853 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -1,21 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <memlayout.h> - -#include <arch/header.ld> - -/* - * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) -#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) - -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#include <soc/memlayout.h> SECTIONS { diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index c5d9d08..b1b9027 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -1,23 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <memlayout.h> - -#include <arch/header.ld> - -/* - * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) -#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) -#define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 4) - -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#include <soc/memlayout.h> SECTIONS { diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index f927b60..a47e7c5 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -1,23 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <memlayout.h> - -#include <arch/header.ld> - -/* - * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) -#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) -#define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 64K) - -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#include <soc/memlayout.h> SECTIONS { diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index ed3b71b..3dc386e 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -1,19 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <memlayout.h> -#include <arch/header.ld> -/* - * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) -#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) -#define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 64K) -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#include <soc/memlayout.h> + SECTIONS { /* MT8188 has 192KB SRAM in total. */ diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 06806c5..ec8fa9c 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -1,26 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <memlayout.h> - -#include <arch/header.ld> - -/* - * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) -#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) -#define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 64K) - -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); - -#define EARLY_INIT(addr, size) \ - REGION(early_init_data, addr, size, 4) +#include <soc/memlayout.h> SECTIONS { -- To view, visit https://review.coreboot.org/c/coreboot/+/83571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Gerrit-Change-Number: 83571 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Move symbols.h into MTK common directory
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83570?usp=email ) Change subject: soc/mediatek: Move symbols.h into MTK common directory ...................................................................... soc/mediatek: Move symbols.h into MTK common directory Because the declaration of MTK SOCs are gernerally the same. Share a common soc/symbols.h. BUG=b:317009620 TEST=rauru build pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/symbols.h D src/soc/mediatek/mt8173/include/soc/symbols.h D src/soc/mediatek/mt8183/include/soc/symbols.h D src/soc/mediatek/mt8186/include/soc/symbols.h D src/soc/mediatek/mt8188/include/soc/symbols.h D src/soc/mediatek/mt8192/include/soc/symbols.h D src/soc/mediatek/mt8195/include/soc/symbols.h 7 files changed, 10 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83570/1 diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h new file mode 100644 index 0000000..5e1c705 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/symbols.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef _SOC_MEDIATEK_COMMON_SYMBOLS_H_ +#define _SOC_MEDIATEK_COMMON_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h deleted file mode 100644 index ae5d998..0000000 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ -#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif diff --git a/src/soc/mediatek/mt8183/include/soc/symbols.h b/src/soc/mediatek/mt8183/include/soc/symbols.h deleted file mode 100644 index 2c281b4..0000000 --- a/src/soc/mediatek/mt8183/include/soc/symbols.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_ -#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_ -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8186/include/soc/symbols.h b/src/soc/mediatek/mt8186/include/soc/symbols.h deleted file mode 100644 index 7610224..0000000 --- a/src/soc/mediatek/mt8186/include/soc/symbols.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_MEDIATEK_MT8186_SYMBOLS_H_ -#define _SOC_MEDIATEK_MT8186_SYMBOLS_H_ - -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif /* _SOC_MEDIATEK_MT8186_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8188/include/soc/symbols.h b/src/soc/mediatek/mt8188/include/soc/symbols.h deleted file mode 100644 index fcda1ef..0000000 --- a/src/soc/mediatek/mt8188/include/soc/symbols.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#ifndef _SOC_MEDIATEK_MT8188_SYMBOLS_H_ -#define _SOC_MEDIATEK_MT8188_SYMBOLS_H_ - -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif /* _SOC_MEDIATEK_MT8188_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h deleted file mode 100644 index a7feee7..0000000 --- a/src/soc/mediatek/mt8192/include/soc/symbols.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ -#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8195/include/soc/symbols.h b/src/soc/mediatek/mt8195/include/soc/symbols.h deleted file mode 100644 index 2a102eb..0000000 --- a/src/soc/mediatek/mt8195/include/soc/symbols.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#ifndef _SOC_MEDIATEK_MT8195_SYMBOLS_H_ -#define _SOC_MEDIATEK_MT8195_SYMBOLS_H_ -#include <symbols.h> - -DECLARE_REGION(dram_dma) - -#endif /* _SOC_MEDIATEK_MT8195_SYMBOLS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Gerrit-Change-Number: 83570 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: util/mtkheader: Add gfh header for mt8196 bootblock code
by Jarried Lin (Code Review) 19 Jul '24

19 Jul '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83569?usp=email ) Change subject: util/mtkheader: Add gfh header for mt8196 bootblock code ...................................................................... util/mtkheader: Add gfh header for mt8196 bootblock code TEST=Build Pass. BUG=b:317009620 Change-Id: Ida203a72c23b94b1848418c9727a5788df421eea Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M util/mtkheader/gen-bl-img.py 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83569/1 diff --git a/util/mtkheader/gen-bl-img.py b/util/mtkheader/gen-bl-img.py index 1627a79..3201225 100755 --- a/util/mtkheader/gen-bl-img.py +++ b/util/mtkheader/gen-bl-img.py @@ -23,7 +23,8 @@ def gen_gfh_info(chip, data): entries = { 'mt8173': 0x000C1000, - 'mt8183': 0x00201000 + 'mt8183': 0x00201000, + 'mt8196': 0x02001000, } gfh_format = '<44I' -- To view, visit https://review.coreboot.org/c/coreboot/+/83569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida203a72c23b94b1848418c9727a5788df421eea Gerrit-Change-Number: 83569 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>

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