coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: libpayload/x86: Extend exception handling to x86_64 architecture
by Arthur Heymans (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Julius Werner, Paul Menzel, Subrata Banik. Arthur Heymans has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83036?usp=email ) Change subject: libpayload/x86: Extend exception handling to x86_64 architecture ...................................................................... Patch Set 13: Code-Review+1 (2 comments) File payloads/libpayload/arch/x86/exception_asm_64.S: https://review.coreboot.org/c/coreboot/+/83036/comment/c4c188a6_ed5132cd?us… : PS13, Line 338: offset > > offset 32:63 goes into 8(%rax) > > actually we have marked that zero already https://review.coreboot.org/c/coreboot/+/83036/13/payloads/libpayload/arch/… here, hence, unable to comment here. > > let me add the comment above? > > WDYT? 0 is wrong if you link this payload above 4G. Maybe it's easier https://review.coreboot.org/c/coreboot/+/83036/comment/91705d72_5a9e339f?us… : PS13, Line 338: offset > > offset 32:63 goes into 8(%rax) > > actually we have marked that zero already https://review.coreboot.org/c/coreboot/+/83036/13/payloads/libpayload/arch/… here, hence, unable to comment here. > > let me add the comment above? > > WDYT? diff --git a/payloads/libpayload/arch/x86/exception_asm_64.S b/payloads/ libpayload/arch/x86/exception_asm_64.S index 0ea9af813a..0d4fa13f8f 100644 --- a/payloads/libpayload/arch/x86/exception_asm_64.S +++ b/payloads/libpayload/arch/x86/exception_asm_64.S @@ -267,10 +267,11 @@ gdt_ptr: * for us. */ .macro interrupt_gate target - .long \target - .long \target - .long 0 - .long 0 + .word 0 //updated later + .word 0x20 // Segment + .word 0 // updated later + .word 0xee00 // 64bit interrupt gate + .quad \target // updated later .endm .altmacro @@ -335,10 +336,13 @@ exception_init_asm: /* Set up IDT entries */ mov $idt, %rax 1: - andl $0x0000ffff, (%rax) /* Target code segment offset [15:0] */ - orl $0x00200000, (%rax) /* Target code segment selector */ - andl $0xffff0000, 4(%rax) /* Target code segment offset [31:16] */ - orl $0x0000ee00, 4(%rax) /* Present, Type 64-bit Interrupt Gate */ + movq 8(%rax), %rdi + movw %di, (%rax) + shl $16, %rdi + movw %di, 6(%rax) + shl $16, %rdi + movl %edi, 8(%rax) + movl $0, 12(%rax) add $16, %rax cmp $idt_end, %rax jne 1b I would set the address in the top 8 bytes, copy it in a register and patch up the IDT entry. Does this work? -- To view, visit https://review.coreboot.org/c/coreboot/+/83036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887 Gerrit-Change-Number: 83036 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Jun 2024 15:02:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: libpayload/x86: Extend exception handling to x86_64 architecture
by Subrata Banik (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Arthur Heymans, Julius Werner, Paul Menzel. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83036?usp=email ) Change subject: libpayload/x86: Extend exception handling to x86_64 architecture ...................................................................... Patch Set 14: (1 comment) File payloads/libpayload/arch/x86/exception_asm_64.S: https://review.coreboot.org/c/coreboot/+/83036/comment/8c483b31_a97e129c?us… : PS13, Line 338: offset > > offset 32:63 goes into 8(%rax) > > actually we have marked that zero already https://review.coreboot.org/c/coreboot/+/83036/13/payloads/libpayload/arch/… here, hence, unable to comment here. > > let me add the comment above? > > WDYT? updated a comment above https://review.coreboot.org/c/coreboot/+/83036/14/payloads/libpayload/arch/… original review comment: https://review.coreboot.org/c/coreboot/+/83036/comment/31974d3c_ae7097e8/ -- To view, visit https://review.coreboot.org/c/coreboot/+/83036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887 Gerrit-Change-Number: 83036 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: libpayload/x86: Extend exception handling to x86_64 architecture
by Subrata Banik (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Arthur Heymans, Julius Werner, Paul Menzel. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83036?usp=email ) Change subject: libpayload/x86: Extend exception handling to x86_64 architecture ...................................................................... Patch Set 13: (1 comment) File payloads/libpayload/arch/x86/exception_asm_64.S: https://review.coreboot.org/c/coreboot/+/83036/comment/f5561988_8a17470c?us… : PS13, Line 338: offset > offset 32:63 goes into 8(%rax) actually we have marked that zero already https://review.coreboot.org/c/coreboot/+/83036/13/payloads/libpayload/arch/… here, hence, unable to comment here. let me add the comment above? WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/83036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887 Gerrit-Change-Number: 83036 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
by Arthur Heymans (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Angel Pons, Maximilian Brune, Nico Huber, Philipp Hug, Ron Minnich. Arthur Heymans has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email ) Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access ...................................................................... Patch Set 5: (1 comment) File src/commonlib/bsd/lz4_wrapper.c: https://review.coreboot.org/c/coreboot/+/81910/comment/2adb1d69_38d1aa2e?us… : PS5, Line 14: static uint16_t LZ4_readLE16(const void *src) : { : return *((const uint8_t *)src + 1) << 8 : | *(const uint8_t *)src; : } : : static uint32_t LZ4_readLE32(const void *src) : { : return *((const uint8_t *)src + 3) << 24 : | *((const uint8_t *)src + 2) << 16 : | *((const uint8_t *)src + 1) << 8 : | *(const uint8_t *)src; : } > How about: > > ```suggestion > static uint16_t LZ4_readLE16(const void *src) > { > #if defined(__riscv) > /* RISC-V implementations may trap on any unaligned access. */ > return *((const uint8_t *)src + 1) << 8 > | *(const uint8_t *)src; > #else > return le16toh(*(const uint16_t *)src); > #endif > } > > static uint32_t LZ4_readLE32(const void *src) > { > #if defined(__riscv) > /* RISC-V implementations may trap on any unaligned access. */ > return *((const uint8_t *)src + 3) << 24 > | *((const uint8_t *)src + 2) << 16 > | *((const uint8_t *)src + 1) << 8 > | *(const uint8_t *)src; > #else > return le32toh(*(const uint32_t *)src); > #endif > } > ``` > > If there's any other platforms that need to use the same thing as RISC-V, I would suggest introducing a flag (e.g. a Kconfig symbol or some macro). Unaligned memory access support is optional in riscv so a SOC specific flag would indeed be best. -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:30:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: libpayload/x86: Extend exception handling to x86_64 architecture
by Arthur Heymans (Code Review) 19 Jun '24

19 Jun '24

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[M] Change in coreboot[main]: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures
by Subrata Banik (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/crashlog/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/d1f3a5cb_c4ed64e1?us… : PS15, Line 321: sizeof(uintptr_t) > The address increment should be common for 32 and 64 bit architecture . sizeof(uintptr_t) is 4 bytes because pointers on a 32-bit system are 32 bits wide. On a 64-bit system, its is 8 bytes. if `src_addr` is a pointer then it solves the problem if you follow the suggestion coming from Angel. -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 16 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures
by Sowmya Aralguppe (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/crashlog/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/ab2f9d56_8acf5983?us… : PS15, Line 321: sizeof(uintptr_t) > ```suggestion […] The address increment should be common for 32 and 64 bit architecture . sizeof(uintptr_t) is 4 bytes because pointers on a 32-bit system are 32 bits wide. On a 64-bit system, its is 8 bytes. -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 16 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7
by Kapil Porwal (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Poornima Tom, Pranava Y N, V Sowmya. Kapil Porwal has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83074?usp=email ) Change subject: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7 ...................................................................... Patch Set 3: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Gerrit-Change-Number: 83074 Gerrit-PatchSet: 3 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:12:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7
by Subrata Banik (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Poornima Tom, Pranava Y N, V Sowmya. Subrata Banik has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83074?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7 ...................................................................... Patch Set 3: -Code-Review (2 comments) File src/mainboard/google/brya/variants/nivviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83074/comment/25fd13c2_ca49d1d6?us… : PS3, Line 292: device generic 0 on why there is no WAKE PIN configuration? also, need to set `add_acpi_dma_property` property. https://review.coreboot.org/c/coreboot/+/83074/comment/b572750b_b1c5bfcd?us… : PS3, Line 296: end This is wrong as in WIFI_CATEGORY FW config unable to make CNVi disable for PCIe sku. please follow the suggestion below ``` device ref cnvi_wifi on chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end probe WIFI_CATEGORY WIFI_6 end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Gerrit-Change-Number: 83074 Gerrit-PatchSet: 3 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 19 Jun 2024 14:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures
by Sowmya Aralguppe (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Sowmya Aralguppe, Subrata Banik, Tarun. Hello Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83106?usp=email to look at the new patch set (#16). Change subject: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures ...................................................................... soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> --- M src/soc/intel/alderlake/crashlog.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/tigerlake/crashlog_lib.c 5 files changed, 69 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/83106/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 16 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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