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Change subject: mb/purism/librem_cnl: Prefer include <soc/gpio.h> via <gpio.h>
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Commented on change 82872; we discussed this at the last leadership meeting and the consensus was that including soc/gpio.h from mainboard sources is OK, details in the comment there.
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Change subject: mb/purism/librem_skl: Prefer include <soc/gpio.h> via <gpio.h>
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
@ehaouas@noos.fr, we discussed this at the last leadership meeting, consensus is that we don't want to change these inclusions across the board. Including soc/gpio.h from mainboards is OK.
I don't think the style guide really meant to say that you must include gpio.h instead of soc/gpio.h; it's saying that don't need to include both. gpio.h has include-what-you-use annotations stating it exports soc/gpio.h, which is consistent with that.
Either way, there was agreement that we could edit the style guide for clarity here, and including soc/gpio.h is fine.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83117?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: documentation: Fix evaluation of reStructuredText
......................................................................
documentation: Fix evaluation of reStructuredText
eval_rst isn't a valid directive. Use eval-rst instead. Also, add curly
braces where necessary since the MyST parser requires them.
Change-Id: I68337354e9bd4de4b2c29d4e42c3bb22337fbe06
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83117
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M Documentation/getting_started/writing_documentation.md
M Documentation/mainboard/hp/8560w.md
M Documentation/mainboard/hp/pro_3500_series.md
3 files changed, 6 insertions(+), 6 deletions(-)
Approvals:
Nicholas Chin: Looks good to me, approved
Angel Pons: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md
index 51ea531..b9c30b0 100644
--- a/Documentation/getting_started/writing_documentation.md
+++ b/Documentation/getting_started/writing_documentation.md
@@ -99,7 +99,7 @@
Under Sphinx markdown tables are not supported. Therefore you can use following
code block to write tables in reStructuredText and embed them into the markdown:
- ```eval_rst
+ ```{eval-rst}
+------------+------------+-----------+
| Header 1 | Header 2 | Header 3 |
+============+============+===========+
@@ -144,7 +144,7 @@
You can import CSV files and let sphinx automatically convert them to human
readable tables, using the following reStructuredText snipped:
- ```eval_rst
+ ```{eval-rst}
.. csv-table::
:header: "Key", "Value"
:file: keyvalues.csv
diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md
index babd632..103d912 100644
--- a/Documentation/mainboard/hp/8560w.md
+++ b/Documentation/mainboard/hp/8560w.md
@@ -17,7 +17,7 @@
![8560w_chip_location](8560w_flash.webp)
-```eval_rst
+```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@@ -61,7 +61,7 @@
## Technology
-```eval_rst
+```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3500_series.md
index 241b567..881bf37 100644
--- a/Documentation/mainboard/hp/pro_3500_series.md
+++ b/Documentation/mainboard/hp/pro_3500_series.md
@@ -14,7 +14,7 @@
## Flashing coreboot
-```{eval_rst}
+```{eval-rst}
+---------------------+-------------------------+
| Type | Value |
+=====================+=========================+
@@ -82,7 +82,7 @@
## Technology
-```{eval_rst}
+```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
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Change subject: mb/google/brya/var/nivviks: Enable PCIe Wifi Gpios based on fw_config
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/fw_config.c:
https://review.coreboot.org/c/coreboot/+/83077/comment/e7adedbb_d97fd7f8?us… :
PS6, Line 103: PAD_CFG_GPO
> Another case, i can think of now is , when there is any update for any wifi firmware, don't they prefer to reset it completely?
if wifi fw update required to reset the controller then there should be power sequencing code existed in BIOS/ACPI because none of the kernel driver actually aware how to reset the controller w/o end details about platform.
Better you check with kernel/driver folks, my recommendation is simple, lock the GPO unless there is a valid driver usage. There is no point of argue unless there are some data that says either we need or we don't need to configure those PINs being independent of AP FW.
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Change subject: mb/google/brya/var/nivviks: Enable PCIe Wifi Gpios based on fw_config
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/fw_config.c:
https://review.coreboot.org/c/coreboot/+/83077/comment/eb483e8c_2a9c6919?us… :
PS6, Line 103: PAD_CFG_GPO
> If any such recent vulnerability has been reported recently, i agree that it is risky. […]
Another case, i can think of now is , when there is any update for any wifi firmware, don't they prefer to reset it completely?
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Change subject: mb/google/brya/var/nivviks: Enable PCIe Wifi Gpios based on fw_config
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/fw_config.c:
https://review.coreboot.org/c/coreboot/+/83077/comment/9f4419d5_fd658fbe?us… :
PS6, Line 103: PAD_CFG_GPO
> > Ideally, i think, locking of GPIO becomes relevant, when it is some thing like Write protect signa […]
If any such recent vulnerability has been reported recently, i agree that it is risky. But, what about the regular use case in which user prefer to turn off wifi when not using it and turn it on later based on usage? Doesn't this need a reset for PERST0# ? Also, If we lock it, user will be forced to restart the system completely, inorder to reset PERST0# signal for wifi to turn on again right?
May be we should involve kernel team also to clarify, on how do they actually prefer to turn on and turn off wifi here?
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Hello Andrey Petrov, Krishna P Bhat D, Ronak Kanabar, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: driver/intel/fsp2_0: Prevent error logs during S3 wakeup
......................................................................
driver/intel/fsp2_0: Prevent error logs during S3 wakeup
This patch adds the S3 wakeup check to prevent firmware error logging
that occurred when the system resumed from the S3 state.
BUG=b:348091236
TEST=Verified that no error logs appear during S3 resume on nivviks
Change-Id: I13463b5409e248cf4843c9a887a47d73459972a3
Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com>
---
M src/drivers/intel/fsp2_0/fsp_gop_blt.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83055/4
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Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/commonlib/bsd/lz4_wrapper.c:
https://review.coreboot.org/c/coreboot/+/81910/comment/1cd1064e_d356330f?us… :
PS5, Line 20: LZ4_readLE32
> I don't see a reference to this one?
Nvm it's below
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Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81910/comment/9a76f645_72035f3c?us… :
PS1, Line 18: The coreboot LZ4 decompression code does some misaligned access during
: decompression
> NB. I'd expect that inlining LZ4_readLE16() has a bigger effect.
No the actual lz4c.c.inc is included below and the compiler is sufficiently smart to do that already.
File src/commonlib/bsd/lz4_wrapper.c:
https://review.coreboot.org/c/coreboot/+/81910/comment/7c7bd521_77838ec0?us… :
PS5, Line 20: LZ4_readLE32
I don't see a reference to this one?
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