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Haikun Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82054?usp=email )
Change subject: drivers/mipi: Add support for STA_ER88576 panel
......................................................................
Patch Set 6:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82054/comment/abf35388_26f38b9c :
PS5, Line 9: Add STA panel STA_ER88577 serializable data to CBFS.
> Please mention the datasheet name and revision, and how you wrote the initialization.
Done
https://review.coreboot.org/c/coreboot/+/82054/comment/4615bbb7_803cb0b1 :
PS5, Line 12: include
> includes
Done
File src/drivers/mipi/panel-STA_ER88577.c:
https://review.coreboot.org/c/coreboot/+/82054/comment/e6f818d2_546bff1d :
PS5, Line 57: PANEL_DELAY(120),
> That is quite long.
We need this delay to light up the screen normally, thanks.
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Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
Patch Set 12:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81928/comment/95acd6be_e2faac02 :
PS11, Line 34: Start address = 0x00004000
: End address = 0x00322fff
> I think this should print the actual range, not the enabled range, so these should be 0 (I also left […]
Thank you for your advise, I've update test result in patchset12.
Please help to review, thanks!
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/81928/comment/dcb63ad5_b6dca9cb :
PS11, Line 1749: struct fpsba *fpsba, uint32_t gpr0_offset,
> These arguments are not necessary
Done, thanks!
https://review.coreboot.org/c/coreboot/+/81928/comment/ed20ae1f_ec6ec3ed :
PS11, Line 1753: enabled_gprd_reg.value = fpsba->pchstrp[gpr0_offset];
> This is not necessary (and doesn't do anything since you overwrite all the fields below).
Done, thanks!
https://review.coreboot.org/c/coreboot/+/81928/comment/dfd8d566_b89afe26 :
PS11, Line 1786: union gprd enabled_gprd;
: enabled_gprd = get_enabled_gprd(fpsba, gpr0_offset, image, size);
:
> nit: combine onto one line
Done, thanks!
https://review.coreboot.org/c/coreboot/+/81928/comment/075792c7_7643ea5e :
PS11, Line 1807: union gprd enabled_gprd;
: enabled_gprd = get_enabled_gprd(fpsba, gpr0_offset, image, size);
> nit: combine onto one line
Done, thanks!
https://review.coreboot.org/c/coreboot/+/81928/comment/60f1d036_148363b8 :
PS11, Line 1818: enabled_gprd
> This should be `fpsba->pchstrp[gpr0_offset]` (print the actual range, not the enabled range).
Done, thanks!
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Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81774?usp=email )
(
20 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.
BUG=None
TEST=MIC function is normal
Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
2 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Eric Lai: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 517e4bc..1e10d40 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -8,6 +8,7 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_NAU8825
+ select DRIVERS_I2C_RT5645
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
select DRIVERS_INTEL_PMC
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index c7942c1..2f5b1d2 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -348,15 +348,13 @@
end
end
device ref i2c3 on
- chip drivers/i2c/generic
+ chip drivers/i2c/rt5645
register "hid" = ""10EC5650""
register "name" = ""RT58""
register "desc" = ""Realtek RT5650""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
- register "property_count" = "1"
- register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
- register "property_list[0].name" = ""realtek,jd-mode""
- register "property_list[0].integer" = "2"
+ register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+ register "jd_mode" = "2"
device i2c 1a on end
end
end
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Hello David Wu, Krishna P Bhat D, Reka Norman, Stefan Reinauer, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
util/ifdtool: Add support for checking GPR0 status
This patch adds support for the new command-line option `-c` to
the ifdtool, which is able to check GPR0 (Global Protected Range)
status.
This patch also add helper function get_enabled_gprd() to get enabled
GPR0 settings. It used in enable_gpr0() and is_gpr0_protected().
Developers can use ifdtool with '-c' option to check whether GPR0 is
set to enabled or disabled in the binary file.
BUG=none
TEST=(1) > ifdtool -p mtl -E image-unlocked.bin -O image-lock.bin
...
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
...
GPR0 protection is now enabled
(2) > ifdtool -p mtl -c image-unlocked.bin
GPR0 status: Disabled
Value at GPRD offset (64) is 0x00000000
--------- GPR0 Protected Range --------------
Start address = 0x00000000
End address = 0x00000fff
(3) > ifdtool -p mtl -c image-lock.bin
GPR0 status: Enabled
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7
Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
---
M util/ifdtool/ifdtool.c
1 file changed, 58 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/81928/12
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Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
......................................................................
mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module.
2.Describe the FW_CONFIG probe for the settings on glassway.
- WIFI_SAR_0 for Intel Wi-Fi module AX211
BUG=336051631
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b
Signed-off-by: Daniel_Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/glassway/Makefile.mk
M src/mainboard/google/brya/variants/glassway/overridetree.cb
A src/mainboard/google/brya/variants/glassway/variant.c
4 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81781/3
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Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
......................................................................
Patch Set 2: Code-Review+2
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