April 2024 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Eric Lai (Code Review) 24 Apr '24

24 Apr '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81773?usp=email ) Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... drivers/i2c/rt5645: Add RT5645 amp driver RT5663 is very old and it was used the hard code like RT53 or 10EC5663, which is the different series from RT5645/5650, it may caused some ambiguity. Because I2C generic driver dose not support dsd gpio setting, we declared the new rt5645 series driver for expansion. Add RT5645 AMP support. The kernel driver of 5650 is written in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO. ALC5650 DataSheet Rev 0.93 Realtek upstream link: https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/ Hide the device because of Microsoft Windows. BUG=None TEST=verified in anraggar and probe device rt5650 succeed ``` \_SB.PCI0.I2C3.RT58: Realtek RT5650 ``` Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81773 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- A src/drivers/i2c/rt5645/Kconfig A src/drivers/i2c/rt5645/Makefile.mk A src/drivers/i2c/rt5645/chip.h A src/drivers/i2c/rt5645/rt5645.c 4 files changed, 144 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Kapil Porwal: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/rt5645/Kconfig b/src/drivers/i2c/rt5645/Kconfig new file mode 100644 index 0000000..76cfee8 --- /dev/null +++ b/src/drivers/i2c/rt5645/Kconfig @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_I2C_RT5645 + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/i2c/rt5645/Makefile.mk b/src/drivers/i2c/rt5645/Makefile.mk new file mode 100644 index 0000000..69d5f7e --- /dev/null +++ b/src/drivers/i2c/rt5645/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_I2C_RT5645) += rt5645.c diff --git a/src/drivers/i2c/rt5645/chip.h b/src/drivers/i2c/rt5645/chip.h new file mode 100644 index 0000000..e8537ee --- /dev/null +++ b/src/drivers/i2c/rt5645/chip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> + +struct drivers_i2c_rt5645_config { + const char *desc; /* Device Description */ + const char *name; /* ACPI Device Name */ + const char *hid; /* ACPI _HID */ + struct acpi_gpio cbj_sleeve; /* sleeve power gate GPIO */ + struct acpi_gpio hp_detect; + unsigned int uid; + unsigned int bus_speed; + /* Allow GPIO based interrupt or PIRQ */ + struct acpi_gpio irq_gpio; + struct acpi_irq irq; + uint32_t jd_mode; +}; diff --git a/src/drivers/i2c/rt5645/rt5645.c b/src/drivers/i2c/rt5645/rt5645.c new file mode 100644 index 0000000..28434ee --- /dev/null +++ b/src/drivers/i2c/rt5645/rt5645.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include "chip.h" + +#define RT5645_ACPI_NAME "RT58" +#define RT5645_ACPI_HID "10EC5650" + +#define RT5645_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "realtek," key, (val)) + +static void rt5645_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_rt5645_config *config = dev->chip_info; + const char *path; + const char *scope = acpi_device_scope(dev); + int cbj_sleeve_index = -1, irq_gpio_index = -1, hp_detect_index = -1; + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp; + int curr_index = 0; + + if (!config) + return; + + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + if (config->hid) + acpigen_write_name_string("_HID", config->hid); + else + acpigen_write_name_string("_HID", RT5645_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); + /* Hide the device because of Microsoft Windows */ + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + /* Use either Interrupt() or GpioInt() */ + if (config->irq_gpio.pin_count) + irq_gpio_index = acpi_device_write_dsd_gpio(&config->irq_gpio, + &curr_index); + else + acpi_device_write_interrupt(&config->irq); + + /* Add I2C GPIO index */ + cbj_sleeve_index = acpi_device_write_dsd_gpio(&config->cbj_sleeve, + &curr_index); + hp_detect_index = acpi_device_write_dsd_gpio(&config->hp_detect, + &curr_index); + acpigen_write_resourcetemplate_footer(); + + /* _DSD for devicetree properties */ + /* This points to the first pin in the first gpio entry in _CRS */ + path = acpi_device_path(dev); + dp = acpi_dp_new_table("_DSD"); + if (config->irq_gpio.pin_count) + acpi_dp_add_gpio(dp, "irq-gpios", path, irq_gpio_index, 0, + config->irq_gpio.active_low); + if (config->cbj_sleeve.pin_count) + acpi_dp_add_gpio(dp, "cbj-sleeve-gpios", path, cbj_sleeve_index, 0, + config->cbj_sleeve.active_low); + if (config->hp_detect.pin_count) + acpi_dp_add_gpio(dp, "hp-detect-gpios", path, hp_detect_index, 0, + config->hp_detect.active_low); + RT5645_DP_INT("jd-mode", config->jd_mode); + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh\n", path, + config->desc ? : dev->chip_ops->name, dev->path.i2c.device); +} + +static const char *rt5645_acpi_name(const struct device *dev) +{ + struct drivers_i2c_rt5645_config *config = dev->chip_info; + static char name[5]; + if (config->name) + return config->name; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + return name; +} + +static struct device_operations rt5645_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = rt5645_acpi_name, + .acpi_fill_ssdt = rt5645_fill_ssdt, +}; + +static void rt5645_enable(struct device *dev) +{ + dev->ops = &rt5645_ops; +} + +struct chip_operations drivers_i2c_rt5645_ops = { + .name = "ASoC RT5645 Codec driver", + .enable_dev = rt5645_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 26 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/google/brya/var/nova: Add initial configurations
by Eric Lai (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: David Wu, Dinesh Gehlot, Kapil Porwal, Kenneth Chan, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82043?usp=email ) Change subject: mb/google/brya/var/nova: Add initial configurations ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please don't give +2 by yourself -- To view, visit https://review.coreboot.org/c/coreboot/+/82043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51 Gerrit-Change-Number: 82043 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 06:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya/var/nova: Add initial configurations
by Kenneth Chan (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82043?usp=email ) Change subject: mb/google/brya/var/nova: Add initial configurations ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51 Gerrit-Change-Number: 82043 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Apr 2024 06:01:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/intel/idaville: Porting to Intel Idaville LCC board
by Ziang Wang (Code Review) 23 Apr '24

23 Apr '24

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82074?usp=email ) Change subject: mb/intel/idaville: Porting to Intel Idaville LCC board ...................................................................... mb/intel/idaville: Porting to Intel Idaville LCC board Booted to EDK2 Payload in IDV-LCC simulation. Current workaround: 1. notify.c: Skip FSP notify. 2. pci_device.c: Do not really assign MMIO resource, possibly some memory mapping issues going on. 3. util.c: Hardcode to 1 CPU for now. 4. uncore_acpi.c: Skip most ACPI table creations. Change-Id: I468755a8ade4d5ad438c7b4798f8fe38c201cc14 Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- A bin/FspRel_M.bin A bin/FspRel_S.bin A bin/FspRel_T.bin A bin/UEFIPAYLOAD A bin/m_10_606c1_01000290.mcb A bin/readme.md A configs/builder/config.intel.crb.idv M src/device/pci_device.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/smmstore/store.c A src/mainboard/intel/idaville/Kconfig A src/mainboard/intel/idaville/Kconfig.name A src/mainboard/intel/idaville/Makefile.mk A src/mainboard/intel/idaville/acpi/platform.asl A src/mainboard/intel/idaville/acpi_tables.c A src/mainboard/intel/idaville/board.fmd A src/mainboard/intel/idaville/board_info.txt A src/mainboard/intel/idaville/bootblock.c A src/mainboard/intel/idaville/console.c A src/mainboard/intel/idaville/devicetree.cb A src/mainboard/intel/idaville/dsdt.asl A src/mainboard/intel/idaville/include/idv_pch_gpio.h A src/mainboard/intel/idaville/ramstage.c A src/mainboard/intel/idaville/romstage.c A src/mainboard/intel/idaville/vpd.h M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/hob_display.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h 40 files changed, 2,655 insertions(+), 743 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/82074/1 diff --git a/bin/FspRel_M.bin b/bin/FspRel_M.bin new file mode 100644 index 0000000..a1aa468 --- /dev/null +++ b/bin/FspRel_M.bin Binary files differ diff --git a/bin/FspRel_S.bin b/bin/FspRel_S.bin new file mode 100644 index 0000000..e9de9f5 --- /dev/null +++ b/bin/FspRel_S.bin Binary files differ diff --git a/bin/FspRel_T.bin b/bin/FspRel_T.bin new file mode 100644 index 0000000..32b2f1f --- /dev/null +++ b/bin/FspRel_T.bin Binary files differ diff --git a/bin/UEFIPAYLOAD b/bin/UEFIPAYLOAD new file mode 100644 index 0000000..f46ad80 --- /dev/null +++ b/bin/UEFIPAYLOAD Binary files differ diff --git a/bin/m_10_606c1_01000290.mcb b/bin/m_10_606c1_01000290.mcb new file mode 100644 index 0000000..04ab878 --- /dev/null +++ b/bin/m_10_606c1_01000290.mcb Binary files differ diff --git a/bin/readme.md b/bin/readme.md new file mode 100644 index 0000000..5dcd589 --- /dev/null +++ b/bin/readme.md @@ -0,0 +1,9 @@ +Binaries used here are available from public repos + +FSP: https://github.com/intel/FSP/tree/master/IdavilleFspBinPkg/Lcc/FspBin + +Microcode: https://github.com/slimbootloader/firmwareblob/tree/master/Microcode/Idavil… + +# Important + +Please note that the coreboot.rom built with this patch is 16M, which contains only the BIOS part, you still need to stitch it into a 64M IFWI using [Stitchloader.py](https://github.com/slimbootloader/slimbootloader/blob/mast… \ No newline at end of file diff --git a/configs/builder/config.intel.crb.idv b/configs/builder/config.intel.crb.idv new file mode 100644 index 0000000..e5f4951 --- /dev/null +++ b/configs/builder/config.intel.crb.idv @@ -0,0 +1,22 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass + +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_IDAVILLE=y +#CONFIG_HAVE_IFD_BIN=y +#CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="bin/m_10_606c1_01000290.mcb" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="bin/FspRel_T.bin" +CONFIG_FSP_M_FILE="bin/FspRel_M.bin" +CONFIG_FSP_S_FILE="bin/FspRel_S.bin" +CONFIG_USE_BLOBS=y +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_PAYLOAD_FILE="bin/UEFIPAYLOAD" \ No newline at end of file diff --git a/src/device/pci_device.c b/src/device/pci_device.c index af3355d..719e40a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -603,7 +603,7 @@ if (resource->flags & IORESOURCE_IO) base_lo |= PCI_BASE_ADDRESS_SPACE_IO; - pci_write_config32(dev, resource->index, base_lo); + // pci_write_config32(dev, resource->index, base_lo); if (resource->flags & IORESOURCE_PCI64) pci_write_config32(dev, resource->index + 4, base_hi); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 22bbf53..33adc18 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -61,7 +61,7 @@ fsp_notify_fn fspnotify; uint32_t ret; - if (data->skip) { + if (true) { printk(BIOS_INFO, "coreboot skipped calling FSP notify phase: %08x.\n", phase); return; } diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index f1e07e4..188315f 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -12,6 +12,8 @@ #define SMMSTORE_REGION "SMMSTORE" +#define FMAP_SECTION_SMMSTORE_START 0xd30000 +#define FMAP_SECTION_SMMSTORE_SIZE 0x40000 _Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START, SMM_BLOCK_SIZE), "SMMSTORE FMAP region not aligned to 64K"); diff --git a/src/mainboard/intel/idaville/Kconfig b/src/mainboard/intel/idaville/Kconfig new file mode 100644 index 0000000..719bf49 --- /dev/null +++ b/src/mainboard/intel/idaville/Kconfig @@ -0,0 +1,60 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_IDAVILLE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select SOC_INTEL_SKYLAKE_SP + select SUPERIO_ASPEED_AST2400 + select UART_OVERRIDE_BAUDRATE + select VPD + +config MAINBOARD_DIR + default "intel/idaville" + +config MAINBOARD_PART_NUMBER + default "idaville" + +config MAINBOARD_FAMILY + string + default "idaville" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config UART_FOR_CONSOLE + int + default 0 + +config TTYS0_BAUD + default 115200 + +config TTYS0_BASE + default 0x3f8 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x00070000 + +config DCACHE_RAM_SIZE + hex + default 0xFFF00 + +config FSP_M_RC_HEAP_SIZE + hex + default 0xD0000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x5000 + +config MAX_SOCKET + int + default 1 + +config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR + def_bool y + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/intel/idaville/Kconfig.name b/src/mainboard/intel/idaville/Kconfig.name new file mode 100644 index 0000000..0cc860f --- /dev/null +++ b/src/mainboard/intel/idaville/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_IDAVILLE + bool "Idaville" diff --git a/src/mainboard/intel/idaville/Makefile.mk b/src/mainboard/intel/idaville/Makefile.mk new file mode 100644 index 0000000..1b67017 --- /dev/null +++ b/src/mainboard/intel/idaville/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +ramstage-y += ramstage.c + +all-y += console.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/idaville/acpi/platform.asl b/src/mainboard/intel/idaville/acpi/platform.asl new file mode 100644 index 0000000..13e6fc3 --- /dev/null +++ b/src/mainboard/intel/idaville/acpi/platform.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <arch/x86/acpi/post.asl> \ No newline at end of file diff --git a/src/mainboard/intel/idaville/acpi_tables.c b/src/mainboard/intel/idaville/acpi_tables.c new file mode 100644 index 0000000..b6e3846 --- /dev/null +++ b/src/mainboard/intel/idaville/acpi_tables.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/intel/idaville/board.fmd b/src/mainboard/intel/idaville/board.fmd new file mode 100644 index 0000000..1c407e0 --- /dev/null +++ b/src/mainboard/intel/idaville/board.fmd @@ -0,0 +1,12 @@ +FLASH 16M { + MISC_RW@0x0 0x10000 { + RW_VPD(PRESERVE)@0x0 0x4000 + } + WP_RO@0x10000 0xff0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0xfec000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfeb800 + } + } +} diff --git a/src/mainboard/intel/idaville/board_info.txt b/src/mainboard/intel/idaville/board_info.txt new file mode 100644 index 0000000..81876f5 --- /dev/null +++ b/src/mainboard/intel/idaville/board_info.txt @@ -0,0 +1,5 @@ +Board name: Idaville +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 20xx diff --git a/src/mainboard/intel/idaville/bootblock.c b/src/mainboard/intel/idaville/bootblock.c new file mode 100644 index 0000000..a3265a6 --- /dev/null +++ b/src/mainboard/intel/idaville/bootblock.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> +#include <idv_pch_gpio.h> +#include <arch/mmio.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 +#define PCI_DEVICE_NUMBER_PCH_HSUART 26 +#define PCI_FUNCTION_NUMBER_PCH_HSUART0 0 + + +#define MM_PCI_ADDRESS(Bus, Device, Function, Register) \ +(0x80000000 + \ + (UINTN)((Bus) << 20) + \ + (UINTN)((Device) << 15) + \ + (UINTN)((Function) << 12) + \ + (UINTN)(Register) \ +) + +static void PlatformHookSerialPortInitialize(void) +{ + uint32_t BaseAddr = 0; + BaseAddr = MM_PCI_ADDRESS(DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_HSUART, + PCI_FUNCTION_NUMBER_PCH_HSUART0, + 0); + + uint16_t tmp = read16((void *)(BaseAddr + PCI_COMMAND)); + tmp |= (uint16_t) ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + write16((void *)(BaseAddr + PCI_COMMAND), tmp); + + write32((void *)(BaseAddr + PCI_BASE_ADDRESS_0), 0x3F8); + write16((void *)(BaseAddr + PCI_COMMAND), (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); +} + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_s_write_config32(PCH_DEV_LPC, 0x80, + (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* pre-configure Lewisburg PCH GPIO pads */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + PlatformHookSerialPortInitialize(); + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); + aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); + + /* Enable UART function pin */ + aspeed_enable_uart_pin(serial_dev); +} diff --git a/src/mainboard/intel/idaville/console.c b/src/mainboard/intel/idaville/console.c new file mode 100644 index 0000000..21ee09c --- /dev/null +++ b/src/mainboard/intel/idaville/console.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/uart.h> + +unsigned int get_uart_baudrate(void) +{ + /* SOL console baud rate. */ + return 115200; +} diff --git a/src/mainboard/intel/idaville/devicetree.cb b/src/mainboard/intel/idaville/devicetree.cb new file mode 100644 index 0000000..721d8cb --- /dev/null +++ b/src/mainboard/intel/idaville/devicetree.cb @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/skx + + device cpu_cluster 0 on end + + device domain 0 on + device gpio 0 alias pch_gpio on end + device pci 00.0 on end # Host bridge + end +end diff --git a/src/mainboard/intel/idaville/dsdt.asl b/src/mainboard/intel/idaville/dsdt.asl new file mode 100644 index 0000000..06145c4 --- /dev/null +++ b/src/mainboard/intel/idaville/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/xeon_sp/acpi/uncore.asl> + Scope (\_SB.PC00) + { + #include <soc/intel/xeon_sp/acpi/pch.asl> + } +} diff --git a/src/mainboard/intel/idaville/include/idv_pch_gpio.h b/src/mainboard/intel/idaville/include/idv_pch_gpio.h new file mode 100644 index 0000000..c84a0d9 --- /dev/null +++ b/src/mainboard/intel/idaville/include/idv_pch_gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_PCH_GPIO_H +#define CFG_PCH_GPIO_H + +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1) +}; + +#endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/intel/idaville/ramstage.c b/src/mainboard/intel/idaville/ramstage.c new file mode 100644 index 0000000..85d7ac1 --- /dev/null +++ b/src/mainboard/intel/idaville/ramstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ocp/dmi/ocp_dmi.h> +#include <soc/ramstage.h> +#include <soc/smmrelocate.h> + +extern struct fru_info_str fru_strings; + + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} + +static void mainboard_enable(struct device *dev) +{ +} + +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/intel/idaville/romstage.c b/src/mainboard/intel/idaville/romstage.c new file mode 100644 index 0000000..17124b3 --- /dev/null +++ b/src/mainboard/intel/idaville/romstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <FspmUpd.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> +#include <soc/romstage.h> +#include <string.h> +#include <gpio.h> +#include <soc/gpio_soc_defs.h> + +static BL_SYSTEM_PCI_BASE_LIMITS iio_res; + +static void oem_update_iio(FSPM_UPD *mupd) +{ +} + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + mupd->FspmConfig.PcdBifurcationPcie0 = 9; + mupd->FspmConfig.PcdBifurcationPcie1 = 5; + mupd->FspmConfig.PcdBifurcationPcie2 = 6; + + mupd->FspmConfig.PcdPcieRootPortEn = 0xFFF; + + mupd->FspmConfig.PcdIIOPciePortBifurcation = 0xFF; + mupd->FspmConfig.PcdIIOPciePort2Bifurcation = 0; + + for (int stack = 0; stack < BL_MAX_LOGIC_IIO_STACK; stack++) { + iio_res.Socket[0].StackLimits[stack].IoBase = 0; + iio_res.Socket[0].StackLimits[stack].IoLimit = 0; + iio_res.Socket[0].StackLimits[stack].LowMmioBase = 0; + iio_res.Socket[0].StackLimits[stack].LowMmioLimit = 0; + iio_res.Socket[0].StackLimits[stack].HighMmioBase = 0; + iio_res.Socket[0].StackLimits[stack].HighMmioLimit = 0; + } + mupd->FspmConfig.PcdIioResConfigPtr = (uint32_t) &iio_res; + + oem_update_iio(mupd); +} + +void mainboard_memory_init_params(FSPM_UPD *FspmUpd) +{ + mainboard_config_iio(FspmUpd); + // FspmUpd->FspmArchUpd.StackBase = 0xFE800000 + 0x40000 + 0x7000 + 0x19000; + // FspmUpd->FspmArchUpd.StackSize = 0xFE800000 + 0xFFF00 - FspmUpd->FspmArchUpd.StackBase; + + /* do not configure GPIO controller inside FSP-M */ + // mupd->FspmConfig.GpioConfig.GpioTable = NULL; + // mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; + FspmUpd->FspmConfig.PcdHsuartDevice = 0; + FspmUpd->FspmConfig.PcdFspDebugPrintErrorLevel = 2; + FspmUpd->FspmConfig.PcdPchDmiAspm = 0; + FspmUpd->FspmConfig.PcdPchLegacyIoLowLatency = 0; + FspmUpd->FspmConfig.PcdProcessorEistEnable = 0; + FspmUpd->FspmConfig.PcdProcessorHWPMEnable = 0; + FspmUpd->FspmConfig.PcdPackageCState = 0; + FspmUpd->FspmConfig.PcdMonitorMWait = 0; + FspmUpd->FspmConfig.PcdPowerLimit1Enable = 0; + FspmUpd->FspmConfig.PcdPowerLimit2Enable = 0; + FspmUpd->FspmConfig.PcdTurboMode = 0; + FspmUpd->FspmConfig.PcdDramRaplEnable = 0; + FspmUpd->FspmConfig.PcdCkeProgramming = 1; + FspmUpd->FspmConfig.PcdApdEnable = 0; + FspmUpd->FspmConfig.PcdPpdEnable = 0; + FspmUpd->FspmConfig.PcdPcieGlobalAspm = 0; + FspmUpd->FspmConfig.PcdHyperThreading = 0; +} diff --git a/src/mainboard/intel/idaville/vpd.h b/src/mainboard/intel/idaville/vpd.h new file mode 100644 index 0000000..9309884 --- /dev/null +++ b/src/mainboard/intel/idaville/vpd.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef IDAVILLE_VPD_H +#define IDAVILLE_VPD_H + +#endif /* IDAVILLE_VPD_H */ diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 3e9922f6..beabc87 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -53,11 +53,11 @@ .CodeRegionLength = (UINT32)CACHE_ROM_SIZE, .Reserved1 = {0}, }, - .FsptConfig = { - .FsptPort80RouteDisable = 0, - .ReservedTempRamInitUpd = {0}, - }, - .UnusedUpdSpace0 = {0}, + // .FsptConfig = { + // .FsptPort80RouteDisable = 0, + // .ReservedTempRamInitUpd = {0}, + // }, + // .UnusedUpdSpace0 = {0}, .UpdTerminator = 0x55AA, }; #endif //(!CONFIG(PLATFORM_USES_FSP2_4)) diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index d0eab02..831067c 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -196,17 +196,22 @@ union xeon_domain_path dn = { .domain_path = 0 }; if (!hob) return; - + uint8_t uc1_inited = 0; struct bus *root_bus = dev_root.downstream; for (int s = 0; s < CONFIG_MAX_SOCKET; ++s) { if (!soc_cpu_is_enabled(s)) continue; - for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { + for (int x = 0; x < BL_MAX_LOGIC_IIO_STACK; ++x) { const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; const size_t seg = hob->PlatformData.CpuQpiInfo[s].PcieSegment; - - if (ri->BusBase > ri->BusLimit) - continue; + printk(BIOS_INFO, "ri->BusBase=0x%x, BusLimit=0x%x\n", ri->BusBase, ri->BusLimit); + // if (ri->BusBase > ri->BusLimit) + // continue; + if (ri->BusBase == 0xff) { + if (uc1_inited) + continue; + uc1_inited = 1; + } /* Prepare domain path */ dn.socket = s; diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 9e25920..7fdc2c5 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -22,6 +22,6 @@ { lpc_lockdown_config(); pmc_lockdown_config(); - sata_lockdown_config(chipset_lockdown); + // sata_lockdown_config(chipset_lockdown); spi_lockdown_config(chipset_lockdown); } diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 009527c..3e437b1 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -147,6 +147,8 @@ .init = xeon_sp_core_init, }; +#define CPUID_ICELAKE_D_LLC 0x606C1 + static const struct cpu_device_id cpu_table[] = { /* Skylake-SP A0/A1 CPUID 0x506f0*/ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1, CPUID_EXACT_MATCH_MASK }, @@ -154,6 +156,7 @@ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0, CPUID_EXACT_MATCH_MASK }, /* Skylake-SP 4 CPUID 0x50654*/ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4, CPUID_EXACT_MATCH_MASK }, + {X86_VENDOR_INTEL, CPUID_ICELAKE_D_LLC, CPUID_EXACT_MATCH_MASK }, CPU_TABLE_END }; diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c index bc65e64..2c9a9fc 100644 --- a/src/soc/intel/xeon_sp/skx/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -95,50 +95,50 @@ printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n"); printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n"); - printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType); - printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType); - printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType); - printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); - for (int x = 0; x < MAX_SOCKET; ++x) { - printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, " - "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n", - x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x], - hob->SystemStatus.MaxCoreToBusRatio[x], - hob->SystemStatus.MinCoreToBusRatio[x]); - } - printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n", - hob->SystemStatus.CurrentCoreToBusRatio); - printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n", - hob->SystemStatus.IntelSpeedSelectCapable); - printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n", - hob->SystemStatus.IssConfigTdpLevelInfo); - for (int x = 0; x < TDP_MAX_LEVEL; ++x) { - printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, " - "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n", - x, hob->SystemStatus.IssConfigTdpTdpInfo[x], - hob->SystemStatus.IssConfigTdpPowerInfo[x], - hob->SystemStatus.IssConfigTdpCoreCount[x]); - } - printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n", - hob->SystemStatus.socketPresentBitMap); + // printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType); + // printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType); + // printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType); + // printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); + // for (int x = 0; x < MAX_SOCKET; ++x) { + // printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, " + // "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n", + // x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x], + // hob->SystemStatus.MaxCoreToBusRatio[x], + // hob->SystemStatus.MinCoreToBusRatio[x]); + // } + // printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n", + // hob->SystemStatus.CurrentCoreToBusRatio); + // printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n", + // hob->SystemStatus.IntelSpeedSelectCapable); + // printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n", + // hob->SystemStatus.IssConfigTdpLevelInfo); + // for (int x = 0; x < TDP_MAX_LEVEL; ++x) { + // printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, " + // "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n", + // x, hob->SystemStatus.IssConfigTdpTdpInfo[x], + // hob->SystemStatus.IssConfigTdpPowerInfo[x], + // hob->SystemStatus.IssConfigTdpCoreCount[x]); + // } + // printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n", + // hob->SystemStatus.socketPresentBitMap); printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit); printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit); - printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase); - printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC); - printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh); - printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC); + // printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase); + // printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC); + // printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh); + // printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC); printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); - printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", - hob->PlatformData.PlatGlobalMmiolBase); - printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", - hob->PlatformData.PlatGlobalMmiolLimit); - printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", - hob->PlatformData.PlatGlobalMmiohBase); - printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", - hob->PlatformData.PlatGlobalMmiohLimit); + // printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", + // hob->PlatformData.PlatGlobalMmiolBase); + // printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", + // hob->PlatformData.PlatGlobalMmiolLimit); + // printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", + // hob->PlatformData.PlatGlobalMmiohBase); + // printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", + // hob->PlatformData.PlatGlobalMmiohLimit); printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); @@ -148,8 +148,8 @@ printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber); printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity); printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity); - printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", - hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); + // printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", + // hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); for (int s = 0; s < MAX_SOCKET; ++s) { printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s); @@ -167,14 +167,14 @@ hob->PlatformData.IIO_resource[s].IoApicBase); printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].IoApicLimit); - printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceMem32Base); - printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); - printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", - hob->PlatformData.IIO_resource[s].PciResourceMem64Base); - printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", - hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); + // printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", + // hob->PlatformData.IIO_resource[s].PciResourceMem32Base); + // printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", + // hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); + // printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", + // hob->PlatformData.IIO_resource[s].PciResourceMem64Base); + // printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", + // hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); for (int x = 0; x < MAX_IIO_STACK; ++x) { @@ -199,22 +199,22 @@ printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress); } - printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[s]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", - p, iio_resource.PcieInfo.PortInfo[p].Device, - iio_resource.PcieInfo.PortInfo[p].Function); - } + // printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); + // IIO_RESOURCE_INSTANCE iio_resource = + // hob->PlatformData.IIO_resource[s]; + // for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + // printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", + // p, iio_resource.PcieInfo.PortInfo[p].Device, + // iio_resource.PcieInfo.PortInfo[p].Function); + // } } - printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n"); - for (int socket = 0; socket < MAX_SOCKET; ++socket) { - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", - socket, stack, - hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]); - } - } + // printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n"); + // for (int socket = 0; socket < MAX_SOCKET; ++socket) { + // for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + // printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", + // socket, stack, + // hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]); + // } + // } } diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index ec52153..56956ab 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -35,10 +35,10 @@ #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR1_FUN 1 -#define PCU_CR1_DEVID 0x2081 +#define PCU_CR1_DEVID 0x3459 #define PCU_CR0_FUN 0 -#define PCU_CR0_DEVID 0x2080 +#define PCU_CR0_DEVID 0x3458 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 @@ -136,9 +136,9 @@ #define CHA_UTIL_ALL_FUNC 1 #define CHA_UTIL_ALL_MMCFG_CSR 0xc0 -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 -#define VTD_DEV_NUM 0x5 +#define MMAP_VTD_CFG_REG_DEVID 0x09a2 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x09a2 +#define VTD_DEV_NUM 0x0 #define VTD_FUNC_NUM 0x0 #if !defined(__SIMPLE_DEVICE__) diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index a5c78f6..0f038cd 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -9,18 +9,18 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + // const config_t *config = config_of_soc(); + // FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - mupd->FspmUpdVersion = FSP_UPD_VERSION; + // mupd->FspmUpdVersion = FSP_UPD_VERSION; // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + // m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + // m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; mainboard_memory_init_params(mupd); - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; + // m_cfg->VTdConfig.VTdSupport = config->vtd_support; + // m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + // m_cfg->VTdConfig.ATS = config->ats_support; } diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 6f48246..d330863 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -57,6 +57,8 @@ bool is_pcie_iio_stack_res(const STACK_RES *res) { + if (res->BusBase == 0xff) + return true; return res->BusBase < res->BusLimit; } @@ -156,42 +158,42 @@ * 5A..4D PSTACK3 stack 4 IOU4 * 5A..5D PSTACK4 stack 5 IOU5 */ -int soc_get_stack_for_port(int port) -{ - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -} +// int soc_get_stack_for_port(int port) +// { +// if (port == PORT_0) +// return CSTACK; +// else if (port >= PORT_1A && port <= PORT_1D) +// return PSTACK0; +// else if (port >= PORT_2A && port <= PORT_2D) +// return PSTACK1; +// else if (port >= PORT_3A && port <= PORT_3D) +// return PSTACK2; +// else if (port >= PORT_4A && port <= PORT_4D) +// return PSTACK3; // MCP0 +// else if (port >= PORT_5A && port <= PORT_5D) +// return PSTACK4; // MCP1 +// else +// return -1; +// } uint8_t soc_get_iio_ioapicid(int socket, int stack) { uint8_t ioapic_id = socket ? 0xf : 0x9; - switch (stack) { - case CSTACK: - break; - case PSTACK0: - ioapic_id += 1; - break; - case PSTACK1: - ioapic_id += 2; - break; - case PSTACK2: - ioapic_id += 3; - break; - default: - return 0xff; - } + //switch (stack) { + //case CSTACK: + // break; + //case PSTACK0: + // ioapic_id += 1; + // break; + //case PSTACK1: + // ioapic_id += 2; + // break; + //case PSTACK2: + // ioapic_id += 3; + // break; + //default: + // return 0xff; + //} return ioapic_id; } diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index bcfb4da..5ea8000 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -302,15 +302,15 @@ APIC_DEV_NUM, APIC_FUNC_NUM); // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } + // if (socket != 0 && stack == CSTACK) { + // for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + // printk(BIOS_DEBUG, " [PCI Endpoint Device] " + // "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + // bus, CBDMA_DEV_NUM, cbdma_func_id); + // current += acpi_create_dmar_ds_pci(current, + // bus, CBDMA_DEV_NUM, cbdma_func_id); + // } + // } #endif // Add PCIe Ports @@ -325,14 +325,14 @@ #if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } + // if (hob->PlatformData.VMDStackEnable[socket][stack] && + // stack >= PSTACK0 && stack <= PSTACK2) { + // printk(BIOS_DEBUG, " [PCI Endpoint Device] " + // "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + // bus, VMD_DEV_NUM, VMD_FUNC_NUM); + // current += acpi_create_dmar_ds_pci(current, + // bus, VMD_DEV_NUM, VMD_FUNC_NUM); + // } #endif } @@ -573,7 +573,7 @@ acpi_cedt_t *cedt; const config_t *const config = config_of(device); - + if (!CONFIG(BOARD_IDAVILLE)) { /* SRAT */ current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); @@ -634,6 +634,7 @@ printk(BIOS_DEBUG, "ACPI: * HEST at %lx\n", current); current = hest_create(current, rsdp); } + } return current; } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 81dc77d..c865c28 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -54,7 +54,7 @@ int get_platform_thread_count(void) { - return soc_get_num_cpus() * get_threads_per_package(); + return 1 * get_threads_per_package(); } const IIO_UDS *get_iio_uds(void) @@ -77,7 +77,7 @@ */ bool soc_cpu_is_enabled(const size_t idx) { - const IIO_UDS *hob = get_iio_uds(); + const BL_IIO_UDS *hob = (BL_IIO_UDS *) get_iio_uds(); assert(idx < CONFIG_MAX_SOCKET); return hob->PlatformData.IIO_resource[idx].Valid; @@ -85,7 +85,7 @@ unsigned int soc_get_num_cpus(void) { - return get_iio_uds()->SystemStatus.numCpus; + return ((BL_IIO_UDS *) get_iio_uds())->SystemStatus.numCpus; } #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h index daa0bb4..b2d83c4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2023, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,11 +37,11 @@ #pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C4E41 /* 'ANLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E41 /* 'ANLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C4E41 /* 'ANLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 7a6ecb1..7d9b437 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2023, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,528 +37,1524 @@ #pragma pack(1) -/** - FSP Header Version Number -**/ -#define FSP_UPD_VERSION (0x1947) +#define MAX_CHANNEL 3 /* Maximum Number of Memory Channels */ +#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */ +#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */ +#define MAX_USB_PORTS 4 -#define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */ -#define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */ +/* +* SMBIOS Memory Info structures. +*/ +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20]; /* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; -#define HIDE 1 -#define NOT_HIDE 0 +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMM]; +} CHANNEL_INFO; -#define IIO_BIFURCATE_AUTO 0xFF +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT16 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNEL]; +} FSP_SMBIOS_MEMORY_INFO; -/* Ports 1D-1A, 2D-2A, 3D-3A */ -#define IIO_BIFURCATE_x4x4x4x4 0 -#define IIO_BIFURCATE_x4x4xxx8 1 -#define IIO_BIFURCATE_xxx8x4x4 2 -#define IIO_BIFURCATE_xxx8xxx8 3 -#define IIO_BIFURCATE_xxxxxx16 4 -#define IIO_BIFURCATE_xxxxxxxx 0xF +typedef struct { + UINT32 PerfSig; + UINT16 PerfLen; + UINT16 Reserved4; + UINT32 PerfIdx; + UINT64 PerfData[32]; +} FSP_PERF_INFO; +#define BL_MAX_FIA_LANES 24 +#define BL_FIA_LANE_OVERRIDE_DISABLED 0xff +#define BL_FIA_LANE_DISABLED 0x0 +#define BL_FIA_LANE_PCIE 0x1 +#define BL_FIA_LANE_SATA 0x2 +#define BL_FIA_LANE_XHCI 0x3 +#define BL_FIA_LANE_PCIE_ROOT_PORT_LINK_WIDTH_SET_BY_BICTRL 0x0 +#define BL_FIA_LANE_PCIE_ROOT_PORT_LINK_WIDTH_X1 0x1 -typedef enum { - IioPortA = 0, - IioPortB = 1, - IioPortC = 2, - IioPortD = 3 -} IIO_PORTS; +typedef struct { + UINT8 FiaLaneConfig[BL_MAX_FIA_LANES]; + UINT8 FiaLaneLinkWidth[BL_MAX_FIA_LANES]; +} BL_HSIO_INFORMATION; /** - * Enums and Macro definitions needed for reference RVP and CRB - * table declarations -**/ -typedef enum { - Iio_Socket0 = 0, - Iio_Socket1, - Iio_Socket2, - Iio_Socket3, - Iio_Socket4, - Iio_Socket5, - Iio_Socket6, - Iio_Socket7 -} IIO_SOCKETS; + This structure holds the DLL configuration + register values that will be programmed by RC. + Those policies should be used by platform if default values + provided by RC are not sufficient to provide stable operation + at all supported speed modes. RC will blindly set the DLL values + as provided in this structure. -typedef enum { - Iio_Iou0 = 0, - Iio_Iou1, - Iio_Iou2, - Iio_Mcp0, - Iio_Mcp1, - Iio_IouMax -} IIO_IOUS; - -/** - IIO PCIe Ports - **/ -typedef enum { - PORT_0 = 0, - // IOU2 - PORT_1A, - PORT_1B, - PORT_1C, - PORT_1D, - // IOU0 - PORT_2A, - PORT_2B, - PORT_2C, - PORT_2D, - // IOU1 - PORT_3A, - PORT_3B, - PORT_3C, - PORT_3D, - // MCP0 - PORT_4A, - PORT_4B, - PORT_4C, - PORT_4D, - // MCP1 - PORT_5A, - PORT_5B, - PORT_5C, - PORT_5D, - MAX_PORTS -} PCIE_PORTS; - -/** - IIO Stacks - **/ -typedef enum { - CSTACK = 0, - PSTACK0, - PSTACK1, - PSTACK2, - PSTACK3, - PSTACK4, - MAX_STACKS -} IIO_STACKS; - -#define IioStack0 CSTACK -/* MAX_LOGIC_IIO_STACK is needed by uncore_acpi.c, define the same value from nb_acpi.c for - Skylake-SP to keep the same behavior. */ -#define MAX_LOGIC_IIO_STACK PSTACK2 - -/** - NTB Per Port Definition - **/ -typedef enum { - NTB_PORT_TRANSPARENT = 0, - NTB_PORT_NTB_NTB -} NTB_PPD; - -/** - NTB Upstream/Downstream Configuration - **/ -typedef enum { - NTB_XLINK_DSD_USP = 2, - NTB_XLINK_USD_DSP -} NTB_XLINK; - -/** - PCIe Link Speed Selection - **/ -typedef enum { - PcieAuto = 0, - PcieGen1, - PcieGen2, - PcieGen3 -} PCIE_LINK_SPEED; - -/** - GPIO Pad Number -**/ - -typedef UINT32 UPD_GPIO_PAD; - -/** - UPD_GPIO_CONFIG: - 64 bit struct defining GPIO PAD configuration + For help with obtaining valid DLL values for your platform please + contact enabling support. **/ typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig and Host Software Pad Ownership are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 4; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion Out, both In and Out, - both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 5; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting - is applicable only if GPIO is in input mode. - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 8; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 4; - - /** - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 7; - - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 3; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 2; - - UINT32 RsvdBits : 27; ///< Reserved bits for future extension - - UINT32 RsvdBits1; ///< Reserved bits for future extension -} UPD_GPIO_CONFIG; + UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control + UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control 1 + UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control 2 + UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay Control 1 + UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay Control 2 + UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Control, valid only for eMMC +} BL_SCS_SD_DLL; /** - UPD_GPIO_INIT_CONFIG: - Defines a GPIO Pad and its respective configuration - Constitutes one entry in the GPIO config table - Reference FSP implementation: - AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\GpioTable.c - Bootloaders can include the following to define GPIO PADs/other macros: - PurleySktPkg\SouthClusterLbg\Include\Library\GpioLib.h + Definition of FIA OVERRIDE STATUS HOB + Get/Set Status are defined by their respective Get/Set MeFiaMuxConfig functions called in PeiFiaMuxConfigInitLib. + + FIA MUX configuration is based on platform design and generally set by soft straps. + FIA MUX configuration can change the generic lane assignment through the FSP UPDs to increase flexibility. + FIA_OVERRIDE_STATUS_HOB allows the FSP to provide the required feedback + on the update of the FIA MUX configuration to the customer's bootloader. **/ typedef struct { - UPD_GPIO_PAD GpioPad; - UPD_GPIO_CONFIG GpioConfig; -} UPD_GPIO_INIT_CONFIG; + UINT32 FiaMuxConfigGetStatus; // Status returned by MeFiaMuxConfigGet (MeFiaMuxLib) + UINT32 FiaMuxConfigSetStatus; // Status returned by MeFiaMuxConfigSet (MeFiaMuxLib) + BOOLEAN FiaMuxConfigSetRequired; // Indicates that a set was required in the FIA lane assignment. + // FALSE = the requested config matched the existing one. + // TRUE = the requested config did not match the existing one. +} BL_FIA_OVERRIDE_STATUS_HOB; -/** - GPIOTABLE_CONFIG: - GpioTable - Base Address of the Gpio Table declared by the - bootloader. - Default: NULL - NumberofEntries - Number of Entries in the GPIO Table provided - Default: 0 - If GpioTable is Null or NumberofEntries is 0, then FSP will handle Gpio Pad - configuration using default GPIO_INIT_CONFIG tables -**/ + +// +// Data Types +// +#ifndef UINT64_STRUCT_T +#define UINT64_STRUCT_T +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} BL_UINT64_STRUCT; +#endif // UINT64_STRUCT_T + +/// +/// RC version number structure. +/// typedef struct { - UPD_GPIO_INIT_CONFIG *GpioTable; - UINT32 NumberOfEntries; -} GPIOTABLE_CONFIG; + UINT8 Major; + UINT8 Minor; + UINT8 Revision; + UINT16 BuildNumber; +} BL_RC_VERSION; -/** - UPD_IIO_BIFURCATION_DATA_ENTRY: - Defines IIO Bifurcation for IIO Units - Constitutes one entry in the IIO Bifurcation table, describing bifurcation entries as: - Socket | IOU | Bifurcation - Valid IouNumbers are from 0 to 4 - Reference FSP Implementation : - AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\IioBifurInit.c - Definitions for relevant bifurcation macros: - NumberCpRcPkg\Library\BaseMemoryCoreLib\Chip\Skx\Include\Iio\IioRegs.h -**/ +#define BL_MAX_CHA_MAP 4 +#define BL_MAX_FW_KTI_PORTS 3 +#define BL_MAX_SOCKET 1 +#define BL_NUMBER_PORTS_PER_SOCKET 5 +#define BL_TYPE_MAX_MMIO_BAR 11 +#define BL_MAX_IMC 1 +#define BL_MAX_CH 3 +#define BL_MAX_LOGIC_IIO_STACK 8 +#define BL_MAX_IIO_STACK 6 +#define BL_MaxIIO BL_MAX_SOCKET +#define BL_MC_MAX_NODE (BL_MAX_SOCKET * BL_MAX_IMC) + + typedef struct { - UINT8 Socket; - UINT8 IouNumber; - UINT8 Bifurcation; -} UPD_IIO_BIFURCATION_DATA_ENTRY; + UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + UINT8 PeerPort; // Port of the peer socket +}BL_QPI_PEER_DATA; -/** - IIOBIFURCATION_CONFIG: - IIoBifurcationTable - Base Address of the IIO Bifurcation table - declared by the bootloader - Default: NULL - NumberofEntries - Number of Entries in the IIO Bifurcation Table - Default: 0 - If IIoBifurcationTable is Null or NumberofEntries is 0, then FSP will handle IIO - bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables -**/ typedef struct { - UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; - UINT32 NumberOfEntries; -} IIOBIFURCATION_CONFIG; + UINT8 Valid; + UINT32 MmioBar[BL_TYPE_MAX_MMIO_BAR]; + UINT8 PcieSegment; + BL_UINT64_STRUCT SegMmcfgBase; + UINT16 stackPresentBitmap; + UINT16 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList[BL_MAX_CHA_MAP]; + UINT32 SocId; + BL_QPI_PEER_DATA PeerInfo[BL_MAX_FW_KTI_PORTS]; // QPI LEP info +} BL_QPI_CPU_DATA; -/** - VTD_CONFIG : - VT direct IO Configuration Support - VTdSupport - Enable/Disable VTd Support - CoherencySupport - Enable/Disable Coherency Support - ATS - Enable/Disable Address Translation Services - FSP Will Disable VTd by default -**/ typedef struct { - UINT8 VTdSupport; - UINT8 CoherencySupport; - UINT8 ATS; -} VTD_CONFIG; + UINT8 Valid; + UINT8 SocId; + BL_QPI_PEER_DATA PeerInfo[BL_MAX_SOCKET]; // QPI LEP info +} BL_QPI_IIO_DATA; -/** - UPD_PCIE_PORT_CONFIG - PCIe port configuration - PortIndex - Index of the port to be configured as defined by PCI_PORTS - HidePort - Hide the selected port - DeEmphasis - DeEmphasis of the selected PCIe port - PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set - DfxDnTxPreset - PCIe Downstream Tx Preset, valid values (0x00 - 0x09, - 0xFF is Auto, Auto sets 0x07) - DfxRxPreset - PCIe Downstream Rx Preset, valid values (0x00 - 0x06, 0xFF is Auto) - DfxUpTxPreset - PCIe Upstream Tx Preset, valid values (0x00 - 0x09, 0xFF is Auto) - Sris - Enable/Disable SRIS (0x00 - Disable, 0x01 - Enable) - PcieCommonClock - Configure port clocking. (0x00 - Distinct, 0x01 - Common) - MaxPayload - PCIe Max Payload Size on the port - NtbPpd - NTB port Configuration as defined in NTB_PPD - NtbSplitBar - 0: Use one 64, 1: Use two 32-bit split bars - NtbSBar01Prefetch - Configure Split BAR 0/1 as prefetchable - NtbXlinkCtlOverride - NTB Cross-link as defined in NTB_XLINK - NtbBarSizePBar4 - Set Prefetchable BAR 4 size for the primary NTB side in case - Split Bar is Enabled - NtbBarSizePBar5 - Set Prefetchable BAR 5 size for the primary NTB side in case - Split Bar is Enabled - FSP_WA: Till FSP fixes NtbBarSizeOverride, parameters below are MANDATORY!: - These BAR size registers are write once registers and will be programmed with 0 - if not passed as FSP is - hardcoding NtbBarSizeOverride to 0x01 for now. - Split BAR sizes would need to be programmed mandatorily as well in case split bars - are enabled. - NtbBarSizePBar23 - Set Prefetchable BAR 23 size for the primary NTB side - NtbBarSizePBar45 - Used to set bar 4 and 5 sizes in case Split Bar is Disabled - NtbBarSizeSBar23 - Set Prefetchable BAR 23 size for the secondary NTB side - NtbBarSizeSBar45 - Set Prefetchable BAR 45 size for the secondary NTB side in case - Split Bar is disabled -**/ typedef struct { - UINT32 PortIndex; - UINT8 HidePort; - UINT8 DeEmphasis; - UINT8 PortLinkSpeed; - UINT8 MaxPayload; - UINT8 DfxDnTxPreset; - UINT8 DfxRxPreset; - UINT8 DfxUpTxPreset; - UINT8 Sris; - UINT8 PcieCommonClock; - UINT8 NtbPpd; - UINT8 NtbSplitBar; - UINT8 NtbBarSizePBar23; - UINT8 NtbBarSizePBar4; - UINT8 NtbBarSizePBar5; - UINT8 NtbBarSizePBar45; - UINT8 NtbBarSizeSBar23; - UINT8 NtbBarSizeSBar4; - UINT8 NtbBarSizeSBar5; - UINT8 NtbBarSizeSBar45; - UINT8 NtbSBar01Prefetch; - UINT8 NtbXlinkCtlOverride; -} UPD_PCI_PORT_CONFIG; + UINT8 Device; + UINT8 Function; +} BL_IIO_PORT_INFO; -/** - PCIEPORT_CONFIG: - PciePortConfiguration - Pointer to an array of PCIe port configuration structures - as declared above - NumberOfEntries - Number of elements in the PciePortConfiguration Array -**/ typedef struct { - UPD_PCI_PORT_CONFIG *ConfigurationTable; + BL_IIO_PORT_INFO PortInfo[BL_NUMBER_PORTS_PER_SOCKET]; +} BL_IIO_DMI_PCIE_INFO; - UINT16 NumberOfEntries; -} IIOPCIPORT_CONFIG; +typedef struct _BL_STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map + UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map + UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map + UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map + UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices + UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices + UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices + UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices + UINT32 VtdBarAddress; + UINT32 Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack +} BL_STACK_RES; -/** - UPD_IIO_STACK_RESOURCE_CONFIG: - StackIndex - Index of the CPU IIO Stack to be configured as defined by IIO_STACKS - PciResourceIoBase - PciResourceIoLimit - PciResourceMem32Base - PciResourceMem32Limit - PciResourceMem64Base - PciResourceMem64Limit -**/ typedef struct { - UINT8 StackIndex; - UINT16 PciResourceIoBase; - UINT16 PciResourceIoLimit; - UINT32 PciResourceMem32Base; - UINT32 PciResourceMem32Limit; - UINT64 PciResourceMem64Base; - UINT64 PciResourceMem64Limit; -} UPD_IIO_STACK_RESOURCE_CONFIG; + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map + UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map + UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map + UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map + BL_STACK_RES StackRes[BL_MAX_LOGIC_IIO_STACK]; + UINT32 RcBaseAddress; + BL_IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} BL_IIO_RESOURCE_INSTANCE; -/** - IIORESOURCE_CONFIG: - ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array - NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array -**/ typedef struct { - UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; - UINT16 NumberOfEntries; -} IIORESOURCE_CONFIG; + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmio32Base; // Global Mmiol base + UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit + UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0] + UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0] + BL_QPI_CPU_DATA CpuQpiInfo[BL_MAX_SOCKET]; // QPI related info per CPU + BL_QPI_IIO_DATA IioQpiInfo[BL_MAX_SOCKET]; // QPI related info per IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + BL_IIO_RESOURCE_INSTANCE IIO_resource[BL_MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[BL_MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[BL_MAX_SOCKET]; + UINT8 VMDStackEnable[BL_MaxIIO][BL_MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + BL_UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; //5370389 + UINT32 UboxMmioSize; + UINT32 MaxAddressBits; +} BL_PLATFORM_DATA; -/** - UPD_PCH_PCIE_PORT: - PortIndex - PCH PCIe Port Index. - Valid Port Numbers are: 0 to 19. - Enable - Enable/Disable PCH PCIe port - PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set -**/ typedef struct { - UINT8 PortIndex; - UINT8 ForceEnable; - UINT8 PortLinkSpeed; -} UPD_PCH_PCIE_PORT; + UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode) + UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT) + UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC + UINT32 OutKtiPerLinkL1En[BL_MAX_SOCKET]; // output kti link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB + UINT32 ieRequestedSize; // Size of the memory range requested by IE FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + UINT16 tolmLimit; + UINT32 tohmLimit; + BL_RC_VERSION RcVersion; + BOOLEAN MsrTraceEnable; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD support + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[BL_MAX_SOCKET][BL_MAX_IMC]; + UINT16 LlcSizeReg; + UINT8 chEnabled[BL_MAX_SOCKET][BL_MAX_CH]; + UINT8 memNode[BL_MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 DfxRstCplBitsEn; +} BL_SYSTEM_STATUS; -/** - PCHPCIPORT_CONFIG: - PciPortConfig - Pointer to an array of PCH PCI Ports to be configured - RootPortFunctionSwapping - Disable root port swapping based on device - connection status - PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage - The value of this policy is in 1/10th percent units. - Valid spread range: 0-20. Auto: 0xFE (sets it to hardware default) - Completely Disable PCIe PLL SSC: 0xFF - A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% - NumberOfEntries - Number of entries in the PCH PCI Port configuration -**/ typedef struct { - UPD_PCH_PCIE_PORT *PciPortConfig; - UINT8 RootPortFunctionSwapping; - UINT8 PciePllSsc; - UINT16 NumberOfEntries; -} PCHPCIPORT_CONFIG; + BL_PLATFORM_DATA PlatformData; + BL_SYSTEM_STATUS SystemStatus; +} BL_IIO_UDS; + +//PCI MMIO and IO resource reconfiguration +typedef struct { + UINT16 IoBase; // Base of I/O range assigned to entity + UINT16 IoLimit; // Limit of I/O range assigned to entity + UINT32 LowMmioBase; // Base of low MMIO region for entity + UINT32 LowMmioLimit; // Limit of low MMIO region for entity + UINT64 HighMmioBase; // Base of high (64-bit) MMIO region for entity + UINT64 HighMmioLimit; // Limit of high (64-bit) MMIO region for entity +} BL_PCI_BASE_LIMITS; + +typedef struct { + BL_PCI_BASE_LIMITS StackLimits[BL_MAX_LOGIC_IIO_STACK]; // Base and Limit of all PCIe resources for each stack of the socket +} BL_SOCKET_PCI_BASE_LIMITS; + +typedef struct { + BL_SOCKET_PCI_BASE_LIMITS Socket[BL_MAX_SOCKET]; // Base and limit of all PCIe resources for each socket +} BL_SYSTEM_PCI_BASE_LIMITS; + +typedef struct { + UINT64 Key0[BL_MAX_SOCKET]; + UINT64 Key1[BL_MAX_SOCKET]; +} BL_TME_INIT_DATA; + /** FSP-M Configuration **/ typedef struct { -/** Offset 0x0040 - MRC Debug Print Level - Select the FSP MRC debug message print level. Options are a bitmask, so you can - combine options. BIT0:MIN DEBUG, BIT1:MAX DEBUG, BIT2:TRACE, BIT3:MEM TRAIN, BIT4:TEST, - BIT5:CPGC, BIT6:REG ACCESS +/** Offset 0x0040 - Enable BIOS SSA RMT + Enables/Disables SSA RMT. Please refer to the Integration guide for RMT details. + $EN_DIS **/ - UINT8 PcdFspMrcDebugPrintErrorLevel; + UINT8 PcdEnableBiosSsaRMT; -/** Offset 0x0041 - KTI Debug Print Level - Select the FSP KTI debug message print level. Options are a bitmask, so you can - combine options. BIT0:ERROR, BIT1:WARNING, BIT2:INFO0, BIT3:INFO1 +/** Offset 0x0041 - Enable BIOS SSA RMT on Fast Cold Boot + Enables/Disables SSA RMT on a Fast Cold Boot + $EN_DIS **/ - UINT8 PcdFspKtiDebugPrintErrorLevel; + UINT8 PcdEnableBiosSsaRMTonFCB; -/** Offset 0x0042 - HSUART Device - Select the PCI High Speed UART Device for Serial Port. - 0:HSUART0, 1:HSUART1, 2:HSUART2 +/** Offset 0x0042 - Enable RMT per Bit Margining + Enables/Disables Per Bit Margining + $EN_DIS **/ - UINT8 PcdHsuartDevice; + UINT8 PcdBiosSsaPerBitMargining; -/** Offset 0x0043 - Customer Revision - The Customer can set this revision string for their own purpose. +/** Offset 0x0043 - Enable SSA Tables Display + Enables/Disables displaying results as tables + $EN_DIS **/ - UINT8 PcdCustomerRevision[32]; + UINT8 PcdBiosSsaDisplayTables; -/** Offset 0x0063 - GpioConfig - GpioConfig Struct. Defaults: GpioTable:NULL, NumberOfEntries:0x00 +/** Offset 0x0044 - Enable SSA Plot Display + Enables/Disables the display of per bit results as plots + $EN_DIS **/ - GPIOTABLE_CONFIG GpioConfig; + UINT8 PcdBiosSsaPerDisplayPlots; -/** Offset 0x006B - IioBifurcationConfig - IioBifurcationConfig Table Struct. Defaults: IioBifurcationTable:NULL, - NumberOfEntries:0x00 +/** Offset 0x0045 - Loop count for rank test + Exponential loop count for a single rank test **/ - IIOBIFURCATION_CONFIG IioBifurcationConfig; + UINT8 PcdBiosSsaLoopCount; -/** Offset 0x0073 +/** Offset 0x0046 - Enable Backside Margining + Enables/Disables margin test on the register or buffer backside + $EN_DIS **/ - UINT8 UnusedUpdSpace0[16]; + UINT8 PcdBiosSsaBacksideMargining; -/** Offset 0x0083 - VTdConfig - VTdConfig Struct. Defaults: All values are set to 0. VTd Disabled. +/** Offset 0x0047 - Enable Early Read ID Margining + Enables/Disables PMem Early Read Id Test + $EN_DIS **/ - VTD_CONFIG VTdConfig; + UINT8 PcdBiosSsaEarlyReadIdMargining; - UINT8 reserved1[35]; - -/** Offset 0x00A9 - Board ID Number - Select the BoardId based on the target Platform. Default assumes an unknown board. +/** Offset 0x0048 - Enable Step Size Override + Enables/Disables overriding the default step sizes + $EN_DIS **/ - UINT8 BoardId; + UINT8 PcdBiosSsaStepSizeOverride; - UINT8 reserved2[24]; - -/** Offset 0x00C2 **/ - VOID *SetupStructPtr; - - UINT8 reserved3[20]; - -/** Offset 0x00DA - IioPciConfig - IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. +/** Offset 0x0049 - Step size RxDqs + Step size of RxDqs. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - IIOPCIPORT_CONFIG IioPciConfig; + UINT8 PcdBiosSsaRxDqs; -/** Offset 0x00E0 - PchPciConfig - PCH Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. +/** Offset 0x004A - Step size RxVrefs + Step size of RxVrefs. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - PCHPCIPORT_CONFIG PchPciConfig; + UINT8 PcdBiosSsaRxVref; -/** Offset 0x00E8 - IioResourceConfig - IIO Resource Struct. Defaults: All pointers are NULL. All values are set to zero. +/** Offset 0x004B - Step size TxDqs + Step size of TxDqs. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - IIORESOURCE_CONFIG IioResourceConfig; + UINT8 PcdBiosSsaTxDq; - UINT8 reserved4[3]; - -/** Offset 0x00F1 - DCI Enable - Enable / Disable DCI - $EN_DIS +/** Offset 0x004C - Step size TxVrefs + Step size of TxVrefs. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - UINT8 PchDciEn; + UINT8 PcdBiosSsaTxVref; -/** Offset 0x00F2 - IO Margining Tool (IOMT) Enable - Enable / Disable Io Margining Tool - $EN_DIS +/** Offset 0x004D - Step size CmdAll + Step size of CmdAll. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - UINT8 IomtEnable; + UINT8 PcdBiosSsaCmdAll; -/** Offset 0x00F3 - Hyper Threading (HT) disable - Disable Hyper threading. Disable: 0x01 | Enable: 0x00 | Default - HT enabled - $EN_DIS +/** Offset 0x004E - Step size CmdVref + Step size of CmdVref. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - UINT8 HyperThreadingDisable; + UINT8 PcdBiosSsaCmdVref; -/** Offset 0x00F4 +/** Offset 0x004F - Step size CtlAll + Step size of CtlAll. Auto:1. Supported values : 1,2,4,8. This option is valid only + if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - UINT8 UnusedUpdSpace1[236]; + UINT8 PcdBiosSsaCtlAll; -/** Offset 0x01E0 +/** Offset 0x0050 - Step size EridDelay + Step size of EridDelay. Auto:1. Supported values : 1,2,4,8. This option is valid + only if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 **/ - UINT8 ReservedMemoryInitUpd[16]; -} FSPM_CONFIG; + UINT8 PcdBiosSsaEridDelay; + +/** Offset 0x0051 - Step size EridVref + Step size of EridVref. Auto:1. Supported values : 1,2,4,8. This option is valid + only if 'Enable Step size override' is Enabled + 1:1, 2:2, 4:4, 8:8 +**/ + UINT8 PcdBiosSsaEridVref; + +/** Offset 0x0052 - Enable SSA RMT Debug Message + Enables the BSSA RMT debug messages + 2:Disable, 5:Enable +**/ + UINT8 PcdBiosSsaDebugMessages; + +/** Offset 0x0053 - TCC Enable + Enable or Disable Intel® Time Coordinated Compute (TCC) features + $EN_DIS +**/ + UINT8 PcdTccEnable; + +/** Offset 0x0054 +**/ + UINT8 UnusedUpdSpace0[12]; + +/** Offset 0x0060 - ECC Support + Enable/disable ECC Support. + $EN_DIS +**/ + UINT8 PcdEccSupport; + +/** Offset 0x0061 - Fast Boot + Enable/Disable Fast Boot. + 0:Disabled,1:Enabled +**/ + UINT8 PcdFastBoot; + +/** Offset 0x0062 - Memory Test + Enable/Disable Memory Test. + $EN_DIS +**/ + UINT8 PcdMemTest; + +/** Offset 0x0063 - Memory Turnaround Time Optimization + Enable/Disable Memory turnaround time optimization. + $EN_DIS +**/ + UINT8 PcdMemTurnaroundOpt; + +/** Offset 0x0064 - Memory Frequency + Set DDR Memory Frequency Limit + 0: AUTO, 13:2400, 15:2666, 17: 2933 +**/ + UINT8 PcdDdrFreq; + +/** Offset 0x0065 - Memory Command Timing + Select the desired memory controller command timing + 0:Auto, 1:1N, 2:2N, 3:3N +**/ + UINT8 PcdCommandTiming; + +/** Offset 0x0066 - Memory Custom Refresh Rate + Set Desired rate in 0.1x units of the standard 7.8 usec interval. The valid range + is 20 - 80(i.e. 2x to 8x) +**/ + UINT8 PcdCustomRefreshRate; + +/** Offset 0x0067 +**/ + UINT8 UnusedUpdSpace1[41]; + +/** Offset 0x0090 - HSUART Device + Select the PCI High Speed UART Device for Serial Port. + 0:HSUART0, 1:HSUART1, 2:HSUART2 +**/ + UINT8 PcdHsuartDevice; + +/** Offset 0x0091 - ME Heci Communication + Enable/Disable ME Heci Communication. + 0:Disabled,1:Enabled +**/ + UINT8 PcdHeciCommunication; + +/** Offset 0x0092 - Virtualization Technology for Directed I/O + Enable/Disable Virtualization Technology for Directed I/O. + $EN_DIS +**/ + UINT8 PcdVtdSupport; + +/** Offset 0x0093 - Enable USB3 Ports + Enable/Disable per USB3 Ports. One byte for each port, byte0 for port0, byte1 for + port1 and so on. +**/ + UINT32 PcdPchUsb3Port; + +/** Offset 0x0097 - Enable USB2 Ports + Enable/Disable per USB2 Ports. One byte for each port, byte0 for port0, byte1 for + port1 and so on. +**/ + UINT32 PcdPchUsb2Port; + +/** Offset 0x009B - Enable USB3 Port Over Current Configuration + Enable over current pin assignment per USB3 port. 0xFF mean skip over current pin. + One byte for each port, byte0 for port0, byte1 for port1 and so on +**/ + UINT32 PcdPchUsb3PortOc; + +/** Offset 0x009F - Enable USB2 Port Over Current Configuration + Enable over current pin assignment per USB2 port. 0xFF mean skip over current pin. + One byte for each port, byte0 for port0, byte1 for port1 and so on +**/ + UINT32 PcdPchUsb2PortOc; + +/** Offset 0x00A3 - USB2 Per Port HS Pre-emphasis Bias + USB2 Per Port HS Pre-emphasis Bias. 000b - 0mV, 001b - 11.25mV, 010b - 16.9mV, 011b + - 28.15mV, 100b - 28.15mV, 101b - 39.35mV, 110b - 45mV, 111b - 56.3mV. One byte + for each port. +**/ + UINT32 PcdUsb2PeTxiSet; + +/** Offset 0x00A7 - USB2 Per Port HS Transmitter Bias + USB2 Per Port HS Transmitter Bias. 000b - 0mV, 001b - 11.25mV, 010b - 16.9mV, 011b + - 28.15mV, 100b - 28.15mV, 101b - 39.35mV, 110b - 45mV, 111b - 56.3mV. One byte + for each port. +**/ + UINT32 PcdUsb2TxiSet; + +/** Offset 0x00AB - USB2 Per Port HS Transmitter Emphasis + USB2 Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT32 PcdUsb2PreDeEmp; + +/** Offset 0x00AF - USB2 Per Port Half Bit Pre-emphasis + USB2 Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT32 PcdUsb2PreEmpHalfBit; + +/** Offset 0x00B3 - IIO PCIe Port 1 Bifurcation + IIO PCI Express port bifurcation for selected slot(s). + 0xFF:Auto, 0:X4X4X4X4, 1:X4X4X8, 2:X8X4X4, 3:X8X8, 4:X16 +**/ + UINT8 PcdIIOPciePortBifurcation; + +/** Offset 0x00B4 - IIO PCIe R-Link DeEmphasis + Desired DeEmphasis level for IIO PCIe R-Link + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPcieRLinkDeEmphasis; + +/** Offset 0x00B5 - IIO PCIe Port 1A DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 1A + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort1ADeEmphasis; + +/** Offset 0x00B6 - IIO PCIe Port 1B DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 1B + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort1BDeEmphasis; + +/** Offset 0x00B7 - IIO PCIe Port 1C DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 1C + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort1CDeEmphasis; + +/** Offset 0x00B8 - IIO PCIe Port 1D DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 1D + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort1DDeEmphasis; + +/** Offset 0x00B9 - IIO PCIe R-Link Link Speed + Desired Link Speed for IIO PCIe R-Link + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3 +**/ + UINT8 PcdIIoPcieLinkSpeedRLink; + +/** Offset 0x00BA - IIO PCIe Port 1A Link Speed + Desired Link Speed for IIO PCIe Port 1A + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort1ALinkSpeed; + +/** Offset 0x00BB - IIO PCIe Port 1B Link Speed + Desired Link Speed for IIO PCIe Port 1B + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort1BLinkSpeed; + +/** Offset 0x00BC - IIO PCIe Port 1C Link Speed + Desired Link Speed for IIO PCIe Port 1C + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort1CLinkSpeed; + +/** Offset 0x00BD - IIO PCIe Port 1D Link Speed + Desired Link Speed for IIO PCIe Port 1D + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort1DLinkSpeed; + +/** Offset 0x00BE - IIO PCIe R-Link Aspm + Desired Active state power management settings for IIO PCIe R-Link + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPcieRLinkAspm; + +/** Offset 0x00BF - IIO PCIe Port 1A Aspm + Desired Active state power management settings for IIO PCIe Port 1A + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort1AAspm; + +/** Offset 0x00C0 - IIO PCIe Port 1B Aspm + Desired Active state power management settings for IIO PCIe Port 1B + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort1BAspm; + +/** Offset 0x00C1 - IIO PCIe Port 1C Aspm + Desired Active state power management settings for IIO PCIe Port 1C + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort1CAspm; + +/** Offset 0x00C2 - IIO PCIe Port 1D Aspm + Desired Active state power management settings for IIO PCIe Port 1D + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort1DAspm; + +/** Offset 0x00C3 - PCH PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0: Auto, 5:4x2, 6:1x4 2x2, 7:2x2 1x4, 8:2x4, 9:1x8 +**/ + UINT8 PcdBifurcationPcie0; + +/** Offset 0x00C4 - PCH PCIe Controller 2 Bifurcation + Configure PCI Express controller 2 bifurcation. + 0: Auto, 5:4x2, 6:1x4 2x2, 7:2x2 1x4, 8:2x4, 9:1x8 +**/ + UINT8 PcdBifurcationPcie2; + +/** Offset 0x00C5 - PCH PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0: Auto, 5:4x2, 6:1x4 2x2, 7:2x2 1x4, 8:2x4, 9:1x8 +**/ + UINT8 PcdBifurcationPcie1; + +/** Offset 0x00C6 - IIO PCIe Port 2 Bifurcation + IIO PCI Express port bifurcation for selected slot(s). This Option is valid only + for IVL HCC Platform. + 0xFF:Auto, 0:X4X4X4X4, 1:X4X4X8, 2:X8X4X4, 3:X8X8, 4:X16 +**/ + UINT8 PcdIIOPciePort2Bifurcation; + +/** Offset 0x00C7 - IIO PCIe Port 2A DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 2A This Option is valid only for IVL + HCC Platform. + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort2ADeEmphasis; + +/** Offset 0x00C8 - IIO PCIe Port 2B DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 2B This Option is valid only for IVL + HCC Platform. + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort2BDeEmphasis; + +/** Offset 0x00C9 - IIO PCIe Port 2C DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 2C This Option is valid only for IVL + HCC Platform. + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort2CDeEmphasis; + +/** Offset 0x00CA - IIO PCIe Port 2D DeEmphasis + Desired DeEmphasis level for IIO PCIe Port 2D This Option is valid only for IVL + HCC Platform. + 0:6dB, 1:3.5dB +**/ + UINT8 PcdIIoPciePort2DDeEmphasis; + +/** Offset 0x00CB - IIO PCIe Port 2A Link Speed + Desired Link Speed for IIO PCIe Port 2A This Option is valid only for IVL HCC Platform. + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort2ALinkSpeed; + +/** Offset 0x00CC - IIO PCIe Port 2B Link Speed + Desired Link Speed for IIO PCIe Port 2B This Option is valid only for IVL HCC Platform. + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort2BLinkSpeed; + +/** Offset 0x00CD - IIO PCIe Port 2C Link Speed + Desired Link Speed for IIO PCIe Port 2C This Option is valid only for IVL HCC Platform. + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort2CLinkSpeed; + +/** Offset 0x00CE - IIO PCIe Port 2D Link Speed + Desired Link Speed for IIO PCIe Port 2D This Option is valid only for IVL HCC Platform. + 0:Auto, 1:GEN1, 2:GEN2, 3:GEN3, 4:GEN4 +**/ + UINT8 PcdIIoPciePort2DLinkSpeed; + +/** Offset 0x00CF - IIO PCIe Port 2A Aspm + Desired Active state power management settings for IIO PCIe Port 2A This Option + is valid only for IVL HCC Platform. + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort2AAspm; + +/** Offset 0x00D0 - IIO PCIe Port 2B Aspm + Desired Active state power management settings for IIO PCIe Port 2B This Option + is valid only for IVL HCC Platform. + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort2BAspm; + +/** Offset 0x00D1 - IIO PCIe Port 2C Aspm + Desired Active state power management settings for IIO PCIe Port 2C This Option + is valid only for IVL HCC Platform. + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort2CAspm; + +/** Offset 0x00D2 - IIO PCIe Port 2D Aspm + Desired Active state power management settings for IIO PCIe Port 2D This Option + is valid only for IVL HCC Platform. + 0:Disabled,4:Auto +**/ + UINT8 PcdIIoPciePort2DAspm; + +/** Offset 0x00D3 - IIO PCIe Port 2A Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 2A This Option is valid only for IVL HCC Platform. + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort2AHPCapable; + +/** Offset 0x00D4 - IIO PCIe Port 2B Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 2B This Option is valid only for IVL HCC Platform. + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort2BHPCapable; + +/** Offset 0x00D5 - IIO PCIe Port 2C Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 2C This Option is valid only for IVL HCC Platform. + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort2CHPCapable; + +/** Offset 0x00D6 - IIO PCIe Port 2D Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 2D This Option is valid only for IVL HCC Platform. + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort2DHPCapable; + +/** Offset 0x00D7 - IIO PCIe Port 2A Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 2A This Option is valid + only for IVL HCC Platform. + $EN_DIS +**/ + UINT8 PcdIIoPciePort2AHPSurprise; + +/** Offset 0x00D8 - IIO PCIe Port 2B Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 2B This Option is valid + only for IVL HCC Platform. + $EN_DIS +**/ + UINT8 PcdIIoPciePort2BHPSurprise; + +/** Offset 0x00D9 - IIO PCIe Port 2C Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 2C This Option is valid + only for IVL HCC Platform. + $EN_DIS +**/ + UINT8 PcdIIoPciePort2CHPSurprise; + +/** Offset 0x00DA - IIO PCIe Port 2D Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 2D This Option is valid + only for IVL HCC Platform. + $EN_DIS +**/ + UINT8 PcdIIoPciePort2DHPSurprise; + +/** Offset 0x00DB - Warm Reset Elimination Enable + Warm Reset Elimination Enable or Disable. + $EN_DIS +**/ + UINT8 PcdDfxWarmResetEliminationEn; + +/** Offset 0x00DC - Clock Generator Address + Set SKU Clock generator address. Valid field should be set. Skip Clock Generator + should be set to Disable. +**/ + UINT8 PcdSkuClockGeneratorAddress; + +/** Offset 0x00DD - SSC Secondary Smbus use + Enable or Disable SSC Secondary Smbus use. Skip Clock Generator should be set to Disable. + $EN_DIS +**/ + UINT8 PcdSkuSSCSecondarySmbusUsed; + +/** Offset 0x00DE - Skip Clock Generator + Enable or Disable to skip clock generator configuration. + $EN_DIS +**/ + UINT8 PcdSkipClockGenerator; + +/** Offset 0x00DF - SSC Enable for Host + Enable Spread Spectrum Control for the Host(CPU) PCIe High-Speed Root Ports. Skip + Clock Generator should be set to Disable. + 0:Disable, 1:Enable SSC with 0.25 spread, 2:Enable SSC with 0.5 spread +**/ + UINT8 PcdEnableClockSpreadSpec; + +/** Offset 0x00E0 +**/ + UINT8 UnusedUpdSpace2[57]; + +/** Offset 0x0119 - PCI-E port Clock Gating + Enable / Disable PCI-E Clock Gating for each port First byte represents Clock gating + for port 1A,Second byte for port 2A... respectively for each PCI-E Port. Each byte + takes value 0x00(Disable)~0x01(Enable) +**/ + UINT8 PcdPciePortClkGateEnable[21]; + +/** Offset 0x012E - Power Performance Tuning + Options decides who Controls EPB. 0:In OS mode :IA32_ENERGY_PERF_BIAS is used (Option + 0 is valid only if PcdProcessorHWPMEnable is 0/1), 1:In BIOS mode:ENERGY_PERF_BIAS_CONFIG + is used, 2:In PECI mode: PCS53 is used. + 0:OS Controls EPB, 1:BIOS Controls EPB , 2:PECI Controls EPB +**/ + UINT8 PcdPwrPerfTuning; + +/** Offset 0x012F - ENERGY_PERF_BIAS_CFG mode + (Valid if Power Performance Tuning is set to 1:BIOS Controls EPB.) Use input from + ENERGY_PERF_BIAS_CONFIG mode selection. PERF/Balanced Perf/Balanced Power/Power + 0:Performance, 7:Balanced Performance, 8:Balanced Power ,15:Power +**/ + UINT8 PcdAltEngPerfBIAS; + +/** Offset 0x0130 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 PcdCustomerRevision[32]; + +/** Offset 0x0150 - Memory Thermal Throttling + Enable/disable Memory Thermal Throttling + 0:Disabled,2:Enabled +**/ + UINT8 PcdMemoryThermalThrottling; + +/** Offset 0x0151 - FSP Debug Print Level + Select the FSP debug print level. + 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG +**/ + UINT8 PcdFspDebugPrintErrorLevel; + +/** Offset 0x0152 +**/ + UINT8 PcdFiaMuxOverride; + +/** Offset 0x0153 +**/ + UINT8 FiaMuxCfgInvalidate; + +/** Offset 0x0154 - DCI Enable + Enable / Disable DCI . Refer to Integration guide + $EN_DIS +**/ + UINT8 PcdDciEn; + +/** Offset 0x0155 - USB DbC Enable Mode + USB Debug mode . Refer to Integration guide + 0:Disabled, 1:USB2, 2:USB3, 3:Both, 4:NoChange (default) +**/ + UINT8 PcdDciDbcMode; + +/** Offset 0x0156 - USB3 Type-C UFP2DFP Debug Support + USB3 UFP2DFP Debug support. Refer to Integration guide + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 PcdDciUsb3TypecUfpDbg; + +/** Offset 0x0157 - PCH Trace Hub Enable Mode + Select Host or Target for Trace Hub debugger tool. Refer to Integration guide. + 0:Disable, 1:Target debugger, 2:Host debugger +**/ + UINT8 PcdPchTraceHubMode; + +/** Offset 0x0158 - PCH TH Mem Buffer Size 0 + Select size of memory region 0 buffer. Refer to Integration guide. + 0:None/OS, 1:1 MB, 2:8 MB, 3:64 MB, 4:128 MB, 5:256 MB, 6:512 MB +**/ + UINT8 PcdPchTraceHubMemReg0Size; + +/** Offset 0x0159 - PCH TH Mem Buffer Size 1 + Select size of memory region 1 buffer. Refer to Integration guide + 0:None/OS, 1:1 MB, 2:8 MB, 3:64 MB, 4:128 MB, 5:256 MB, 6:512 MB +**/ + UINT8 PcdPchTraceHubMemReg1Size; + +/** Offset 0x015A +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x015B - IMR3 Enable + Enable/Disable IMR3 .Default is Disabled .Refer to Integration guide + $EN_DIS +**/ + UINT8 PcdEnableIMR3; + +/** Offset 0x015C - Processor X2APIC Enable + Enable / Disable Processor X2APIC. Refer to Integration guide + $EN_DIS +**/ + UINT8 PcdProcessorX2Apic; + +/** Offset 0x015D - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PcdHyperThreading; + +/** Offset 0x015E - PCIe Hot Plug Enable + Enable / Disable PCIe Hot Plug. + $EN_DIS +**/ + UINT8 PcdPcieHotPlugEnable; + +/** Offset 0x015F +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x0160 - IIO PCIe R-Link Hot Plug Capable + Hot Plug Capable for IIO PCIe R-Link + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPcieLinkHPCapable; + +/** Offset 0x0161 - IIO PCIe Port 1A Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 1A + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort1AHPCapable; + +/** Offset 0x0162 - IIO PCIe Port 1B Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 1B + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort1BHPCapable; + +/** Offset 0x0163 - IIO PCIe Port 1C Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 1C + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort1CHPCapable; + +/** Offset 0x0164 - IIO PCIe Port 1D Hot Plug Capable + Hot Plug Capable for IIO PCIe Port 1D + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcdIIoPciePort1DHPCapable; + +/** Offset 0x0165 - IIO PCIe R-Link Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe R-Link + $EN_DIS +**/ + UINT8 PcdIIoPcieLinkHPSurprise; + +/** Offset 0x0166 - IIO PCIe Port 1A Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 1A + $EN_DIS +**/ + UINT8 PcdIIoPciePort1AHPSurprise; + +/** Offset 0x0167 - IIO PCIe Port 1B Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 1B + $EN_DIS +**/ + UINT8 PcdIIoPciePort1BHPSurprise; + +/** Offset 0x0168 - IIO PCIe Port 1C Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 1C + $EN_DIS +**/ + UINT8 PcdIIoPciePort1CHPSurprise; + +/** Offset 0x0169 - IIO PCIe Port 1D Hot Plug Surprise + Enable / Disable Hot Plug Capable Surprise for IIO PCIe Port 1D + $EN_DIS +**/ + UINT8 PcdIIoPciePort1DHPSurprise; + +/** Offset 0x016A - Speed Step (P-states) + Enable / Disable EIST (P-States) + $EN_DIS +**/ + UINT8 PcdProcessorEistEnable; + +/** Offset 0x016B - Boot performance mode + Select Boot Performance State. EIST should be Enabled + 0:Max Performance, 1:Max Efficient, 2:Set by Intel Node Manager +**/ + UINT8 PcdBootPState; + +/** Offset 0x016C - Hardware P-States + Select Hardware P-State control + 0:Disable, 1:Native Mode, 2:Out of Band Mode, 3:Native Mode with No Legacy Support +**/ + UINT8 PcdProcessorHWPMEnable; + +/** Offset 0x016D - Hardware PM Interrupt + Enable / Disable Hardware PM Interrupt. Hardware P-States should be Native mode + $EN_DIS +**/ + UINT8 PcdProcessorHWPMInterrupt; + +/** Offset 0x016E - EPP Enable + Enable / Disable EPP. Hardware P-States should not be disabled + $EN_DIS +**/ + UINT8 PcdProcessorEPPEnable; + +/** Offset 0x016F - EPP profile + Select HWPM Profile (EPP). Hardware P-States should be OOB and EPP should be enabled + 0:Performance, 128:Balanced Performance, 192:Balanced Power, 255:Power +**/ + UINT8 PcdProcessorEppProfile; + +/** Offset 0x0170 - Package C State + Package C State limit + 0:C0/C1 state, 1:C2 state, 2:C6(non Retention) state, 255:Auto +**/ + UINT8 PcdPackageCState; + +/** Offset 0x0171 - Enhanced Halt State (C1E) + Enable / Disable Core C1E auto promotion Control + $EN_DIS +**/ + UINT8 PcdProcessorC1eEnable; + +/** Offset 0x0172 - C2C3TT + C2 to C3 Transition Timer. Default = 0, means [AUTO] +**/ + UINT8 PcdC2C3TT; + +/** Offset 0x0173 - CPU C3 report + Enable/Disable CPU C3(ACPI C2) report to OS + $EN_DIS +**/ + UINT8 PcdC3Enable; + +/** Offset 0x0174 - CPU C6 report + Enable/Disable CPU C6(ACPI C3) report to OS + 0:Disable, 1:Enable, 255:Auto +**/ + UINT8 PcdC6Enable; + +/** Offset 0x0175 - Enable Monitor MWAIT + Enable / Disable Monitor and MWAIT instructions + $EN_DIS +**/ + UINT8 PcdMonitorMWait; + +/** Offset 0x0176 - C State Latency Control VALID[0] + Enable / Disable validity of the Value field in this register + $EN_DIS +**/ + UINT8 PcdCStateLatencyCtrlValid0; + +/** Offset 0x0177 - C State Latency Control MULTIPLIER[0] + Indicates the unit of measurement that is defined for the Value field in this register. + Valid field should be set +**/ + UINT8 PcdCStateLatencyCtrlMultiplier0; + +/** Offset 0x0178 - C State Latency Control VALUE[0] + The Interrupt Response Time Limit is given in units defined in the Multiplier field + of this register. Valid field should be set +**/ + UINT16 PcdCStateLatencyCtrlValue0; + +/** Offset 0x017A - C State Latency Control VALID[1] + Enable / Disable validity of the Value field in this register + $EN_DIS +**/ + UINT8 PcdCStateLatencyCtrlValid1; + +/** Offset 0x017B - C State Latency Control MULTIPLIER[1] + Indicates the unit of measurement that is defined for the Value field in this register. + Valid field should be set +**/ + UINT8 PcdCStateLatencyCtrlMultiplier1; + +/** Offset 0x017C - C State Latency Control VALUE[1] + The Interrupt Response Time Limit is given in units defined in the Multiplier field + of this register. Valid field should be set +**/ + UINT16 PcdCStateLatencyCtrlValue1; + +/** Offset 0x017E - C State Latency Control VALID[2] + Enable / Disable validity of the Value field in this register + $EN_DIS +**/ + UINT8 PcdCStateLatencyCtrlValid2; + +/** Offset 0x017F - C State Latency Control MULTIPLIER[2] + Indicates the unit of measurement that is defined for the Value field in this register. + Valid field should be set +**/ + UINT8 PcdCStateLatencyCtrlMultiplier2; + +/** Offset 0x0180 - C State Latency Control VALUE[2] + The Interrupt Response Time Limit is given in units defined in the Multiplier field + of this register. Valid field should be set +**/ + UINT16 PcdCStateLatencyCtrlValue2; + +/** Offset 0x0182 - Config TDP Lock + Config TDP CONTROL Lock Bit. EIST should be enabled + $EN_DIS +**/ + UINT8 PcdConfigTdpLock; + +/** Offset 0x0183 - AVX P1 + AVX P1 level selection. EIST should be enabled + 0:Normal, 1:Level 1, 2:Level 2 +**/ + UINT8 PcdConfigTdpLevel; + +/** Offset 0x0184 - AVX Support + Enable/Disable AVX/2/3 instructions. Applicable to only certain SKUs - OC and HEDT + $EN_DIS +**/ + UINT8 PcdAvxSupport; + +/** Offset 0x0185 - AVX Licence Pre-Grant Override + Enables AVX ICCP pre-grant level override + $EN_DIS +**/ + UINT8 PcdAvxLicensePreGrant; + +/** Offset 0x0186 - AVX ICCP pre-grant level + Pre-grants an AVX level to the core. Base frequency is not updated. AVX Licence + Pre-Grant Override should be enabled + 1:128 Heavy, 2:256 Light, 3:256 Heavy, 4: 512 Light, 5: 512 Heavy +**/ + UINT8 PcdAvxIccpLevel; + +/** Offset 0x0187 - GPSS timer + P-state change hysteresis time window + 0:0 us, 5:50 us, 50:500 us +**/ + UINT8 PcdGpssTimer; + +/** Offset 0x0188 - Software Controlled T-States + Enable / Disable Software Controlled T-States + $EN_DIS +**/ + UINT8 PcdTStateEnable; + +/** Offset 0x0189 - PROCHOT Modes + When a processor thermal sensor trips, the PROCHOT# will be driven + 0:Output-only, 1:Disable, 2:Both Input and Output, 3:Input-only +**/ + UINT8 PcdEnableProcHot; + +/** Offset 0x018A - Thermal Monitor + Enable / Disable Thermal Monitor + $EN_DIS +**/ + UINT8 PcdEnableThermalMonitor; + +/** Offset 0x018B - AC Exception On Split Lock + Enable or Disable AC (Alignment Check) Exception On Split Lock + $EN_DIS +**/ + UINT8 PcdAcExceptionOnSplitLockEnable; + +/** Offset 0x018C - PCIe Allocating Write Flows + Select Vc0/VCp write selection for all CPU PCIe ports + 0x00:Non-Allocating, 0x01:Allocating +**/ + UINT8 PcdPcieAllocatingFlow; + +/** Offset 0x018D - IIO LLC Ways [19:0](Hex) + MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask +**/ + UINT32 PcdIioLlcWaysMask; + +/** Offset 0x0191 - Enable/ Disable VMD + Enable/Disable VMD in this Stack for socket0. First byte:Represents VMD config for + PCH port(Stack 0) Second Byte:Represents VMD config for IOU 0(Stack1) Each byte + takes value 0x00(Disable)~0x01(Enable) +**/ + UINT8 PcdVMDEnabled[2]; + +/** Offset 0x0193 - PCH Root Port + Configuration PCH root port:Enable-VMD ownership root port (Valid if PchRootPortIsAllowed + for respective port) First byte represents PCH Root Port 0,Second byte is PCH Root + Port 1,... PCH Root Port 11 respectively for each PCH Root Port. Each byte takes + value 0x00(Disable)~0x01(Enable) +**/ + UINT8 PcdVMDPchPortEnable[12]; + +/** Offset 0x019F - VMD port A + Enable/Disable Intel® Volume Management Device Technology on specific root port + $EN_DIS +**/ + UINT8 PcdVMDPortEnableA; + +/** Offset 0x01A0 +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x01A1 - VMD port B + Enable/Disable Intel® Volume Management Device Technology on specific root port + $EN_DIS +**/ + UINT8 PcdVMDPortEnableB; + +/** Offset 0x01A2 - VMD port C + Enable/Disable Intel® Volume Management Device Technology on specific root port + $EN_DIS +**/ + UINT8 PcdVMDPortEnableC; + +/** Offset 0x01A3 - VMD port D + Enable/Disable Intel® Volume Management Device Technology on specific root port + $EN_DIS +**/ + UINT8 PcdVMDPortEnableD; + +/** Offset 0x01A4 - Hot Plug Capable + Enable/Disable Hot Plug for PCIe Root Ports. First Byte:Represents VMD Hot plug + config for PCH port. Second Byte:Represents VMD Hot plug config for IOU 0 Each + byte takes value 0(Disable)~1(Enable) +**/ + UINT8 PcdVMDHotPlugEnable[2]; + +/** Offset 0x01A6 - CfgBar Size + Setup VMD Config BAR size (in bits Min=0x14, Max=0x1B), ex: 0x14(20 bits)=1MB, 0x1B(27bits)=128MB + First Byte:Represents VMD Config BAR size for PCH port. Second Byte:Represents + VMD Config BAR size for IOU 0. +**/ + UINT8 PcdVMDCfgBarSz[2]; + +/** Offset 0x01A8 - CfgBar attribute + Set up VMD Config BAR attribute, like 64-bit or prefetchable. First Byte:Represents + VMD Config BAR Attribute for PCH port. Second Byte:Represents VMD Config BAR Attribute + for IOU 0 Each Byte takes value of 0x0:(32-bit non-prefetchable),0x1:(64-bit non-prefetchable), + 0x2:(64-bit prefetchable) +**/ + UINT8 PcdVMDCfgBarAttr[2]; + +/** Offset 0x01AA - MemBar1 Size + Setup VMD Memory BAR1 size (in bits Min=0x14,max=0x27), ex: 0x14(20 bits)=1MB First + Byte:Represents VMD Memory BAR1 size for PCH port Second Byte:Represents VMD Memory + BAR1 size for IOU 0 +**/ + UINT8 PcdVMDMemBarSz1[2]; + +/** Offset 0x01AC - MemBar1 attribute + Set up VMD Memory BAR1 attribute, like 64-bit or prefetchable First Byte:Represents + VMD Memory BAR1 attribute for PCH port Second Byte:Represents VMD Memory BAR1 + attribute for IOU 0 Each Byte takes value of 0x0:(32-bit non-prefetchable),0x1:(64-bit + non-prefetchable), 0x2:(64-bit prefetchable) +**/ + UINT8 PcdVMDMemBar1Attr[2]; + +/** Offset 0x01AE - MemBar2 Size + Setup VMD Memory BAR2 size (in bits Min=0x14,max = 0x27), ex: 0x14(20bits)=1MB, + 0x16(22bits)=4MB. First Byte:Represents VMD Memory BAR2 size for PCH port. Second + Byte:Represents VMD Memory BAR2 size for IOU 0 +**/ + UINT8 PcdVMDMemBarSz2[2]; + +/** Offset 0x01B0 - MemBar2 attribute + Set up VMD Memory BAR2 attribute, like 64-bit or prefetchable. First Byte:Represents + VMD Memory BAR2 attribute for PCH port. Second Byte:Represents VMD Memory BAR2 + attribute for IOU 0 Each Byte takes value of 0x0:(32-bit non-prefetchable),0x1:(64-bit + non-prefetchable), 0x2:(64-bit prefetchable) +**/ + UINT8 PcdVMDMemBar2Attr[2]; + +/** Offset 0x01B2 - VMD for Direct Assign + Enable/ Disable VMD for Direct Assign if VMD is enabled First Byte:Represents VMD + for Direct Assign for PCH port Second Byte:Represents VMD for Direct Assign for + IOU 0 Each byte takes value 0x00(Disable)~0x01(Enable) +**/ + UINT8 PcdVMDDirectAssign[2]; + +/** Offset 0x01B4 - Power Limit 1 Enable + Enable/Disable Power Limit 1 + $EN_DIS +**/ + UINT8 PcdPowerLimit1Enable; + +/** Offset 0x01B5 - Power Limit 2 Enable + Enable/Disable Power Limit 2 + $EN_DIS +**/ + UINT8 PcdPowerLimit2Enable; + +/** Offset 0x01B6 - Turbo Mode + Enable/Disable Turbo Mode + $EN_DIS +**/ + UINT8 PcdTurboMode; + +/** Offset 0x01B7 - IIO PCIe Global ASPM + Enable/Disable PCIe ASPM on all IIO PCIe root ports + $EN_DIS +**/ + UINT8 PcdPcieGlobalAspm; + +/** Offset 0x01B8 - PCH Legacy IO Low Latency + Enable/Disable low latency of legacy IO. Increase power consumption for lower latency. + $EN_DIS +**/ + UINT8 PcdPchLegacyIoLowLatency; + +/** Offset 0x01B9 - PCH DMI ASPM + Enable/Disable L1 ASPM for Rlink + $EN_DIS +**/ + UINT8 PcdPchDmiAspm; + +/** Offset 0x01BA - DRAM RAPL + Enable/Disable DRAM Rapl + $EN_DIS +**/ + UINT8 PcdDramRaplEnable; + +/** Offset 0x01BB - PCH DMI ASPM + Enable/Disable CKE Throttling + $EN_DIS +**/ + UINT8 PcdCkeProgramming; + +/** Offset 0x01BC - PCH DMI ASPM + Enable/Disable APD + $EN_DIS +**/ + UINT8 PcdApdEnable; + +/** Offset 0x01BD - PCH DMI ASPM + Enable/Disable PPD + $EN_DIS +**/ + UINT8 PcdPpdEnable; + +/** Offset 0x01BE - Tcc Tuning enable/disable + Tcc (Time Coordinated Computing) Tuning Enabled + $EN_DIS +**/ + UINT8 PcdTccDsoTuningEn; + +/** Offset 0x01BF - Tcc Tuning enable/disable + Tcc (Time Coordinated Computing) Tuning Enabled + $EN_DIS +**/ + UINT8 PcdTccSoftwareSramEn; + +/** Offset 0x01C0 - Tcc Tuning enable/disable + Tcc (Time Coordinated Computing) Tuning Enabled + $EN_DIS +**/ + UINT8 PcdTccErrorLogEn; + +/** Offset 0x01C1 - Tcc BIOS Config File Base Address + Tcc (Time Coordinated Computing) TCC BIOS Config File Base Address +**/ + UINT32 PcdTccStreamCfgBasePreMem; + +/** Offset 0x01C5 - Tcc BIOS Config File Size + Tcc (Time Coordinated Computing) TCC BIOS Config File Size +**/ + UINT32 PcdTccStreamCfgSizePreMem; + +/** Offset 0x01C9 - Address of BL_TME_INIT_DATA table. + The address of the table of BL_TME_INIT_DATA. +**/ + UINT32 PcdTmePtr; + +/** Offset 0x01CD - Tme Enable + Enable or Disable TME + $EN_DIS +**/ + UINT8 PcdTmeEnable; + +/** Offset 0x01CE - MkTme Enable + Enable or Disable MKTME, Tme should be enabled before enabling MkTme. Cpu addressing + is restricted to 46 bit by default. With MKTME normal adressing will be followed + $EN_DIS +**/ + UINT8 PcdMkTmeEnable; + +/** Offset 0x01CF - IIO PCIe Multi VC Enable + Enable or Disable IIO PCIe Multi Virtual Channels + $EN_DIS +**/ + UINT8 PcdIioPcieMultiVcEnable; + +/** Offset 0x01D0 +**/ + UINT32 PcdIioResConfigPtr; + +/** Offset 0x01D4 +**/ + UINT32 PcdFiaLaneConfigPtr; + +/** Offset 0x01D8 +**/ + UINT32 PcdKtiBufferPtr; + +/** Offset 0x01DC +**/ + UINT32 PcdMemSpdPtr; + +/** Offset 0x01E0 - Protect memory Range size + Size of the PRMRR region +**/ + UINT64 PcdPrmrrSize; + +/** Offset 0x01E8 - SGX Enable + Enable or Disable Software Guard Extensions + $EN_DIS +**/ + UINT8 PcdSgxEnable; + +/** Offset 0x01E9 - SGX Auto registration + Enable or Disable SGX auto registration + $EN_DIS +**/ + UINT8 PcdSgxAutoRegistrationAgent; + +/** Offset 0x01EA - SGX Quality of Service + Enable or Disable SGX QoS to use LLC cache for EPC + $EN_DIS +**/ + UINT8 PcdSgxQoS; + +/** Offset 0x01EB - SGX Debug mode + Enable or Disable SGX Debug mode + $EN_DIS +**/ + UINT8 PcdSgxDebugMode; + +/** Offset 0x01EC - SGX Flexible Launch Control + Enable or Disable SGX Flexible Launch Control + $EN_DIS +**/ + UINT8 PcdSgxLeWr; + +/** Offset 0x01ED - SGX Flexible Launch Control public key Hash 0 + SGX flex launch control public key hash 0 +**/ + UINT64 PcdSgxLePubKeyHash0; + +/** Offset 0x01F5 - SGX Flexible Launch Control public key Hash 1 + SGX flex launch control public key hash 1 +**/ + UINT64 PcdSgxLePubKeyHash1; + +/** Offset 0x01FD - SGX Flexible Launch Control public key Hash 2 + SGX flex launch control public key hash 2 +**/ + UINT64 PcdSgxLePubKeyHash2; + +/** Offset 0x0205 - SGX Flexible Launch Control public key Hash 3 + SGX flex launch control public key hash 3 +**/ + UINT64 PcdSgxLePubKeyHash3; + +/** Offset 0x020D - PCI Express Root Port + Enable/Disable PcieRootPort from 1 to 12, each bit represent a port(bit0-bit11) + and last nibble is unusedFor example, bit0 0 controls PcieRootPortPort 1, bit1 + controls PcieRootPortPort 2... +**/ + UINT16 PcdPcieRootPortEn; + +/** Offset 0x020F - Enable spread spectrum + Enable/Disable spread spectrum. + 0:Disabled,1:Enabled +**/ + UINT8 PcdSpsIccClkSscSetting; + +/** Offset 0x0210 - PCH PCIE PLL Ssc + Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC + of 2.0%)(Default), Auto : 0xFE(Set to hardware default), Disable : 0xFF +**/ + UINT8 PchPciePllSsc; + +/** Offset 0x0211 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSP_M_CONFIG; /** Fsp M UPD Configuration **/ @@ -566,28 +1562,23 @@ /** Offset 0x0000 **/ - FSP_UPD_HEADER FspUpdHeader; + FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 **/ - FSPM_ARCH_UPD FspmArchUpd; + FSPM_ARCH_UPD FspmArchUpd; /** Offset 0x0040 **/ - FSP_M_CONFIG FspmConfig; + FSP_M_CONFIG FspmConfig; -/** Offset 0x01F0 - FspmVersion - FSP-M UPD Version Number +/** Offset 0x0221 **/ - UINT16 FspmUpdVersion; + UINT8 UnusedUpdSpace6[13]; -/** Offset 0x01F2 +/** Offset 0x022E **/ - UINT8 UnusedUpdSpace2[12]; - -/** Offset 0x01FE -**/ - UINT16 UpdTerminator; + UINT16 UpdTerminator; } FSPM_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h index b93a1af..a2020e1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2023, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -42,135 +42,663 @@ **/ typedef struct { -/** Offset 0x0020 - PCIe Controller 0 Bifurcation - Configure PCI Express controller 0 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +/** Offset 0x0020 **/ - UINT8 PcdBifurcationPcie0; + UINT32 PcdCpuMicrocodePatchBase; -/** Offset 0x0021 - PCIe Controller 1 Bifurcation - Configure PCI Express controller 1 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +/** Offset 0x0024 **/ - UINT8 PcdBifurcationPcie1; + UINT32 PcdCpuMicrocodePatchSize; -/** Offset 0x0022 - Active Core Count - Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) - 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, - 14:14, 15:15 +/** Offset 0x0028 - SATA Controllers + Enable/disable SATA Controller .Byte 0,1,2 is for SATA controller 0,1,2 respectively. + Byte4 is unused **/ - UINT8 PcdActiveCoreCount; + UINT32 PcdEnableSATA; -/** Offset 0x0023 +/** Offset 0x002C - SATA Mode + 0:AHCI, 1:RAID. Byte 0,1,2 is for SATA controller 0,1,2 respectively. Byte4 is + unused as only 3 SATA controllers present **/ - UINT32 PcdCpuMicrocodePatchBase; + UINT32 PcdSATAmode; -/** Offset 0x0027 +/** Offset 0x0030 - SATA Interrupt Mode + 0:Msix, 1:Msi, 2:Legacy . Byte 0,1,2 is for SATA controller 0,1,2 respectively. + Byte4 is unused as only 3 SATA controllers present **/ - UINT32 PcdCpuMicrocodePatchSize; + UINT32 PcdSATAInterruptMode; -/** Offset 0x002B - PCIe Controller 0 - Enable / Disable PCI Express controller 0 - $EN_DIS +/** Offset 0x0034 - SATA port Enable for Controller 0 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT8 PcdEnablePcie0; + UINT32 PcdSATA0PortEnable; -/** Offset 0x002C - PCIe Controller 1 - Enable / Disable PCI Express controller 1 - $EN_DIS +/** Offset 0x0038 - SATA port HotPlug capability for Controller 0 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT8 PcdEnablePcie1; + UINT32 PcdSATA0PortHotplug; -/** Offset 0x002D - Embedded Multi-Media Controller (eMMC) - Enable / Disable Embedded Multi-Media controller - $EN_DIS +/** Offset 0x003C - SATA port Enable for Controller 1 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT8 PcdEnableEmmc; + UINT32 PcdSATA1PortEnable; -/** Offset 0x002E - LAN Controllers - Enable / Disable LAN controllers, refer to FSP Integration Guide for details. - 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +/** Offset 0x0040 - SATA port HotPlug capability for Controller 1 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT8 PcdEnableGbE; + UINT32 PcdSATA1PortHotplug; -/** Offset 0x002F +/** Offset 0x0044 - SATA port Enable for Controller 2 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT32 PcdFiaMuxConfigRequestPtr; + UINT32 PcdSATA2PortEnable; -/** Offset 0x0033 +/** Offset 0x0048 - SATA port HotPlug capability for Controller 2 + 0:Disabled , 1: Enabled . Each one of 8 ports are represented by a nibble . for + example : nibble 0 controls port 0 , nibble 1 controls port 1 **/ - UINT8 UnusedUpdSpace0[4]; + UINT32 PcdSATA2PortHotplug; -/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x004C - EMMC controller + Enable/Disable EMMC controller. + $EN_DIS **/ - UINT8 PcdPcieRootPort0DeEmphasis; + UINT8 PcdEmmc; -/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x004D - EMMC HS400 Support + Enable/Disable EMMC HS400 Support. + $EN_DIS **/ - UINT8 PcdPcieRootPort1DeEmphasis; + UINT8 PcdEmmcHS400Support; -/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x004E - PCH PCIe Root Port 0 Link Speed + Desired Link Speed level for PCIe Root Port 0 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort2DeEmphasis; + UINT8 PcdPcieRootPort0LinkSpeed; -/** Offset 0x003A - PCIe Root Port 3 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x004F - PCH PCIe Root Port 1 Link Speed + Desired Link Speed level for PCIe Root Port 1 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort3DeEmphasis; + UINT8 PcdPcieRootPort1LinkSpeed; -/** Offset 0x003B - PCIe Root Port 4 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x0050 - PCH PCIe Root Port 2 Link Speed + Desired Link Speed level for PCIe Root Port 0 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort4DeEmphasis; + UINT8 PcdPcieRootPort2LinkSpeed; -/** Offset 0x003C - PCIe Root Port 5 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x0051 - PCH PCIe Root Port 3 Link Speed + Desired Link Speed level for PCIe Root Port 3 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort5DeEmphasis; + UINT8 PcdPcieRootPort3LinkSpeed; -/** Offset 0x003D - PCIe Root Port 6 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x0052 - PCH PCIe Root Port 4 Link Speed + Desired Link Speed level for PCIe Root Port 8 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort6DeEmphasis; + UINT8 PcdPcieRootPort4LinkSpeed; -/** Offset 0x003E - PCIe Root Port 7 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB +/** Offset 0x0053 - PCH PCIe Root Port 5 Link Speed + Desired Link Speed level for PCIe Root Port 8 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdPcieRootPort7DeEmphasis; + UINT8 PcdPcieRootPort5LinkSpeed; -/** Offset 0x003F +/** Offset 0x0054 - PCH PCIe Root Port 6 Link Speed + Desired Link Speed level for PCIe Root Port 8 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 UnusedUpdSpace1; + UINT8 PcdPcieRootPort6LinkSpeed; -/** Offset 0x0040 +/** Offset 0x0055 - PCH PCIe Root Port 7 Link Speed + Desired Link Speed level for PCIe Root Port 8 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT32 PcdEMMCDLLConfigPtr; + UINT8 PcdPcieRootPort7LinkSpeed; -/** Offset 0x0044 - Disable Monitor MWAIT - Enable / Disable the Monitor-MWAIT Instruction - $EN_DIS +/** Offset 0x0056 - PCH PCIe Root Port 8 Link Speed + Desired Link Speed level for PCIe Root Port 8 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 PcdDisableMonitorFSM; + UINT8 PcdPcieRootPort8LinkSpeed; -/** Offset 0x0045 +/** Offset 0x0057 - PCH PCIe Root Port 9 Link Speed + Desired Link Speed level for PCIe Root Port 9 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 UnusedUpdSpace2[155]; + UINT8 PcdPcieRootPort9LinkSpeed; -/** Offset 0x00E0 +/** Offset 0x0058 - PCH PCIe Root Port 10 Link Speed + Desired Link Speed level for PCIe Root Port 10 + 1:GEN1, 2:GEN2, 3:GEN3 **/ - UINT8 ReservedSiliconInitUpd[16]; -} FSPS_CONFIG; + UINT8 PcdPcieRootPort10LinkSpeed; + +/** Offset 0x0059 - PCH PCIe Root Port 11 Link Speed + Desired Link Speed level for PCIe Root Port 11 + 1:GEN1, 2:GEN2, 3:GEN3 +**/ + UINT8 PcdPcieRootPort11LinkSpeed; + +/** Offset 0x005A - PCH PCIe Root Port 0 Aspm + Desired Active state power management settings for PCIe Root Port 0 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort0Aspm; + +/** Offset 0x005B - PCH PCIe Root Port 1 Aspm + Desired Active state power management settings for PCIe Root Port 1 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort1Aspm; + +/** Offset 0x005C - PCH PCIe Root Port 2 Aspm + Desired Active state power management settings for PCIe Root Port 2 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort2Aspm; + +/** Offset 0x005D - PCH PCIe Root Port 3 Aspm + Desired Active state power management settings for PCIe Root Port 3 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort3Aspm; + +/** Offset 0x005E - PCH PCIe Root Port 4 Aspm + Desired Active state power management settings for PCIe Root Port 4 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort4Aspm; + +/** Offset 0x005F - PCH PCIe Root Port 5 Aspm + Desired Active state power management settings for PCIe Root Port 5 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort5Aspm; + +/** Offset 0x0060 - PCH PCIe Root Port 6 Aspm + Desired Active state power management settings for PCIe Root Port 6 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort6Aspm; + +/** Offset 0x0061 - PCH PCIe Root Port 7 Aspm + Desired Active state power management settings for PCIe Root Port 7 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort7Aspm; + +/** Offset 0x0062 - PCH PCIe Root Port 8 Aspm + Desired Active state power management settings for PCIe Root Port 8 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort8Aspm; + +/** Offset 0x0063 - PCH PCIe Root Port 9 Aspm + Desired Active state power management settings for PCIe Root Port 9 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort9Aspm; + +/** Offset 0x0064 - PCH PCIe Root Port 10 Aspm + Desired Active state power management settings for PCIe Root Port 10 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort10Aspm; + +/** Offset 0x0065 - PCH PCIe Root Port 11 Aspm + Desired Active state power management settings for PCIe Root Port 11 + 0:Disabled, 1:L0, 2:L1, 3:L0SL1 +**/ + UINT8 PcdPcieRootPort11Aspm; + +/** Offset 0x0066 - PCH PCIe Root Port 0 Connection Type + Set Connection Type for PCIe Root Port 0. PCIe Root Port 0 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort0ConnectionType; + +/** Offset 0x0067 - PCH PCIe Root Port 1 Connection Type + Set Connection Type for PCIe Root Port 1. PCIe Root Port 1 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort1ConnectionType; + +/** Offset 0x0068 - PCH PCIe Root Port 2 Connection Type + Set Connection Type for PCIe Root Port 2. PCIe Root Port 2 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort2ConnectionType; + +/** Offset 0x0069 - PCH PCIe Root Port 3 Connection Type + Set Connection Type for PCIe Root Port 3. PCIe Root Port 3 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort3ConnectionType; + +/** Offset 0x006A - PCH PCIe Root Port 8 Connection Type + Set Connection Type for PCIe Root Port 8. PCIe Root Port 8 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort8ConnectionType; + +/** Offset 0x006B - PCH PCIe Root Port 9 Connection Type + Set Connection Type for PCIe Root Port 9. PCIe Root Port 9 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort9ConnectionType; + +/** Offset 0x006C - PCH PCIe Root Port 10 Connection Type + Set Connection Type for PCIe Root Port 10. PCIe Root Port 10 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort10ConnectionType; + +/** Offset 0x006D - PCH PCIe Root Port 11 Connection Type + Set Connection Type for PCIe Root Port 11. PCIe Root Port 11 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort11ConnectionType; + +/** Offset 0x006E - PCH PCIe Root Port 0 HotPlug + Enable/Disable HotPlug for PCIe Root Port 0 + $EN_DIS +**/ + UINT8 PcdPcieRootPort0HotPlug; + +/** Offset 0x006F - PCH PCIe Root Port 1 HotPlug + Enable/Disable HotPlug for PCIe Root Port 1 + $EN_DIS +**/ + UINT8 PcdPcieRootPort1HotPlug; + +/** Offset 0x0070 - PCH PCIe Root Port 2 HotPlug + Enable/Disable HotPlug for PCIe Root Port 2 + $EN_DIS +**/ + UINT8 PcdPcieRootPort2HotPlug; + +/** Offset 0x0071 - PCH PCIe Root Port 3 HotPlug + Enable/Disable HotPlug for PCIe Root Port 3 + $EN_DIS +**/ + UINT8 PcdPcieRootPort3HotPlug; + +/** Offset 0x0072 - PCH PCIe Root Port 8 HotPlug + Enable/Disable HotPlug for PCIe Root Port 8 + $EN_DIS +**/ + UINT8 PcdPcieRootPort8HotPlug; + +/** Offset 0x0073 - PCH PCIe Root Port 9 HotPlug + Enable/Disable HotPlug for PCIe Root Port 9 + $EN_DIS +**/ + UINT8 PcdPcieRootPort9HotPlug; + +/** Offset 0x0074 - PCH PCIe Root Port 10 HotPlug + Enable/Disable HotPlug for PCIe Root Port 10 + $EN_DIS +**/ + UINT8 PcdPcieRootPort10HotPlug; + +/** Offset 0x0075 - PCH PCIe Root Port 11 HotPlug + Enable/Disable HotPlug for PCIe Root Port 11 + $EN_DIS +**/ + UINT8 PcdPcieRootPort11HotPlug; + +/** Offset 0x0076 - PCH PCIe Root Port 4 Connection Type + Set Connection Type for PCIe Root Port 4. PCIe Root Port 4 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort4ConnectionType; + +/** Offset 0x0077 - PCH PCIe Root Port 5 Connection Type + Set Connection Type for PCIe Root Port 5. PCIe Root Port 5 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort5ConnectionType; + +/** Offset 0x0078 - PCH PCIe Root Port 6 Connection Type + Set Connection Type for PCIe Root Port 6. PCIe Root Port 6 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort6ConnectionType; + +/** Offset 0x0079 - PCH PCIe Root Port 7 Connection Type + Set Connection Type for PCIe Root Port 7. PCIe Root Port 7 Hotplug enable forces + connection type to Slot. + 0:Built-In, 1:Slot +**/ + UINT8 PcdPcieRootPort7ConnectionType; + +/** Offset 0x007A - PCH PCIe Root Port 4 HotPlug + Enable/Disable HotPlug for PCIe Root Port 4 + $EN_DIS +**/ + UINT8 PcdPcieRootPort4HotPlug; + +/** Offset 0x007B - PCH PCIe Root Port 5 HotPlug + Enable/Disable HotPlug for PCIe Root Port 5 + $EN_DIS +**/ + UINT8 PcdPcieRootPort5HotPlug; + +/** Offset 0x007C - PCH PCIe Root Port 6 HotPlug + Enable/Disable HotPlug for PCIe Root Port 6 + $EN_DIS +**/ + UINT8 PcdPcieRootPort6HotPlug; + +/** Offset 0x007D - PCH PCIe Root Port 7 HotPlug + Enable/Disable HotPlug for PCIe Root Port 7 + $EN_DIS +**/ + UINT8 PcdPcieRootPort7HotPlug; + +/** Offset 0x007E - Bios WPD + Enable / Disable LockDown Bios WPD + $EN_DIS +**/ + UINT8 PcdLockDownBiosWpd; + +/** Offset 0x007F - Bios Interface + Enable / Disable LockDown Bios Interface + $EN_DIS +**/ + UINT8 PcdLockDownBiosInterface; + +/** Offset 0x0080 - Global Smi + Enable / Disable LockDown Global Smi + $EN_DIS +**/ + UINT8 PcdLockDownGlobalSmi; + +/** Offset 0x0081 - Bios Lock + Enable / Disable LockDown Bios Lock + $EN_DIS +**/ + UINT8 PcdLockDownBiosLock; + +/** Offset 0x0082 - SbAccessUnlock + Enable / Disable P2sbConfig SbAccessUnlock + $EN_DIS +**/ + UINT8 PcdSbAccessUnlock; + +/** Offset 0x0083 - PCH PCIe Root Port VppOverride + Each one of 12 PCH Port VppOverrides are represented by a nibble.For example, nibble + 0 controls PciePort 0, nibble 1 controls PciePort 1.A nibble takes value 0(Disable)~1(Enable). + The last 4 nibbles are unused. Nibble default value: 0x0 +**/ + UINT64 PcdPcieRootPortVppOverride; + +/** Offset 0x008B - PCH PCIe Root Port VppPort + Each one of 12 PCH VppPorts are represented by a nibble.For example, nibble 0 controls + VppPort 0, nibble 1 controls VppPort 1.A nibble takes value 0~1. The last 4 nibbles + are unused. Nibble default value: 0x0 +**/ + UINT64 PcdPcieRootPortVppPort; + +/** Offset 0x0093 - PCH PCIe Root Port VppAddress + Each one of 12 PCH VppAddresses are represented by a nibble.For example, nibble + 0 controls VppAddress 0, nibble 1 controls VppAddress 1.A nibble takes value 0~7. + The last 4 nibbles are unused. Nibble default value: 0x7 +**/ + UINT64 PcdPcieRootPortVppAddress; + +/** Offset 0x009B - PCH PCIe Root Port PTM Enable + Each one of 12 PCIe Port PTM Enable are represented by a nibble.For example, nibble + 0 controls PciePort 0, nibble 1 controls PciePort 1.A nibble takes value 0~1. The + last 4 nibbles are unused. Nibble default value: 0x1 +**/ + UINT64 PcdPcieRootPortPtmEnable; + +/** Offset 0x00A3 - PCH Flash Protection Ranges Write Enable + Write or erase is blocked by hardware. Each byte represents a WriteProtectionEnable + for respective Ranges. Total Protected ranges = 5 +**/ + UINT8 PcdWriteProtectionEnable[5]; + +/** Offset 0x00A8 - PCH Flash Protection Ranges Read Enable + Read is blocked by hardware. Each byte represents a ReadProtectionEnable for respective + Ranges. Total Protected ranges = 5 +**/ + UINT8 PcdReadProtectionEnable[5]; + +/** Offset 0x00AD - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison.Each two bytes represents a ProtectedRangeLimit for respective + Ranges. Total Protected ranges = 5 +**/ + UINT16 PcdProtectedRangeLimit[5]; + +/** Offset 0x00B7 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.Each + two bytes represents a ProtectedRangeBase for respective Ranges. Total Protected + ranges = 5 +**/ + UINT16 PcdProtectedRangeBase[5]; + +/** Offset 0x00C1 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 PcdDevIntConfigPtr; + +/** Offset 0x00C5 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 PcdNumOfDevIntConfig; + +/** Offset 0x00C6 - Interrupt config PxRcConfig + PxRcConfig can be confiured here. First byte is for PIRQA, second byte is for PIRQB, + and so on. +**/ + UINT64 PcdIntConfigPxRcConfig; + +/** Offset 0x00CE - Interrupt config GpioIrqRoute + GpioIrqRoute can be confiured here. Valid value should be set +**/ + UINT8 PcdIntConfigGpioIrqRoute; + +/** Offset 0x00CF - Interrupt config SciIrqSelect + SciIrqSelect can be confiured here. Valid value should be set +**/ + UINT8 PcdIntConfigSciIrqSelect; + +/** Offset 0x00D0 - PCH PCIe Root Port 0 L1 SubState + L1 Substates settings for PCIe Root Port 0 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort0L1SubStates; + +/** Offset 0x00D1 - PCH PCIe Root Port 1 L1 SubState + L1 Substates settings for PCIe Root Port 1 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort1L1SubStates; + +/** Offset 0x00D2 - PCH PCIe Root Port 2 L1 SubState + L1 Substates settings for PCIe Root Port 2 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort2L1SubStates; + +/** Offset 0x00D3 - PCH PCIe Root Port 3 L1 SubState + L1 Substates settings for PCIe Root Port 3 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort3L1SubStates; + +/** Offset 0x00D4 - PCH PCIe Root Port 4 L1 SubState + L1 Substates settings for PCIe Root Port 4 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort4L1SubStates; + +/** Offset 0x00D5 - PCH PCIe Root Port 5 L1 SubState + L1 Substates settings for PCIe Root Port 5 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort5L1SubStates; + +/** Offset 0x00D6 - PCH PCIe Root Port 6 L1 SubState + L1 Substates settings for PCIe Root Port 6 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort6L1SubStates; + +/** Offset 0x00D7 - PCH PCIe Root Port 7 L1 SubState + L1 Substates settings for PCIe Root Port 7 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort7L1SubStates; + +/** Offset 0x00D8 - PCH PCIe Root Port 8 L1 SubState + L1 Substates settings for PCIe Root Port 8 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort8L1SubStates; + +/** Offset 0x00D9 - PCH PCIe Root Port 9 L1 SubState + L1 Substates settings for PCIe Root Port 9 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort9L1SubStates; + +/** Offset 0x00DA - PCH PCIe Root Port 10 L1 SubState + L1 Substates settings for PCIe Root Port 10 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort10L1SubStates; + +/** Offset 0x00DB - PCH PCIe Root Port 11 L1 SubState + L1 Substates settings for PCIe Root Port 11 + 0:Disabled, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2 +**/ + UINT8 PcdPcieRootPort11L1SubStates; + +/** Offset 0x00DC - Tcc Cache Config File Base Address + Tcc (Time Coordinated Computing) Cache Config File Base Address +**/ + UINT32 PcdTccCacheCfgBase; + +/** Offset 0x00E0 - Tcc Cache Config File Size + Tcc (Time Coordinated Computing) Cache Config File Size +**/ + UINT32 PcdTccCacheCfgSize; + +/** Offset 0x00E4 - Tcc Stream Buffer Config File Base Address + Tcc (Time Coordinated Computing) Stream Buffer Config File Base Address +**/ + UINT32 PcdTccStreamCfgBase; + +/** Offset 0x00E8 - Tcc Stream Buffer Config File Size + Tcc (Time Coordinated Computing) Stream Buffer Config File Size +**/ + UINT32 PcdTccStreamCfgSize; + +/** Offset 0x00EC - Tcc CRL Binary File Base Address + Tcc (Time Coordinated Computing) CRL Binary File Base Address +**/ + UINT32 PcdTccCrlBinBase; + +/** Offset 0x00F0 - Tcc CRL Binary File Size + Tcc (Time Coordinated Computing) CRL Binary Config File Size +**/ + UINT32 PcdTccCrlBinSize; + +/** Offset 0x00F4 +**/ + UINT32 PcdEMMCDLLConfigPtr; + +/** Offset 0x00F8 +**/ + UINT32 PcdSgxRegistrationPackageInfoPtr; + +/** Offset 0x00FC +**/ + UINT32 PcdSgxRegistrationConfigPtr; + +/** Offset 0x0100 +**/ + UINT32 PcdSgxUefiFwKeyBlobsPtr; + +/** Offset 0x0104 +**/ + UINT32 PcdSgxRegistrationStatusPtr; + +/** Offset 0x0108 +**/ + UINT32 PcdSgxRegistrationResponsePtr; + +/** Offset 0x010C +**/ + UINT32 PcdSgxUefiFwRegistrationStatePtr; + +/** Offset 0x0110 +**/ + UINT8 PcdSgxRegistrationSoftwareGuardStatus; + +/** Offset 0x0111 +**/ + UINT8 PcdSgxLegacyRegistrationEpcBios; + +/** Offset 0x0112 +**/ + UINT8 PcdSgxLegacyRegistrationEpcSw; + +/** Offset 0x0113 +**/ + UINT32 PcdSecIpInterdepPrevHash; + +/** Offset 0x0117 +**/ + UINT32 PcdSgxRegistrationServerRequestPtr; + +/** Offset 0x011B - Rlink CG Enable + Enable / Disable Rlink Clock Gating + $EN_DIS +**/ + UINT8 PcdPchRlinkClockGating; + +/** Offset 0x011C - PCI Express Clock Gating + Enable / Disable PCI Express Clock Gating + $EN_DIS +**/ + UINT8 PcdPcieClockGatingEnabled; + +/** Offset 0x011D - IO-APIC 24-119 RTE + Enable/Disable IO APIC entries 24-119 + $EN_DIS +**/ + UINT8 PcdPchIoApic24119Entries; + +/** Offset 0x011E +**/ + UINT8 ReservedSiliconInitUpd[4]; +} FSP_S_CONFIG; /** Fsp S UPD Configuration **/ @@ -178,19 +706,19 @@ /** Offset 0x0000 **/ - FSP_UPD_HEADER FspUpdHeader; + FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 **/ - FSPS_CONFIG FspsConfig; + FSP_S_CONFIG FspsConfig; -/** Offset 0x00F0 +/** Offset 0x0122 **/ - UINT8 UnusedUpdSpace3[14]; + UINT8 UnusedUpdSpace0; -/** Offset 0x00FE +/** Offset 0x0123 **/ - UINT16 UpdTerminator; + UINT16 UpdTerminator; } FSPS_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h index 1568f2b..a267551 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2023, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,70 +37,55 @@ #pragma pack(1) + /** FSP-T Core UPD **/ typedef struct { /** Offset 0x0020 **/ - UINT32 MicrocodeRegionBase; + UINT32 MicrocodeRegionBase; /** Offset 0x0024 **/ - UINT32 MicrocodeRegionLength; + UINT32 MicrocodeRegionLength; /** Offset 0x0028 **/ - UINT32 CodeRegionBase; + UINT32 CodeRegionBase; /** Offset 0x002C **/ - UINT32 CodeRegionLength; + UINT32 CodeRegionLength; /** Offset 0x0030 **/ - UINT8 Reserved1[16]; + UINT8 Reserved1[16]; } FSPT_CORE_UPD; -/** FSP-T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Disable Port80 output in FSP-T - Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 - Output, refer to FSP Integration Guide for details - 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output -**/ - UINT8 FsptPort80RouteDisable; - -/** Offset 0x0041 -**/ - UINT8 ReservedTempRamInitUpd[31]; -} FSPT_CONFIG; - /** Fsp T UPD Configuration **/ typedef struct { /** Offset 0x0000 **/ - FSP_UPD_HEADER FspUpdHeader; + FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 **/ - FSPT_CORE_UPD FsptCoreUpd; + FSPT_CORE_UPD FsptCoreUpd; /** Offset 0x0040 **/ - FSPT_CONFIG FsptConfig; + UINT8 ReservedTempRamInitUpd[32]; /** Offset 0x0060 **/ - UINT8 UnusedUpdSpace0[30]; + UINT8 UnusedUpdSpace0[30]; /** Offset 0x007E **/ - UINT16 UpdTerminator; + UINT16 UpdTerminator; } FSPT_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h index 9183244..b2900f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h @@ -99,20 +99,22 @@ IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; } IIO_DMI_PCIE_INFO; -typedef struct _STACK_RES { - uint8_t Personality; - uint8_t BusBase; - uint8_t BusLimit; - uint16_t PciResourceIoBase; - uint16_t PciResourceIoLimit; - uint32_t IoApicBase; - uint32_t IoApicLimit; - uint32_t PciResourceMem32Base; - uint32_t PciResourceMem32Limit; - uint64_t PciResourceMem64Base; - uint64_t PciResourceMem64Limit; - uint32_t VtdBarAddress; -} STACK_RES; +// typedef struct _STACK_RES { +// uint8_t Personality; +// uint8_t BusBase; +// uint8_t BusLimit; +// uint16_t PciResourceIoBase; +// uint16_t PciResourceIoLimit; +// uint32_t IoApicBase; +// uint32_t IoApicLimit; +// uint32_t PciResourceMem32Base; +// uint32_t PciResourceMem32Limit; +// uint64_t PciResourceMem64Base; +// uint64_t PciResourceMem64Limit; +// uint32_t VtdBarAddress; +// } STACK_RES; + +#define STACK_RES BL_STACK_RES typedef struct { uint8_t Valid; @@ -232,11 +234,13 @@ uint8_t AepDimmPresent; } SYSTEM_STATUS; -typedef struct { - PLATFORM_DATA PlatformData; - SYSTEM_STATUS SystemStatus; - uint32_t OemValue; -} IIO_UDS; +// typedef struct { +// PLATFORM_DATA PlatformData; +// SYSTEM_STATUS SystemStatus; +// uint32_t OemValue; +// } IIO_UDS; + +#define IIO_UDS BL_IIO_UDS #pragma pack() void soc_display_iio_universal_data_hob(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/82074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468755a8ade4d5ad438c7b4798f8fe38c201cc14 Gerrit-Change-Number: 82074 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
by Daniel Peng (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81781?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module ...................................................................... mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module 1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module. 2.Describe the FW_CONFIG probe for the settings on glassway. - WIFI_SAR_0 for Intel Wi-Fi module AX211 BUG=336051631 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Signed-off-by: Daniel_Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/Makefile.mk M src/mainboard/google/brya/variants/glassway/overridetree.cb A src/mainboard/google/brya/variants/glassway/variant.c 4 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81781/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Gerrit-Change-Number: 81781 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
by Eric Lai (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81781?usp=email ) Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Gerrit-Change-Number: 81781 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 03:08:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Eric Lai (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Jian Tong. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82056?usp=email ) Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 03:07:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
by Daniel Peng (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81781?usp=email ) Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Gerrit-Change-Number: 81781 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Apr 2024 02:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
by Daniel Peng (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81781?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module ...................................................................... mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module 1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module. 2.Describe the FW_CONFIG probe for the settings on glassway. - WIFI_SAR_0 for Intel Wi-Fi module AX211 BUG=None BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Signed-off-by: Daniel_Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/Makefile.mk M src/mainboard/google/brya/variants/glassway/overridetree.cb A src/mainboard/google/brya/variants/glassway/variant.c 4 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81781/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Gerrit-Change-Number: 81781 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Kun Liu (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Eric Lai, Jian Tong. Kun Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82056?usp=email ) Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 02:18:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Jian Tong (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Eric Lai, Kun Liu. Hello Eric Lai, Kun Liu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82056?usp=email to look at the new patch set (#4). Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... mb/google/brox/var/lotso: Add fw_config field for storage Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82056/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Jian Tong (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Eric Lai, Kun Liu. Hello Eric Lai, Kun Liu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82056?usp=email to look at the new patch set (#3). Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... mb/google/brox/var/lotso: Add fw_config field for storage Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82056/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 3 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Jian Tong (Code Review) 23 Apr '24

23 Apr '24

Jian Tong has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82056?usp=email ) Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... mb/google/brox/var/lotso: Add fw_config field for storage Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82056/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add fw_config field for storage
by Jian Tong (Code Review) 23 Apr '24

23 Apr '24

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82056?usp=email ) Change subject: mb/google/brox/var/lotso: Add fw_config field for storage ...................................................................... mb/google/brox/var/lotso: Add fw_config field for storage Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82056/1 diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 4f2c04a..2c5923c 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field STORAGE 0 1 + option STORAGE_UNKNOWN 0 + option STORAGE_UFS 1 + option STORAGE_NVME 2 + end +end + chip soc/intel/alderlake device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/82056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Gerrit-Change-Number: 82056 Gerrit-PatchSet: 1 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/brya/var/pujjoga: Add GPIO table
by Leo Chou (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shou-Chieh Hsu, Subrata Banik. Leo Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82044?usp=email ) Change subject: mb/google/brya/var/pujjoga: Add GPIO table ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82044/comment/edad936c_4b4c8642 : PS1, Line 9: Fill GPIO table for pujjoga. > Please mention the source (schematics?). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Gerrit-Change-Number: 82044 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 01:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/pujjoga: Add GPIO table
by Leo Chou (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82044?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/var/pujjoga: Add GPIO table ...................................................................... mb/google/brya/var/pujjoga: Add GPIO table Follow GPIO table and schematics of 500E_GEN4S_ADL_N_MB_0418 to add Pujjoga GPIO setting BUG=b:336469694 TEST=emerge-nissa coreboot Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Signed-off-by: leo.chou <leo.chou(a)lcfc.corp-partner.google.com> --- A src/mainboard/google/brya/variants/pujjoga/Makefile.mk A src/mainboard/google/brya/variants/pujjoga/gpio_pujjoga.c 2 files changed, 119 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/82044/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Gerrit-Change-Number: 82044 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: util/ifdtool: Add support for checking GPR0 status
by Reka Norman (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: David Wu, Krishna P Bhat D, Reka Norman, Stefan Reinauer, Subrata Banik, Tyler Wang. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81928?usp=email ) Change subject: util/ifdtool: Add support for checking GPR0 status ...................................................................... Patch Set 11: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81928/comment/42388a6b_96ff6f3b : PS11, Line 34: Start address = 0x00004000 : End address = 0x00322fff I think this should print the actual range, not the enabled range, so these should be 0 (I also left a comment about this below). File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/81928/comment/6bc452b5_db947c0c : PS11, Line 1749: struct fpsba *fpsba, uint32_t gpr0_offset, These arguments are not necessary https://review.coreboot.org/c/coreboot/+/81928/comment/e0db5437_a0ce6d59 : PS11, Line 1753: enabled_gprd_reg.value = fpsba->pchstrp[gpr0_offset]; This is not necessary (and doesn't do anything since you overwrite all the fields below). https://review.coreboot.org/c/coreboot/+/81928/comment/cbaf29b1_3ae70d5d : PS11, Line 1786: union gprd enabled_gprd; : enabled_gprd = get_enabled_gprd(fpsba, gpr0_offset, image, size); : nit: combine onto one line https://review.coreboot.org/c/coreboot/+/81928/comment/8741ba4a_74497d98 : PS11, Line 1807: union gprd enabled_gprd; : enabled_gprd = get_enabled_gprd(fpsba, gpr0_offset, image, size); nit: combine onto one line https://review.coreboot.org/c/coreboot/+/81928/comment/59c611ec_186a2c65 : PS11, Line 1818: enabled_gprd This should be `fpsba->pchstrp[gpr0_offset]` (print the actual range, not the enabled range). -- To view, visit https://review.coreboot.org/c/coreboot/+/81928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7 Gerrit-Change-Number: 81928 Gerrit-PatchSet: 11 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 00:15:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/arm/include/arch/hlt.h: fix warnings & errors of for loop
by Integral (Code Review) 23 Apr '24

23 Apr '24

Integral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82073?usp=email ) Change subject: arch/arm/include/arch/hlt.h: fix warnings & errors of for loop ...................................................................... arch/arm/include/arch/hlt.h: fix warnings & errors of for loop Change-Id: Iae4830a927c8aaf366d49ddd2154f6a180078234 Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/include/arch/hlt.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82073/1 diff --git a/src/arch/arm/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h index 7229643..7bdae39 100644 --- a/src/arch/arm/include/arch/hlt.h +++ b/src/arch/arm/include/arch/hlt.h @@ -5,7 +5,8 @@ static __always_inline void hlt(void) { - for (;;) ; + for (;;) + ; } #endif /* ARCH_HLT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae4830a927c8aaf366d49ddd2154f6a180078234 Gerrit-Change-Number: 82073 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: arch/arm/eabi_compat.c: fix warnings of macros
by Integral (Code Review) 23 Apr '24

23 Apr '24

Integral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82072?usp=email ) Change subject: arch/arm/eabi_compat.c: fix warnings of macros ...................................................................... arch/arm/eabi_compat.c: fix warnings of macros Change-Id: I232f011ba0567af78c69eb8f73366b03d29c2839 Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/eabi_compat.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/82072/1 diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 849fc65..dde564b 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -5,7 +5,7 @@ #include <console/console.h> /* FIXME(dhendrix): prototypes added for assembler */ -int raise(int signum) __attribute__((used)); +int raise(int signum) __used; int raise(int signum) { printk(BIOS_CRIT, "%s: Signal # %d caught\n", __func__, signum); @@ -13,12 +13,12 @@ } /* Dummy function to avoid linker complaints */ -void __aeabi_unwind_cpp_pr0(void) __attribute__((used)); +void __aeabi_unwind_cpp_pr0(void) __used; void __aeabi_unwind_cpp_pr0(void) { } -void __aeabi_unwind_cpp_pr1(void) __attribute__((used)); +void __aeabi_unwind_cpp_pr1(void) __used; void __aeabi_unwind_cpp_pr1(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/82072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232f011ba0567af78c69eb8f73366b03d29c2839 Gerrit-Change-Number: 82072 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: arch/arm/armv7/exception.c: fix warnings of macros and functions
by Integral (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Julius Werner. Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82050?usp=email to look at the new patch set (#4). Change subject: arch/arm/armv7/exception.c: fix warnings of macros and functions ...................................................................... arch/arm/armv7/exception.c: fix warnings of macros and functions Use better alignment attribute macro and add missing identifier names for function definition arguments. Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/armv7/exception.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/82050/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Gerrit-Change-Number: 82050 Gerrit-PatchSet: 4 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/arm/armv7/exception.c: fix warnings and errors of macros and fun...
by Integral (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82050?usp=email to look at the new patch set (#3). Change subject: arch/arm/armv7/exception.c: fix warnings and errors of macros and functions ...................................................................... arch/arm/armv7/exception.c: fix warnings and errors of macros and functions Use better alignment attribute macro and add missing identifier names for function definition arguments. Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/armv7/exception.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/82050/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Gerrit-Change-Number: 82050 Gerrit-PatchSet: 3 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/arm/armv7/exception.c: Fix checkpatch warnings and errors
by Integral (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82050?usp=email to look at the new patch set (#2). Change subject: arch/arm/armv7/exception.c: Fix checkpatch warnings and errors ...................................................................... arch/arm/armv7/exception.c: Fix checkpatch warnings and errors Use better alignment attribute macro and add missing identifier names for function definition arguments. Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/armv7/exception.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/82050/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Gerrit-Change-Number: 82050 Gerrit-PatchSet: 2 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/arm/armv7/exception.c: Fix checkpatch warnings and errors
by Integral (Code Review) 23 Apr '24

23 Apr '24

Integral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82050?usp=email ) Change subject: arch/arm/armv7/exception.c: Fix checkpatch warnings and errors ...................................................................... arch/arm/armv7/exception.c: Fix checkpatch warnings and errors Use better alignment attribute macro, add missing identifier names for function definition arguments. Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Signed-off-by: Integral <integral(a)member.fsf.org> --- M src/arch/arm/armv7/exception.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/82050/1 diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 799ae02..3f53d15 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -5,16 +5,16 @@ #include <arch/exception.h> #include <console/console.h> -uint8_t exception_stack[0x100] __attribute__((aligned(8))); +uint8_t exception_stack[0x100] __aligned(8); extern void *exception_stack_end; -void exception_undefined_instruction(uint32_t *); -void exception_software_interrupt(uint32_t *); -void exception_prefetch_abort(uint32_t *); -void exception_data_abort(uint32_t *); -void exception_not_used(uint32_t *); -void exception_irq(uint32_t *); -void exception_fiq(uint32_t *); +void exception_undefined_instruction(uint32_t *regs); +void exception_software_interrupt(uint32_t *regs); +void exception_prefetch_abort(uint32_t *regs); +void exception_data_abort(uint32_t *regs); +void exception_not_used(uint32_t *regs); +void exception_irq(uint32_t *regs); +void exception_fiq(uint32_t *regs); static void dump_stack(uintptr_t addr, size_t bytes) { -- To view, visit https://review.coreboot.org/c/coreboot/+/82050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c Gerrit-Change-Number: 82050 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-MessageType: newchange

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[S] Change in libgfxinit[main]: gma connectors: Add `Pipe' parameter to Pre_/Post_Off procedures
by Angel Pons (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dinesh Gehlot, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/81524?usp=email ) Change subject: gma connectors: Add `Pipe' parameter to Pre_/Post_Off procedures ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81524?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I01dbf3cae3dfef2130fa10116f70f23238c7a48c Gerrit-Change-Number: 81524 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Tue, 23 Apr 2024 21:41:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in libgfxinit[main]: gma display_probing: Make new TGL ports available
by Angel Pons (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Nico Huber, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/81522?usp=email ) Change subject: gma display_probing: Make new TGL ports available ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File common/hw-gfx-gma-display_probing.ads: https://review.coreboot.org/c/libgfxinit/+/81522/comment/75c3c42a_80470240 : PS4, Line 26: USBC1_HDMI, USBC2_HDMI, USBC3_HDMI, USBC4_HDMI, USBC5_HDMI, USBC6_HDMI, > You mean the other file? That's inside an […] Yeah, what I mean is that I see DP ports being handled, but I don't see where HDMI is handled. Sorry if I'm talking moonshine, it's a bit late. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Gerrit-Change-Number: 81522 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 23 Apr 2024 21:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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