coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/lenovo: Remove blank lines before '}' and after '{'
by Nicholas Sudsgaard (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Alexander Couzens, Elyes Haouas. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81484?usp=email ) Change subject: mb/lenovo: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Regarding the gpio tables, as those are generated by `util/intelp2m`. It might be a good idea to change how the script … [View More]

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[XS] Change in coreboot[main]: mb/lenovo: Remove blank lines before '}' and after '{'
by Nicholas Sudsgaard (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Alexander Couzens, Elyes Haouas. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81484?usp=email ) Change subject: mb/lenovo: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81484?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

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[S] Change in coreboot[main]: soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dram
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81432?usp=email ) Change subject: soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dram ...................................................................... soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dram The memmap_early_dram struct is now only used inside the non-CAR memmap.c, so move the struct definition there. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de… [View More]> Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81432 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/include/amdblocks/memmap.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index e6db85a..396260f 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -10,6 +10,12 @@ #include <memrange.h> #include <types.h> +struct memmap_early_dram { + /* fixed size types, so the layout in CBMEM won't change for 32 vs. 64 bit stages */ + uint32_t base; + uint32_t size; +}; + void memmap_stash_early_dram_usage(void) { struct memmap_early_dram *e; diff --git a/src/soc/amd/common/block/include/amdblocks/memmap.h b/src/soc/amd/common/block/include/amdblocks/memmap.h index 258b8b7..e769df6 100644 --- a/src/soc/amd/common/block/include/amdblocks/memmap.h +++ b/src/soc/amd/common/block/include/amdblocks/memmap.h @@ -9,12 +9,6 @@ DECLARE_REGION(early_reserved_dram) -struct memmap_early_dram { - /* fixed size types, so the layout in CBMEM won't change for 32 vs. 64 bit stages */ - uint32_t base; - uint32_t size; -}; - void memmap_stash_early_dram_usage(void); /* report SoC memory map up to cbmem_top */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81432?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38 Gerrit-Change-Number: 81432 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[XS] Change in coreboot[main]: soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhere
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81391?usp=email ) Change subject: soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhere ...................................................................... soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhere Only the VGA MMIO range used the VGA_MMIO_* defines, but instead of using constants for the end of the region before that and the beginning of the region after that, the … [View More]VGA_MMIO_* defines can be used. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81391 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memmap.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 488c209..e6db85a 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -42,13 +42,13 @@ const uintptr_t early_reserved_dram_end = e->base + e->size; /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, VGA_MMIO_BASE); /* 0xa0000 - 0xbffff: legacy VGA */ mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, VGA_MMIO_BASE + VGA_MMIO_SIZE, 1 * MiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); -- To view, visit https://review.coreboot.org/c/coreboot/+/81391?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697 Gerrit-Change-Number: 81391 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[XS] Change in coreboot[main]: soc/amd/common/cpu/noncar/memmap: make local variables const
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81390?usp=email ) Change subject: soc/amd/common/cpu/noncar/memmap: make local variables const ...................................................................... soc/amd/common/cpu/noncar/memmap: make local variables const Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If3424df80655a150f27c7296a5683b528873816b Reviewed-on: https://review.coreboot.org/c/coreboot/+/81390 Tested-by: … [View More]build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memmap.c 1 file changed, 3 insertions(+), 6 deletions(-) Approvals: Marshall Dawson: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 2aaba83..488c209 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -36,13 +36,10 @@ /* report SoC memory map up to cbmem_top */ void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const uint32_t mem_usable = (uintptr_t)cbmem_top(); const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; + const uintptr_t early_reserved_dram_start = e->base; + const uintptr_t early_reserved_dram_end = e->base + e->size; /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); -- To view, visit https://review.coreboot.org/c/coreboot/+/81390?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3424df80655a150f27c7296a5683b528873816b Gerrit-Change-Number: 81390 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[M] Change in coreboot[main]: soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81389?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources ...................................................................... soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources Since the code for reporting the memory map … [View More]below cbmem_top is basically identical for all non-CAR AMD SoCs, factor this out into a common read_lower_soc_memmap_resources implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/cezanne/memmap.c M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/include/amdblocks/memmap.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/memmap.c M src/soc/amd/mendocino/memmap.c M src/soc/amd/phoenix/memmap.c M src/soc/amd/picasso/memmap.c 8 files changed, 46 insertions(+), 173 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c index 6c8e932..bb1eca2 100644 --- a/src/soc/amd/cezanne/memmap.c +++ b/src/soc/amd/cezanne/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index e21cff8a3..2aaba83 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -2,9 +2,11 @@ #include <amdblocks/memmap.h> #include <amdblocks/smm.h> +#include <arch/vga.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/smm.h> +#include <device/device.h> #include <memrange.h> #include <types.h> @@ -21,7 +23,7 @@ e->size = REGION_SIZE(early_reserved_dram); } -const struct memmap_early_dram *memmap_get_early_dram_usage(void) +static const struct memmap_early_dram *memmap_get_early_dram_usage(void) { struct memmap_early_dram *e = cbmem_find(CBMEM_ID_CB_EARLY_DRAM); @@ -31,6 +33,39 @@ return e; } +/* report SoC memory map up to cbmem_top */ +void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); +} + void smm_region(uintptr_t *start, size_t *size) { static int once; diff --git a/src/soc/amd/common/block/include/amdblocks/memmap.h b/src/soc/amd/common/block/include/amdblocks/memmap.h index cc89d86..258b8b7 100644 --- a/src/soc/amd/common/block/include/amdblocks/memmap.h +++ b/src/soc/amd/common/block/include/amdblocks/memmap.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_MEMMAP_H #define AMD_BLOCK_MEMMAP_H +#include <device/device.h> #include <stdint.h> #include <symbols.h> @@ -15,7 +16,9 @@ }; void memmap_stash_early_dram_usage(void); -const struct memmap_early_dram *memmap_get_early_dram_usage(void); + +/* report SoC memory map up to cbmem_top */ +void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx); void fsp_get_smm_region(uintptr_t *start, size_t *size); diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 6154908..88f386c 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -7,7 +7,6 @@ #include <amdblocks/root_complex.h> #include <amdblocks/smn.h> #include <arch/ioapic.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <types.h> @@ -18,28 +17,7 @@ void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { - ram_from_to(domain, (*idx)++, 0, 0xa0000); - mmio_from_to(domain, (*idx)++, 0xa0000, 0xc0000); // legacy VGA - reserved_ram_from_to(domain, (*idx)++, 0xc0000, 1 * MiB); // Option ROM - - uint32_t mem_usable = (uintptr_t)cbmem_top(); - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - // 1MB - bottom of DRAM reserved for early coreboot usage - ram_from_to(domain, (*idx)++, 1 * MiB, early_reserved_dram_start); - - // DRAM reserved for early coreboot usage - reserved_ram_from_to(domain, (*idx)++, early_reserved_dram_start, - early_reserved_dram_end); - - // top of DRAM consumed early - low top usable RAM - // cbmem_top() accounts for low UMA and TSEG if they are used. - ram_from_to(domain, (*idx)++, early_reserved_dram_end, - mem_usable); + read_lower_soc_memmap_resources(domain, idx); add_opensil_memmap(domain, idx); } diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c index d347bae..feecdd7 100644 --- a/src/soc/amd/glinda/memmap.c +++ b/src/soc/amd/glinda/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c index d347bae..feecdd7 100644 --- a/src/soc/amd/mendocino/memmap.c +++ b/src/soc/amd/mendocino/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c index e516572..9e740cb 100644 --- a/src/soc/amd/phoenix/memmap.c +++ b/src/soc/amd/phoenix/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> #include <vendorcode/amd/opensil/stub/opensil.h> @@ -63,34 +61,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 7ec7adf..2bbf285 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/memmap.h> #include <amdblocks/iomap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,32 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/81389?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 Gerrit-Change-Number: 81389 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[XS] Change in coreboot[main]: mb/google/cherry: Remove blank lines before '}' and after '{'
by Yidi Lin (Code Review) 23 Mar '24

23 Mar '24

Attention is currently required from: Elyes Haouas, Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81477?usp=email ) Change subject: mb/google/cherry: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81477?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

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[S] Change in coreboot[main]: soc/mediatek: Remove blank lines before '}' and after '{'
by Yidi Lin (Code Review) 23 Mar '24

23 Mar '24

Attention is currently required from: Elyes Haouas, Hung-Te Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81462?usp=email ) Change subject: soc/mediatek: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81462?usp=email To unsubscribe, or for help writing mail filters, … [View More]

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[S] Change in coreboot[main]: drivers/i2c/tas5825m: Allow using I2C bus
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81126?usp=email ) Change subject: drivers/i2c/tas5825m: Allow using I2C bus ...................................................................... drivers/i2c/tas5825m: Allow using I2C bus The latest Clevo boards connect the TAS5825M to one of the I2C connections instead of the SMBus connection. The I2C ops are compatible with SMBus, so always use them. Tested on system76/oryp6 (uses SMBus) and in-development … [View More]system76/oryp12 (uses I2C3). TAS5825M init is successful and speaker output works. Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/drivers/i2c/tas5825m/tas5825m.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c index 9f14059..ead1b16 100644 --- a/src/drivers/i2c/tas5825m/tas5825m.c +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -1,23 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/smbus.h> -#include <device/pci.h> +#include <device/i2c_bus.h> #include "chip.h" #include "tas5825m.h" int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) { - return smbus_write_byte(dev, addr, value); + return i2c_dev_writeb_at(dev, addr, value); } -//TODO: use I2C block write for better performance int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t *values, uint8_t length) { + // TODO: use I2C block write for better performance; SMBus does not + // have `transfer` op for it. + int res = 0; for (uint8_t i = 0; i < length; i++) { - res = smbus_write_byte(dev, addr + i, values[i]); + res = i2c_dev_writeb_at(dev, addr + i, values[i]); if (res < 0) return res; } @@ -45,8 +46,7 @@ static void tas5825m_init(struct device *dev) { - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && - ops_smbus_bus(get_pbus_smbus(dev))) { + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && i2c_link(dev)) { printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev)); struct drivers_i2c_tas5825m_config *config = dev->chip_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/81126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Gerrit-Change-Number: 81126 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
by Felix Held (Code Review) 23 Mar '24

23 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81370?usp=email ) Change subject: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder ...................................................................... soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST=intel/archercity CRB Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph <… [View More]patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/ebg/Makefile.mk R src/soc/intel/xeon_sp/ebg/include/soc/xhci.h R src/soc/intel/xeon_sp/ebg/soc_xhci.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h 5 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Jincheng Li: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk index ac73acb..b05c05b 100644 --- a/src/soc/intel/xeon_sp/ebg/Makefile.mk +++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk @@ -2,6 +2,6 @@ bootblock-y += soc_gpio.c soc_pch.c romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c -ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c +ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include diff --git a/src/soc/intel/xeon_sp/spr/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h similarity index 100% rename from src/soc/intel/xeon_sp/spr/include/soc/xhci.h rename to src/soc/intel/xeon_sp/ebg/include/soc/xhci.h diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c similarity index 92% rename from src/soc/intel/xeon_sp/spr/xhci.c rename to src/soc/intel/xeon_sp/ebg/soc_xhci.c index 544ea16..f8aa37b 100644 --- a/src/soc/intel/xeon_sp/spr/xhci.c +++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c @@ -2,10 +2,13 @@ #include <console/console.h> #include <device/pci.h> -#include <soc/pci_devs.h> +#include <soc/pch_pci_devs.h> #include <soc/xhci.h> #include <types.h> +// XHCI register +#define SYS_BUS_CFG2 0x44 + static uint8_t *get_xhci_bar(void) { const struct resource *res; diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 163b5ea..fc8ab17 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -12,7 +12,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 09953aa..510a67f 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -122,9 +122,6 @@ #define IIO_DFX_TSWCTL0 0x30c #define IIO_DFX_LCK_CTL 0x504 -// XHCI register -#define SYS_BUS_CFG2 0x44 - /* MSM registers */ #define MSM_BUS 0xF2 #define MSM_DEV 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81370?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Gerrit-Change-Number: 81370 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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