coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Subrata Banik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Garen Wu, Henry Sun, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 6 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 07:35:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: 3rdparty/amd_blobs: update submodule pointer
by Varshit Pandya (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Felix Held. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81263?usp=email ) Change subject: 3rdparty/amd_blobs: update submodule pointer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1bd0b37bebcdd600465dbd48162792e2c32bfb7 Gerrit-Change-Number: 81263 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Mar 2024 07:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Garen Wu (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Derek Huang, Eric Lai, Henry Sun, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh, Subrata Banik. Garen Wu has uploaded a new patch set (#6) to the change originally created by Rasheed Hsueh. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Henry Sun, Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik Change subject: mb/google/brya: Create yavista variant ...................................................................... mb/google/brya: Create yavista variant Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA. Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Signed-off-by: Hsueh Rasheed <hsueh.rasheed(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/yavista/include/variant/ec.h A src/mainboard/google/brya/variants/yavista/include/variant/gpio.h A src/mainboard/google/brya/variants/yavista/memory/Makefile.mk A src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/yavista/overridetree.cb 8 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/80342/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 6 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: mb/intel/mtlrvp: Add Intel Touch driver for controller 0 and 1
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81335?usp=email ) Change subject: mb/intel/mtlrvp: Add Intel Touch driver for controller 0 and 1 ...................................................................... mb/intel/mtlrvp: Add Intel Touch driver for controller 0 and 1 NOTE: Rework is required for both THC0 and THC1. NOTE: The resistor on the THC-SPI MISO pin should be 100 Ohm. BUG=b:307775082 TEST=set CBI THC0_TOUCH or THC1_TOUCH fw_config to WACOM or ELAN. Boot RVP to OS and run lspci to check THC device and check that THC device driver initialization successfully. /sys/class/hidraw/hidraw0/device/input/ should have several inputs enumerated. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I5433693973a21e90886c9075a23aaac84b2f642d --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.mk M src/mainboard/intel/mtlrvp/fw_config.c M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 5 files changed, 258 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81335/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 36842b5..5b951ab 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -48,6 +48,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI + select SOC_INTEL_TOUCH if BOARD_INTEL_MTLRVP_COMMON diff --git a/src/mainboard/intel/mtlrvp/Makefile.mk b/src/mainboard/intel/mtlrvp/Makefile.mk index d8144c8..103e336 100644 --- a/src/mainboard/intel/mtlrvp/Makefile.mk +++ b/src/mainboard/intel/mtlrvp/Makefile.mk @@ -8,6 +8,7 @@ ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-y += fw_config.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/mtlrvp/fw_config.c b/src/mainboard/intel/mtlrvp/fw_config.c index d874228..a3ea58a 100644 --- a/src/mainboard/intel/mtlrvp/fw_config.c +++ b/src/mainboard/intel/mtlrvp/fw_config.c @@ -4,6 +4,18 @@ #include <gpio.h> #include <inttypes.h> +#if CONFIG(SOC_INTEL_TOUCH) +#include <soc/pci_devs.h> +#include <drivers/intel/touch/chip.h> +const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx); +WEAK_DEV_PTR(touch_0_wacom); +WEAK_DEV_PTR(touch_0_elan); +WEAK_DEV_PTR(touch_0_generic); +WEAK_DEV_PTR(touch_1_wacom); +WEAK_DEV_PTR(touch_1_elan); +WEAK_DEV_PTR(touch_1_generic); +#endif + static const struct pad_config i2s_enable_pads[] = { /* Audio: I2S */ PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), /* I2S_MCLK1_OUT */ @@ -99,3 +111,49 @@ } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); + +#if CONFIG(SOC_INTEL_TOUCH) +const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx) +{ + const struct drivers_intel_touch_config *touch_config = NULL; + + if (ctl_idx == 0) { + if (is_devfn_enabled(PCI_DEVFN_THC0)) { + printk(BIOS_DEBUG, "THC%d device function is enabled\n", ctl_idx); + } + } else if (ctl_idx == 1) { + if (is_devfn_enabled(PCI_DEVFN_THC1)) { + printk(BIOS_DEBUG, "THC%d device function is enabled\n", ctl_idx); + } + } else { + printk(BIOS_ERR, "Invalid index for THC%d\n", ctl_idx); + return NULL; + } + if (ctl_idx == 0) { + if (fw_config_probe(FW_CONFIG(THC0_TOUCH, WACOM))) { + printk(BIOS_DEBUG, "THC%d uses WACOM sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_0_wacom)); + } else if (fw_config_probe(FW_CONFIG(THC0_TOUCH, ELAN))) { + printk(BIOS_DEBUG, "THC%d uses ELAN sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_0_elan)); + } else if (fw_config_probe(FW_CONFIG(THC0_TOUCH, GENERIC))) { + printk(BIOS_DEBUG, "THC%d uses generic sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_0_generic)); + } + } else if (ctl_idx == 1) { + if (fw_config_probe(FW_CONFIG(THC1_TOUCH, WACOM))) { + printk(BIOS_DEBUG, "THC%d uses WACOM sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_1_wacom)); + } else if (fw_config_probe(FW_CONFIG(THC1_TOUCH, ELAN))) { + printk(BIOS_DEBUG, "THC%d uses ELAN sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_1_elan)); + } else if (fw_config_probe(FW_CONFIG(THC1_TOUCH, GENERIC))) { + printk(BIOS_DEBUG, "THC%d uses generic sensor\n", ctl_idx); + touch_config = config_of(DEV_PTR(touch_1_generic)); + } + } + return touch_config; +} +#endif + + diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c index 2c48a0e..02414b6 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c @@ -180,6 +180,8 @@ PAD_CFG_NF(GPP_E05, NONE, DEEP, NF1), /* GPP_E6: THC0_SPI1_RST_N_TCH_PNL1 */ PAD_CFG_NF(GPP_E06, NONE, DEEP, NF2), + /* GPP_E6: THC0_SPI1_RST_N_TCH_PNL1 NOTE: use GPO instead for reset pin */ + PAD_CFG_GPO(GPP_E06, 1, DEEP), /* GPP_E8: CRD_PRIVACY_LED */ PAD_CFG_GPO(GPP_E08, 1, DEEP), /* GPP_E9: USB_CONN_TYPEA_12_TYPEC_01_FP_P7_P8_P9_P10_OC0_N */ @@ -225,12 +227,20 @@ /* GPP_F9: CODEC_INT_N */ PAD_CFG_GPI_APIC(GPP_F09, NONE, DEEP, LEVEL, INVERT), /* TPM: GPP_F11:GPP_F13, GPP_F17 */ + /* EH33 GPP_F11/THC1_SPI2_CLK/ISH_SPIATi_CLK/GSPI1_CLK/USB-C_GPP_F11 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF3), + /* EF36 GPP_F12/GSXDOUT/THC1_SPI2_IO0/ISH_SPIA_MISO/GSPI1_MOSI/I2C5_SCL/USB-C_GPP_F12 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF3), + /* ER33 GPP_F13/GSXSLOAD/THC1_SPI2_IO1/ISH_SPIA_MOSI/GSPI1_MISO/I2C5_SDA/USB-C_GPP_F13 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF3), /* GPP_F14: THC1_SPI2_IO_2_TCH_PNL2 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), /* GPP_F15: THC1_SPI2_IO_3_TCH_PNL2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF3), - /* GPP_F16: THC1_SPI2_RST_N_TCH_PNL2 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3), + /* GPP_F16: THC1_SPI2_RST_N_TCH_PNL2 NOTE: use GPO instead for reset pin */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* EC33 GPP_F17/THC1_SPI2_CS#/ISH_SPIA_CS#/GSPI1_CS0#/USB-C_GPP_F17 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), /* GPP_F18: THC1_SPI2_INT_N_TCH_PNL2 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), /* GPP_F19: X4_PCIE_SLOT2_WAKE_N_R */ diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb index 3f1579e..8adbb4f 100644 --- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -1,5 +1,23 @@ +fw_config + field THC0_TOUCH 12 13 + option NONE 0 + option WACOM 1 + option ELAN 2 + option GENERIC 3 + end + field THC1_TOUCH 14 15 + option NONE 0 + option WACOM 1 + option ELAN 2 + option GENERIC 3 + end +end + chip soc/intel/meteorlake + # THC configuration + register "thc_configuration" = "THC_CONFIG_DOUBLE_CONTROLLER" + device domain 0 on device ref soc_espi on chip ec/google/chromeec @@ -36,5 +54,173 @@ end end end + # NOTE: thc0 & thc1 setting need to match with SOC "thc_configuration". + # device ref thc0 alias thc0_dev on + device ref thc0 on + probe THC0_TOUCH WACOM + probe THC0_TOUCH ELAN + probe THC0_TOUCH GENERIC + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F23)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC0)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + register "sensor_dev_name" = "WACOM_DEV_NAME" + register "connected_device" = "TH_SENSOR_WACOM" + device generic 0 alias touch_0_wacom on + probe THC0_TOUCH WACOM + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F23)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC0)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + register "sensor_dev_name" = "ELAN_DEV_NAME" + register "connected_device" = "TH_SENSOR_ELAN" + device generic 0 alias touch_0_elan on + probe THC0_TOUCH ELAN + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F23)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC0)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E06)" + register "sensor_dev_name" = ""Generic Sensor"" + register "connected_device" = "TH_SENSOR_GENERIC" + register "hidspi_connection_speed" = "17000000" + register "active_ltr" = "0xFFFFFFFF" + register "idle_ltr" = "0xFFFFFFFF" + register "hidspi_input_report_header_address" = "0" + register "hidspi_input_report_body_address" = "0x1000" + register "hidspi_output_report_address" = "0x1000" + register "hidspi_read_opcode" = "0xb" + register "hidspi_write_opcode" = "0xb" + register "hidspi_limit_packet_size" = "1" + register "perform_limit" = "0" + register "reset_sequencing_delay" = "12" + device generic 0 alias touch_0_generic on + probe THC0_TOUCH GENERIC + end + end + end + # secondary non-I2C THC sensor device + device ref thc1 on + probe THC1_TOUCH WACOM + probe THC1_TOUCH ELAN + probe THC1_TOUCH GENERIC + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F22)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC1)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "sensor_dev_name" = "WACOM_DEV_NAME" + register "connected_device" = "TH_SENSOR_WACOM" + device generic 0 alias touch_1_wacom on + probe THC1_TOUCH WACOM + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F22)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC1)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "sensor_dev_name" = "ELAN_DEV_NAME" + register "connected_device" = "TH_SENSOR_ELAN" + device generic 0 alias touch_1_elan on + probe THC1_TOUCH ELAN + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F22)" + # register "enable_delay_ms" = "10" + # register "enable_off_delay_ms" = "2" + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + # register "reset_delay_ms" = "20" + # register "reset_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC1)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "sensor_dev_name" = ""Generic Sensor"" + register "connected_device" = "TH_SENSOR_GENERIC" + register "hidspi_connection_speed" = "17000000" + register "active_ltr" = "0xFFFFFFFF" + register "idle_ltr" = "0xFFFFFFFF" + register "hidspi_input_report_header_address" = "0" + register "hidspi_input_report_body_address" = "0x1000" + register "hidspi_output_report_address" = "0x1000" + register "hidspi_read_opcode" = "0xb" + register "hidspi_write_opcode" = "0x1" + register "hidspi_limit_packet_size" = "1" + register "perform_limit" = "0" + register "reset_sequencing_delay" = "12" + device generic 0 alias touch_1_generic on + probe THC1_TOUCH GENERIC + end + end + end end end + -- To view, visit https://review.coreboot.org/c/coreboot/+/81335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5433693973a21e90886c9075a23aaac84b2f642d Gerrit-Change-Number: 81335 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: amdfwtool: Move linking BHD2 to PSP2 from main to link funcion
by Bao Zheng (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81334?usp=email to review the following change. Change subject: amdfwtool: Move linking BHD2 to PSP2 from main to link funcion ...................................................................... amdfwtool: Move linking BHD2 to PSP2 from main to link funcion Move the complexity from main to function, so the main flow is easy to understand. Change-Id: Ia549a0d08c2a60b8858440543ac8d8b5259017dd Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 16 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/81334/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 64fdfd8..e1aadbe 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1208,15 +1208,22 @@ biosdir->entries[idx].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); } -static void integrate_bios_levels(context *ctx) +static void integrate_bios_levels(context *ctx, amd_cb_config *cb_config) { - unsigned int count = ctx->biosdir->header.num_entries; + unsigned int count; uint32_t current_table_save; - current_table_save = ctx->current_table; - ctx->current_table = (char *)ctx->biosdir - ctx->rom; - - if (ctx->biosdir2) { + if (cb_config->recovery_ab) { + add_psp_firmware_entry(ctx, ctx->pspdir2, ctx->biosdir2, + AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); + if (ctx->pspdir2_b != NULL) + add_psp_firmware_entry(ctx, ctx->pspdir2_b, + ctx->biosdir2_b, AMD_FW_BIOS_TABLE, + TABLE_ALIGNMENT); + } else if (ctx->biosdir2) { + current_table_save = ctx->current_table; + ctx->current_table = (char *)ctx->biosdir - ctx->rom; + count = ctx->biosdir->header.num_entries; assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); ctx->biosdir->entries[count].type = AMD_BIOS_L2_PTR; ctx->biosdir->entries[count].region_type = 0; @@ -1235,9 +1242,9 @@ ctx->biosdir->entries[count].reset = 0; ctx->biosdir->entries[count].ro = 0; count++; + fill_dir_header(ctx->biosdir, count, ctx); + ctx->current_table = current_table_save; } - fill_dir_header(ctx->biosdir, count, ctx); - ctx->current_table = current_table_save; } static void integrate_bios_firmwares(context *ctx, amd_bios_entry *fw_table, @@ -1761,17 +1768,11 @@ amd_bios_table, BHDL2_COOKIE, &cb_config); } - add_psp_firmware_entry(&ctx, ctx.pspdir2, ctx.biosdir2, - AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); - if (ctx.pspdir2_b != NULL) - add_psp_firmware_entry(&ctx, ctx.pspdir2_b, - ctx.biosdir2_b, AMD_FW_BIOS_TABLE, - TABLE_ALIGNMENT); } else { integrate_bios_firmwares(&ctx, amd_bios_table, BHD_COOKIE, &cb_config); - integrate_bios_levels(&ctx); } + integrate_bios_levels(&ctx, &cb_config); } else { /* flat: BHD1 cookie and no pointer to 2nd table */ integrate_bios_firmwares(&ctx, -- To view, visit https://review.coreboot.org/c/coreboot/+/81334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia549a0d08c2a60b8858440543ac8d8b5259017dd Gerrit-Change-Number: 81334 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: amdfwtool: Set the cookie when the table header is created
by Bao Zheng (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Zheng Bao. Hello Felix Held, Fred Reitberger, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81254?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set the cookie when the table header is created ...................................................................... amdfwtool: Set the cookie when the table header is created When the table is created, the cookie is known. When the packing going on, the cookie in header can be checked to see where we are. TEST=Identical test on all AMD SOC platform Change-Id: I300e30292c68a14b44c637b26a13b308dc9c0388 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/81254/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I300e30292c68a14b44c637b26a13b308dc9c0388 Gerrit-Change-Number: 81254 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: amdfwtool: Move the header creation into integration function
by Bao Zheng (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Zheng Bao. Hello Felix Held, Fred Reitberger, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81253?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Move the header creation into integration function ...................................................................... amdfwtool: Move the header creation into integration function Before every integration there is a header creation. We can put them together. And the parameters for PSP/BIOS tables are useless. TEST=Identical test on all AMD SOC platform Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 30 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81253/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199 Gerrit-Change-Number: 81253 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... mb/google/rex: Add Intel Touch for controller 1 for Rex GPIO pad configuration for THC1 according to CBI fw_config. ACPI entries in SSDT for ELAN according to CBI fw_config. THC0 must be enabled when THC1 is enabled. Major rework is required for Rex P1 and P2. minor Rework is needed for EVT. Rex with THC rework won't be able to support UWB and FPCMU. The touch device must be converted to SPI interface. When THC is enabled and the THC rework is in place, the UWB and FPMCU are not supported and need to be disable from the CBI. THC0 will also be provided with ACPI entries when THC1 is enabled. THC1 GPIO pins will be configured for THC according to the CBI TOUCHSCREEN fw_config field. The resistor on the THC-SPI MISO pin should be 100 Ohm. BUG=b:307775082 TEST=set CBI TOUCHSREEN fw_config to TOUCHSCREEN_THC, FP fw_config to FP_ABSENT, and UWB fw_config to UWB_ABSENT. boot Rex to OS and run lspci to check THC device and check that THC device driver initialization successfully. /sys/class/hidraw/hidraw0/device/input/ should have several inputs enumerated. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 3 files changed, 163 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81333/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 880680a..a816ccc 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -88,6 +88,7 @@ select DRIVERS_NXP_UWB_SR1XX select DRIVERS_SOUNDWIRE_CS42L42 select DRIVERS_SOUNDWIRE_MAX98363 + select SOC_INTEL_TOUCH config BOARD_GOOGLE_MODEL_REX_EC_ISH def_bool n diff --git a/src/mainboard/google/rex/variants/rex0/fw_config.c b/src/mainboard/google/rex/variants/rex0/fw_config.c index 60dd6bf..00f644e 100644 --- a/src/mainboard/google/rex/variants/rex0/fw_config.c +++ b/src/mainboard/google/rex/variants/rex0/fw_config.c @@ -5,6 +5,16 @@ #include <console/console.h> #include <fw_config.h> #include <gpio.h> +#include <halt.h> + +#if CONFIG(SOC_INTEL_TOUCH) +#include <soc/pci_devs.h> +#include <drivers/intel/touch/chip.h> +WEAK_DEV_PTR(touch_0_none); +WEAK_DEV_PTR(touch_1_elan); +WEAK_DEV_PTR(touch_1_generic); +const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx); +#endif #define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) @@ -130,8 +140,42 @@ PAD_CFG_GPO(GPP_B17, 0, DEEP) /* EN_WWAN_PWR */ }; +#if CONFIG(SOC_INTEL_TOUCH) +static const struct pad_config thc1_touch_pads[] = { + /* Proto1&2: With THC rework, UWB connector has been used for THC1 instead */ + // PAD_CFG_GPO_LOCK(GPP_D07, 1, LOCK_CONFIG), /* FPMCU_UWB_MUX_SEL */ + PAD_CFG_GPO(GPP_D07, 0, PWROK), /* FPMCU_UWB_MUX_SEL */ + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ + PAD_CFG_GPI(GPP_C01, NONE, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + // PAD_NC(GPP_C07, NONE), + PAD_CFG_GPI(GPP_C07, NONE, DEEP), + /* GPP_F11 : NF3: THC1_SPI2_CLK NF5: GSP1_SOC_CLK_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF3), + /* GPP_F12 : NF3: THC1_SPI2_IO_0 NF5: GSPI1_SOC_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF3), + /* GPP_F13 : NF3: THC1_SPI2_IO_1 NF5: GSPI1_SOC_DI_FPMCU_DO_LS_R */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF3), + /* GPP_F14 : NF3: THC1_SPI2_IO_2 NF8: GSPI0_SOC_DO_TCHSCR_DI NOTE:not used */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 : NF3: THC1_SPI2_IO_3 NF8: GSPI0_SOC_DI_TCHSCR_DO NOTE:not used */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 : NF3: THC1_SPI2_RST_B NF8: GSPI0_SOC_TCHSCR_CLK */ + /* NOTE: configure as GPO for reset pin */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* GPP_F17 : NF3: THC1_SPI2_CS_B NF8: GSPI1_SOC_CS_L */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), + /* GPP_F18 : NF3: THC1_SPI2_INT_B NF8: GSPI0_SOC_TCHSCR_CS_L */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), +}; +#endif + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + bool fw_config_fp_absent; + bool fw_config_uwb_gspi1; + bool fw_config_thc; + if (!fw_config_is_provisioned()) { GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); @@ -168,25 +212,79 @@ GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads); } + fw_config_fp_absent = fw_config_probe(FW_CONFIG(FP, FP_ABSENT)); + fw_config_uwb_gspi1 = fw_config_probe(FW_CONFIG(UWB, UWB_GSPI1)); + fw_config_thc = fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC)); + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_I2C))) { printk(BIOS_INFO, "Configure Touchscreen Interrupt for I2C.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_i2c_int_pads); - } else { /* SPI */ + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) { printk(BIOS_INFO, "Configure Touchscreen Interrupt for SPI.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_spi_int_pads); +#if CONFIG(SOC_INTEL_TOUCH) + } else if (fw_config_thc) { + if (fw_config_uwb_gspi1) { + printk(BIOS_ERR, "Already enabled for THC1.Cannot have UWB with gspi1! Powering off. Please check HW.\n"); + poweroff(); + } else if (!fw_config_fp_absent) { + printk(BIOS_ERR, "Already enabled for THC1.Cannot have UWB with gspi1! Powering off. Please check HW.\n"); + poweroff(); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, thc1_touch_pads); + } +#endif } - if (fw_config_probe(FW_CONFIG(UWB, UWB_GSPI1)) && - fw_config_probe(FW_CONFIG(FP, FP_ABSENT))) { - printk(BIOS_INFO, "Configure GPIOs for UWB over GSPI1.\n"); - GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_enable_pads); - } else { - printk(BIOS_INFO, "Disabling UWB (absent or misconfigured)\n"); - GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_disable_pads); - } + if (!fw_config_thc) { + if (fw_config_uwb_gspi1 && fw_config_fp_absent) { + printk(BIOS_INFO, "Configure GPIOs for UWB over GSPI1.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_enable_pads); + } else { + printk(BIOS_INFO, "Disabling UWB (absent or misconfigured)\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_disable_pads); + if (fw_config_uwb_gspi1 && !fw_config_fp_absent) { + /* FPMCU GPIOs is already enabled in gpio.c */ + /* GPP_E10:SOC_FPMCU_INT_L GPP_B11: EN_FP_PWR GPP_C22: FP_BOOT0 GPP_C23:SOC_FP_RST_L */ + } else { + /* FPMCU GPIOs can be disabled here */ + } + } + } if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) { printk(BIOS_INFO, "Configure GPIOs for no cellular.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads); } } + +#if CONFIG(SOC_INTEL_TOUCH) +const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx) +{ + const struct drivers_intel_touch_config *touch_config = NULL; + + if (ctl_idx == 0) { + if (is_devfn_enabled(PCI_DEVFN_THC0)) { + printk(BIOS_DEBUG, "THC0 device function is enabled\n"); + /* NOTE: thc0 needs to be enabled when there is sensor connected to thc1 in Rex */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC))) { + printk(BIOS_DEBUG, "THC1 uses ELAN sensor\n"); + touch_config = config_of(DEV_PTR(touch_0_none)); + } + } + } else if (ctl_idx == 1) { + + if (is_devfn_enabled(PCI_DEVFN_THC1)) { + printk(BIOS_DEBUG, "THC1 device function is enabled\n"); + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC))) { + printk(BIOS_DEBUG, "THC1 uses ELAN sensor\n"); + touch_config = config_of(DEV_PTR(touch_1_elan)); + } + } + } else { + printk(BIOS_WARNING, "Only THC0 and THC1 are supported!\n"); + return NULL; + } + return touch_config; +} +#endif diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 12068ce..410e393 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -30,10 +30,12 @@ option USB4_HAYDEN_BRIDGE 4 option USB4_ANX7452_V2 5 end + # THC NOTE for P1 and P2:reworked Rex will set the MUX to route to UWB connector for THC1. Use FP_ABSENT. field FP 15 option FP_PRESENT 0 option FP_ABSENT 1 end + # THC NOTE for P1 and P2:reworked Rex use UWB connector for THC1; Use UWB_ABSENT field UWB 16 17 option UWB_ABSENT 0 option UWB_BITBANG 1 @@ -78,6 +80,9 @@ # Enable HDMI in Port B register "ddi_port_B_config" = "0" + # THC configuration + register "thc_configuration" = "THC_CONFIG_DOUBLE_CONTROLLER" + # Enable Display Port Configuration register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, @@ -811,10 +816,17 @@ end probe DB_SD SD_GL9755S end + + # THC NOTE: + # gspi0 needs to be disabled for Intel HIDSPI touch. The ACPI for + # gspi touch is in: /variants/rex0/include/variant/acpi/hid_spi_elan.asl + # When THC is enabled, this ASL will need to be excluded. device ref gspi0 on probe TOUCHSCREEN TOUCHSCREEN_GSPI end device ref gspi1 on + probe FP FP_PRESENT + probe UWB UWB_GSPI1 chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -910,5 +922,48 @@ end end end + # THC NOTE: When thc1 is connected to a sensor device, thc0 also needs to be enabled. + # THC NOTE: needs SOC_INTEL_TOUCH + device ref thc0 on + probe TOUCHSCREEN TOUCHSCREEN_THC + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + register "connected_device" = "TH_SENSOR_NONE" + # register "sensor_dev_name" = "ELAN_DEV_NAME" + # register "connected_device" = "TH_SENSOR_ELAN" + device generic 0 alias touch_0_none on + # NOTE: thc0 needs to be enabled when using thc1 + probe TOUCHSCREEN TOUCHSCREEN_THC + end + end + end + device ref thc1 on + probe TOUCHSCREEN TOUCHSCREEN_THC + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_SPI_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "2" + register "rpt_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)" + # register "rpt_delay_ms" = "0" + register "rpt_off_delay_ms" = "2" + + register "wake_on_touch" = "1" + register "wake_irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_VGPIO3_THC1)" + + register "hidspi_flags" = "HIDSPI_WRITE_MODE_SINGLE" + register "hidspi_reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "sensor_dev_name" = "ELAN_DEV_NAME" + register "connected_device" = "TH_SENSOR_ELAN" + device generic 0 alias touch_1_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/meteorlake: Update Touch Controller UDP params
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81332?usp=email ) Change subject: soc/intel/meteorlake: Update Touch Controller UDP params ...................................................................... soc/intel/meteorlake: Update Touch Controller UDP params The UPD, ThcAssignment, and ThcMode, ThcWakeOnTouch, are specified via THC driver in the device tree. Therefore, SOC needs to get the driver config. a weak function drivers_intel_touch_config() is added such that the mainboard can implement the function to provide the config from the device tree. The CONFIG_SOC_INTEL_TOUCH is needed to add THC support for Meteorlake SOC. BUG=b:307775082 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1 --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 4 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81332/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index a4ebad4..c4a7170 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -155,6 +155,11 @@ select COS_MAPPED_TO_MSB select CAR_HAS_L3_PROTECTED_WAYS +config SOC_INTEL_TOUCH + bool + default n + select DRIVERS_INTEL_TOUCH + config MAX_CPUS int default 22 diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 03adfdb..b5647d3 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -82,6 +82,8 @@ case PCI_DEVFN_TBT2: return "TRP2"; case PCI_DEVFN_TBT3: return "TRP3"; case PCI_DEVFN_IPU: return "IPU0"; + case PCI_DEVFN_THC0: return "THC0"; + case PCI_DEVFN_THC1: return "THC1"; case PCI_DEVFN_ISH: return "ISHB"; case PCI_DEVFN_GNA: return "GNA"; case PCI_DEVFN_XHCI: return "XHCI"; diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index cfef3c1..1eb66aa 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -525,6 +525,13 @@ * as per `enum slew_rate` data type. */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + + /* THC configuraiton */ + enum { + THC_CONFIG_NONE, + THC_CONFIG_SINGLE_PORT0, + THC_CONFIG_DOUBLE_CONTROLLER, + } thc_configuration; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index a02d4b9..557dfda 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -34,6 +34,10 @@ #include <stdlib.h> #include <string.h> #include <types.h> +#if CONFIG(SOC_INTEL_TOUCH) +#include <drivers/intel/touch/chip.h> +const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx); +#endif /* THC assignment definition */ #define THC_NONE 0 @@ -599,6 +603,77 @@ s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD); } +#if CONFIG(SOC_INTEL_TOUCH) +__weak const struct drivers_intel_touch_config *mainboard_get_intel_touch_config(int ctl_idx) +{ + printk(BIOS_ERR, "missing %s define in the mainboard\n", __func__); + return NULL; +} + +static void fill_fsps_single_thc_params(FSP_S_CONFIG *s_cfg, int ctl_idx) +{ + const struct drivers_intel_touch_config *touch_config = mainboard_get_intel_touch_config(ctl_idx); + if (touch_config == NULL) { + printk(BIOS_ERR, "No config found for THC%d\n", ctl_idx); + return; + } + s_cfg->ThcMode[ctl_idx] = touch_config->mode; + printk(BIOS_DEBUG, "THC%d mode: %d\n", ctl_idx, touch_config->mode); + printk(BIOS_DEBUG, "THC%d connected device: %d\n", ctl_idx, + touch_config->connected_device); + if (touch_config->mode == THC_HID_SPI_MODE) { + if (touch_config->connected_device != TH_SENSOR_NONE) { + printk(BIOS_DEBUG, "THC%d sensor device: %s\n", ctl_idx, + touch_config->sensor_dev_name); + printk(BIOS_DEBUG, "THC%d wake enable: %d\n", ctl_idx, + touch_config->wake_on_touch); + s_cfg->ThcWakeOnTouch[ctl_idx] = touch_config->wake_on_touch; + } + } else + printk(BIOS_DEBUG, "THC UPD update is only required for THC with HID SPID mode at this time!\n"); +} + +static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + s_cfg->ThcAssignment[0] = THC_NONE; + s_cfg->ThcAssignment[1] = THC_NONE; + + switch (config->thc_configuration) { + case THC_CONFIG_NONE: + printk(BIOS_WARNING, "THC configuration: None\n"); + break; + case THC_CONFIG_SINGLE_PORT0: + printk(BIOS_WARNING, "THC configuration: THC0 Controllers\n"); + if (is_devfn_enabled(PCI_DEVFN_THC0)) { + s_cfg->ThcAssignment[0] = THC_0; + s_cfg->ThcAssignment[1] = THC_NONE; + fill_fsps_single_thc_params(s_cfg, 0); + } else + printk(BIOS_WARNING, "THC0 is not enabled for configuration.\n"); + if (is_devfn_enabled(PCI_DEVFN_THC1)) + printk(BIOS_WARNING, + "Only THC0 should be enabled for single port configuration\n"); + break; + case THC_CONFIG_DOUBLE_CONTROLLER: + printk(BIOS_WARNING, "THC configuration: Double Controllers\n"); + if (is_devfn_enabled(PCI_DEVFN_THC0)) { + printk(BIOS_DEBUG, "THC0 function is enabled\n"); + s_cfg->ThcAssignment[0] = THC_0; + fill_fsps_single_thc_params(s_cfg, 0); + } + if (is_devfn_enabled(PCI_DEVFN_THC1)) { + printk(BIOS_DEBUG, "THC1 function is enabled\n"); + s_cfg->ThcAssignment[1] = THC_1; + fill_fsps_single_thc_params(s_cfg, 1); + } + if (!is_devfn_enabled(PCI_DEVFN_THC0) || !is_devfn_enabled(PCI_DEVFN_THC1)) + printk(BIOS_WARNING, + "Both THC0 and THC1 must be enabled for double controller configuration!\n"); + } +} +#endif + static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { @@ -802,6 +877,9 @@ fill_fsps_lan_params, fill_fsps_cnvi_params, fill_fsps_vmd_params, +#if CONFIG(SOC_INTEL_TOUCH) + fill_fsps_thc_params, +#endif fill_fsps_tbt_params, fill_fsps_8254_params, fill_fsps_pm_timer_params, -- To view, visit https://review.coreboot.org/c/coreboot/+/81332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1 Gerrit-Change-Number: 81332 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: amdfwtool: Add functions to link all the tables
by Bao Zheng (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Zheng Bao. Hello Felix Held, Fred Reitberger, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81252?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Add functions to link all the tables ...................................................................... amdfwtool: Add functions to link all the tables The purpose of integration function is to pack the FWs into table. We need to remove other process. Create a dedicate function to combine all the tables together. This simplifies the function and logic. TEST=Identical test on all AMD SOC platform Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 89 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81252/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Gerrit-Change-Number: 81252 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024