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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS9:
> Good suggestion, thanks!
Done
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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS9:
> If possible, please contain the changes within `soc_util.h`. […]
Good suggestion, thanks!
File src/soc/intel/xeon_sp/include/soc/fsp_adoption.h:
https://review.coreboot.org/c/coreboot/+/81040/comment/1cf5c926_dd7353be :
PS9, Line 21: #define xSTACK_RES UDS_STACK_RES
> If the types are compatible, wouldn't it be enough to […]
It will work, but personally I'm inclined to keep the C code changes, since the redefine (xSTACK_RES) will reminder developers that this is a redefined symbol.
This is aligned with how FSP driver handles a similar issue, in src/drivers/intel/fsp2_0/include/fsp/util.h
#if CONFIG(PLATFORM_USES_FSP2_4)
#define FSPM_ARCHx_UPD FSPM_ARCH2_UPD
#define FSPS_ARCHx_UPD FSPS_ARCH2_UPD
#else
#define FSPM_ARCHx_UPD FSPM_ARCH_UPD
#define FSPS_ARCHx_UPD FSPS_ARCH_UPD
#endif
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
First provide the original issue b/204230406 for reference.
I'm worried that the original state of the board might not have been taken into consideration.
Has this been verified on Felwinter?
Because this has been shipped.
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Change subject: soc/xeon_sp: Initially add N-1 IBL codes
......................................................................
soc/xeon_sp: Initially add N-1 IBL codes
N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.
Change-Id: I5de2d2f4985b4677dbc156fd8b158c0ab0e46342
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
A src/soc/intel/xeon_sp/ibl/Makefile.mk
A src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h
A src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h
A src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
A src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
A src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h
A src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h
A src/soc/intel/xeon_sp/ibl/lockdown.c
A src/soc/intel/xeon_sp/ibl/soc_gpio.c
A src/soc/intel/xeon_sp/ibl/soc_pch.c
A src/soc/intel/xeon_sp/ibl/soc_pmutil.c
M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h
12 files changed, 903 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81315/8
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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
......................................................................
soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
GraniteRapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/
UDS_SOCKET_RES and retires the usages of STACK_RES/
IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common
codes to work for both 6th Gen before and later.
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---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h
6 files changed, 25 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/10
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
......................................................................
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
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---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/chip_common.c
A src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
4 files changed, 197 insertions(+), 174 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/9
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Interesting, when I did the felwinter project. I already verified all the USB. […]
We see an issue when we apply the first patch in this series where we try to copy _PLD from usb port to mux. PMC mux conn1 uses usbX_port2 and conn2 uses usbX_port3. So, conn1's PLD is to be copied from usbX_port2 and conn2's PLD is to be copied from usbX_port3.
The issue is that `fill_ssdt_typec_device` in `ec_acpi.c` matches conn1 to usbX_port3 and conn2 to usbX_port2, which are reversed. The reason is that given index i, mux_conn[i] is matched with usb port's PLD group token of i+1, so mux_conn[0] is matched with usbX_port2 with group token of 1 and mux_conn[1] is matched with usbX_port3 with group token of 2. Since mux_conn[0] is conn2 and mux_conn[1] is conn1, this matching is swapped.
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Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
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Patch Set 8: Code-Review+1
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
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Patch Set 4:
(1 comment)
Patchset:
PS4:
Interesting, when I did the felwinter project. I already verified all the USB. Anything changed caused the we need change again?
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
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Patch Set 4: Code-Review+2
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