coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Correct the layout
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81394?usp=email ) Change subject: mb/starlabs/starbook/adl: Correct the layout ...................................................................... mb/starlabs/starbook/adl: Correct the layout Adjust the size of the ME partition to match the descriptor Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/adl/board.fmd 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/board.fmd b/src/mainboard/starlabs/starbook/variants/adl/board.fmd index 6a13b46..b652a36 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/board.fmd +++ b/src/mainboard/starlabs/starbook/variants/adl/board.fmd @@ -1,7 +1,7 @@ FLASH 0x2000000 { SI_ALL 0x1000000 { SI_DESC 0x1000 - SI_ME 0x466000 + SI_ME 0x41c000 } SI_BIOS 0x1000000 { EC@0x0 0x20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/81394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Gerrit-Change-Number: 81394 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/starlabs/starbook/{adl,rpl}: Disable CNVi
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81393?usp=email ) Change subject: mb/starlabs/starbook/{adl,rpl}: Disable CNVi ...................................................................... mb/starlabs/starbook/{adl,rpl}: Disable CNVi No variants were ever built with CNVi cards, so disable this device. Change-Id: I3725465eae0c7ade3dafa03add151353818ee761 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb 2 files changed, 0 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 9362b45..f7b45d3 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -17,9 +17,6 @@ # FSP Silicon register "eist_enable" = "1" - register "cnvi_bt_core" = "1" - register "cnvi_bt_audio_offload" = "1" - # Serial I/O register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -87,12 +84,6 @@ end end device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 83f49d9..22f824f 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -7,9 +7,6 @@ register "eist_enable" = "1" register "enable_c1e" = "1" - register "cnvi_bt_core" = "1" - register "cnvi_bt_audio_offload" = "1" - register "disable_dynamic_tccold_handshake" = "1" # Serial I/O @@ -108,12 +105,6 @@ end end device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/81393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3725465eae0c7ade3dafa03add151353818ee761 Gerrit-Change-Number: 81393 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dram
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

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[XS] Change in coreboot[main]: soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhere
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

1 0

[XS] Change in coreboot[main]: soc/amd/common/cpu/noncar/memmap: make local variables const
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

1 0

[M] Change in coreboot[main]: soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81389?usp=email ) Change subject: soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources ...................................................................... soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources Since the code for reporting the memory map up until cbmem_top is basically identical for all non-CAR AMD SoCs, factor this out into a common read_lower_soc_memmap_resources implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 --- M src/soc/amd/cezanne/memmap.c M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/include/amdblocks/memmap.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/memmap.c M src/soc/amd/mendocino/memmap.c M src/soc/amd/phoenix/memmap.c M src/soc/amd/picasso/memmap.c 8 files changed, 46 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81389/1 diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c index 6c8e932..bb1eca2 100644 --- a/src/soc/amd/cezanne/memmap.c +++ b/src/soc/amd/cezanne/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index e21cff8a3..2aaba83 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -2,9 +2,11 @@ #include <amdblocks/memmap.h> #include <amdblocks/smm.h> +#include <arch/vga.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/smm.h> +#include <device/device.h> #include <memrange.h> #include <types.h> @@ -21,7 +23,7 @@ e->size = REGION_SIZE(early_reserved_dram); } -const struct memmap_early_dram *memmap_get_early_dram_usage(void) +static const struct memmap_early_dram *memmap_get_early_dram_usage(void) { struct memmap_early_dram *e = cbmem_find(CBMEM_ID_CB_EARLY_DRAM); @@ -31,6 +33,39 @@ return e; } +/* report SoC memory map up to cbmem_top */ +void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); +} + void smm_region(uintptr_t *start, size_t *size) { static int once; diff --git a/src/soc/amd/common/block/include/amdblocks/memmap.h b/src/soc/amd/common/block/include/amdblocks/memmap.h index cc89d86..258b8b7 100644 --- a/src/soc/amd/common/block/include/amdblocks/memmap.h +++ b/src/soc/amd/common/block/include/amdblocks/memmap.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_MEMMAP_H #define AMD_BLOCK_MEMMAP_H +#include <device/device.h> #include <stdint.h> #include <symbols.h> @@ -15,7 +16,9 @@ }; void memmap_stash_early_dram_usage(void); -const struct memmap_early_dram *memmap_get_early_dram_usage(void); + +/* report SoC memory map up to cbmem_top */ +void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx); void fsp_get_smm_region(uintptr_t *start, size_t *size); diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 6154908..88f386c 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -7,7 +7,6 @@ #include <amdblocks/root_complex.h> #include <amdblocks/smn.h> #include <arch/ioapic.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <types.h> @@ -18,28 +17,7 @@ void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { - ram_from_to(domain, (*idx)++, 0, 0xa0000); - mmio_from_to(domain, (*idx)++, 0xa0000, 0xc0000); // legacy VGA - reserved_ram_from_to(domain, (*idx)++, 0xc0000, 1 * MiB); // Option ROM - - uint32_t mem_usable = (uintptr_t)cbmem_top(); - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - // 1MB - bottom of DRAM reserved for early coreboot usage - ram_from_to(domain, (*idx)++, 1 * MiB, early_reserved_dram_start); - - // DRAM reserved for early coreboot usage - reserved_ram_from_to(domain, (*idx)++, early_reserved_dram_start, - early_reserved_dram_end); - - // top of DRAM consumed early - low top usable RAM - // cbmem_top() accounts for low UMA and TSEG if they are used. - ram_from_to(domain, (*idx)++, early_reserved_dram_end, - mem_usable); + read_lower_soc_memmap_resources(domain, idx); add_opensil_memmap(domain, idx); } diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c index d347bae..feecdd7 100644 --- a/src/soc/amd/glinda/memmap.c +++ b/src/soc/amd/glinda/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c index d347bae..feecdd7 100644 --- a/src/soc/amd/mendocino/memmap.c +++ b/src/soc/amd/mendocino/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,34 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c index e516572..9e740cb 100644 --- a/src/soc/amd/phoenix/memmap.c +++ b/src/soc/amd/phoenix/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> #include <vendorcode/amd/opensil/stub/opensil.h> @@ -63,34 +61,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 7ec7adf..2bbf285 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -3,8 +3,6 @@ #include <amdblocks/memmap.h> #include <amdblocks/iomap.h> #include <amdblocks/root_complex.h> -#include <arch/vga.h> -#include <cbmem.h> #include <device/device.h> #include <stdint.h> @@ -62,32 +60,7 @@ */ void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + read_lower_soc_memmap_resources(dev, idx); /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/81389?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 Gerrit-Change-Number: 81389 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/genoa_poc/domain: refactor read_soc_memmap_resources
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81388?usp=email ) Change subject: soc/amd/genoa_poc/domain: refactor read_soc_memmap_resources ...................................................................... soc/amd/genoa_poc/domain: refactor read_soc_memmap_resources To bring genoa_poc more in line with the other AMD SoCs, move the reporting of the memory map up to cbmem_top from the openSIL-specific add_opensil_memmap function to read_soc_memmap_resources. This is a preparation for making this code common for all newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f --- M src/soc/amd/genoa_poc/domain.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c 2 files changed, 26 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/81388/1 diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 5672f65..6154908 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -3,9 +3,11 @@ #include <acpi/acpigen_pci.h> #include <amdblocks/ioapic.h> #include <amdblocks/data_fabric.h> +#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <amdblocks/smn.h> #include <arch/ioapic.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <types.h> @@ -16,6 +18,29 @@ void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { + ram_from_to(domain, (*idx)++, 0, 0xa0000); + mmio_from_to(domain, (*idx)++, 0xa0000, 0xc0000); // legacy VGA + reserved_ram_from_to(domain, (*idx)++, 0xc0000, 1 * MiB); // Option ROM + + uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + // 1MB - bottom of DRAM reserved for early coreboot usage + ram_from_to(domain, (*idx)++, 1 * MiB, early_reserved_dram_start); + + // DRAM reserved for early coreboot usage + reserved_ram_from_to(domain, (*idx)++, early_reserved_dram_start, + early_reserved_dram_end); + + // top of DRAM consumed early - low top usable RAM + // cbmem_top() accounts for low UMA and TSEG if they are used. + ram_from_to(domain, (*idx)++, early_reserved_dram_end, + mem_usable); + add_opensil_memmap(domain, idx); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index b1d4b93..bdf58e9 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -86,30 +86,8 @@ // This assumes holes are allocated void add_opensil_memmap(struct device *dev, unsigned long *idx) { - ram_from_to(dev, (*idx)++, 0, 0xa0000); - mmio_from_to(dev, (*idx)++, 0xa0000, 0xc0000); // legacy VGA - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); // Option ROM - - uint32_t mem_usable = (uintptr_t)cbmem_top(); - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - // 1MB - bottom of DRAM reserved for early coreboot usage - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - // DRAM reserved for early coreboot usage - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, - early_reserved_dram_end); - - // top of DRAM consumed early - low top usable RAM - // cbmem_top() accounts for low UMA and TSEG if they are used. - ram_from_to(dev, (*idx)++, early_reserved_dram_end, - mem_usable); - // Account for UMA and TSEG + const uint32_t mem_usable = (uintptr_t)cbmem_top(); const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB); if (mem_usable != top_mem) reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); -- To view, visit https://review.coreboot.org/c/coreboot/+/81388?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f Gerrit-Change-Number: 81388 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: src: Add missing SPDX license headers
by Nicholas Chin (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Jason Nien, Martin Roth, Philipp Hug, ron minnich. Hello Jason Nien, Martin Roth, Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81421?usp=email to look at the new patch set (#2). Change subject: src: Add missing SPDX license headers ...................................................................... src: Add missing SPDX license headers Other files in the commits that added these files were licensed under GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that as the license. Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/soc/sifive/fu740/include/soc/gpio.h 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/81421/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e Gerrit-Change-Number: 81421 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Nico Huber (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81312/comment/3179cc6d_ac429538 : PS14, Line 224: if (is_ubox_stack_res(ri)) : soc_create_ubox_domains(dn, root_bus, ri, seg); : else if (CONFIG(SOC_INTEL_HAS_CXL) && is_iio_cxl_stack_res(ri)) : soc_create_cxl_domains(dn, root_bus, ri, seg); : else if (is_pcie_iio_stack_res(ri)) : soc_create_pcie_domains(dn, root_bus, ri, seg); : else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) : soc_create_ioat_domains(dn, root_bus, ri, seg); > soc_create_domains() Just noticed that name is already taken. Well, any other name then :) (might be a good idea to get some concept into the prefixes. in the original `soc/intel/` parts, `soc_` is usually used for chip-specific code. if everything ends up with a soc_ prefix, we could as well not have any prefix.) -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Mar 2024 16:08:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/lint: Fix license header regex
by Nicholas Chin (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Martin L Roth. Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81422?usp=email ) Change subject: util/lint: Fix license header regex ...................................................................... util/lint: Fix license header regex A trailing | at the end of the regex added a zero length alternative match, causing all files to match and be filtered out. Also, a missing | separator between cmos.default and .apcb would cause those files to be unintentionally scanned. Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/lint/lint-000-license-headers 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81422/1 diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 68bdae7..56addac 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -67,8 +67,8 @@ \.spd|\ config|\ cmos\.layout|\ -cmos\.default\ -\.apcb$|\ +cmos\.default|\ +\.apcb$\ " #space separated list of directories to test -- To view, visit https://review.coreboot.org/c/coreboot/+/81422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef Gerrit-Change-Number: 81422 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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