coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: TESTONLY: mb/dell/e6400/bootblock.c: Remove license header
by Nicholas Chin (Code Review) 22 Mar '24

22 Mar '24

Nicholas Chin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81423?usp=email ) Change subject: TESTONLY: mb/dell/e6400/bootblock.c: Remove license header ...................................................................... Abandoned Test completed, CI properly fails after fix -- To view, visit https://review.coreboot.org/c/coreboot/+/81423?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93b3897ed1eac13b08961d02d3f7f0dea8286e14 Gerrit-Change-Number: 81423 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Jérémy Compostella (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80337/comment/ff433395_5c46a8ba : PS13, Line 28: TESTED > > TEST: <...> […] You comment triggered my curiosity, thank you. I have been using the `TEST` tag following people recommendation and without checking the documentation. I found the following guideline this morning. https://doc.coreboot.org/contributing/gerrit_guidelines.html#recommendation… So it looks like two following are correct: ``` Tested that google/vilbox and qemu/q35 boot to payload ``` or ``` TEST: booted to payload on google/vilbox and qemu/q35 ``` I have a little preference for the second one as being more formal it can easily been extracted by a script if someone would wanted to collect some test practices. -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Mar 2024 17:01:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#5). Change subject: [for test] upgrade crossgcc ...................................................................... [for test] upgrade crossgcc upgarde LLVM to 18.1.2 & LD upgrade CMake to 3.29.0 upgrade IASL to G20240322 Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-G20240322_iasl.patch A util/crossgcc/sum/G20240322.tar.gz.cksum D util/crossgcc/sum/R06_28_23.tar.gz.cksum D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.29.0.tar.gz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.2.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.2.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.2.src.tar.xz.cksum 18 files changed, 26 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: [for test] upgrade crossgcc ...................................................................... [for test] upgrade crossgcc upgarde LLVM to 18.1.2 & LD upgrade CMake to 3.29.0 upgrade IASL to G20240322 Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/acpica-R06_28_23_iasl.patch A util/crossgcc/sum/G20240322.tar.gz.cksum D util/crossgcc/sum/R06_28_23.tar.gz.cksum D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.29.0.tar.gz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.2.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.2.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.2.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.2.src.tar.xz.cksum 18 files changed, 26 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: TESTONLY: mb/dell/e6400/bootblock.c: Remove license header
by Nicholas Chin (Code Review) 22 Mar '24

22 Mar '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81423?usp=email ) Change subject: TESTONLY: mb/dell/e6400/bootblock.c: Remove license header ...................................................................... TESTONLY: mb/dell/e6400/bootblock.c: Remove license header For testing util/lint/lint-000-license-headers in CI Change-Id: I93b3897ed1eac13b08961d02d3f7f0dea8286e14 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/e6400/bootblock.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/81423/1 diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/e6400/bootblock.c index c72622e..da4d1bb 100644 --- a/src/mainboard/dell/e6400/bootblock.c +++ b/src/mainboard/dell/e6400/bootblock.c @@ -1,5 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - #include <bootblock_common.h> #include <ec/dell/mec5035/mec5035.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81423?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93b3897ed1eac13b08961d02d3f7f0dea8286e14 Gerrit-Change-Number: 81423 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/starlabs/starbook: Correct alphabetisation of Kconfig options
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81399?usp=email ) Change subject: mb/starlabs/starbook: Correct alphabetisation of Kconfig options ...................................................................... mb/starlabs/starbook: Correct alphabetisation of Kconfig options Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/starlabs/starbook/Kconfig 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 32c8064..a5ba419 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -127,6 +127,10 @@ default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML default "merlin" +config EDK2_BOOTSPLASH_FILE + string + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" @@ -160,14 +164,9 @@ string default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin" - config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n -config EDK2_BOOTSPLASH_FILE - string - default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" - config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL -- To view, visit https://review.coreboot.org/c/coreboot/+/81399?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91 Gerrit-Change-Number: 81399 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Set RP9 detection timeout to 50ms
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81398?usp=email ) Change subject: mb/starlabs/starbook/adl: Set RP9 detection timeout to 50ms ...................................................................... mb/starlabs/starbook/adl: Set RP9 detection timeout to 50ms Certain SSDs are not detected in the default time window, so change this to 50ms to allow these SSDs to be detected. Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index f7b45d3..2437880 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -115,6 +115,7 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_detect_timeout_ms = 50, }" smbios_slot_desc "SlotTypeM2Socket3" -- To view, visit https://review.coreboot.org/c/coreboot/+/81398?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439 Gerrit-Change-Number: 81398 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIO
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81397?usp=email ) Change subject: mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIO ...................................................................... mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIO The CPU port is not used so disable it. Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index 3144c71..32ec1ce 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -374,7 +374,7 @@ /* H18: CPI C10 Gate */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* H19: Clock Request 4 CPU M.2 SSD */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), /* H20: Not Connected */ PAD_NC(GPP_H20, NONE), /* H21: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87 Gerrit-Change-Number: 81397 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO comments
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81396?usp=email ) Change subject: mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO comments ...................................................................... mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO comments Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/rpl/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index b7c9a8f..3144c71 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -206,7 +206,7 @@ PAD_NC(GPP_D3, NONE), /* D4: Not Connected */ PAD_NC(GPP_D4, NONE), - /* D5: Not Connected */ + /* D5: Clock Request 0 */ PAD_NC(GPP_D5, NONE), /* D6: Clock Request 1 PCH M.2 SSD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), @@ -381,7 +381,7 @@ PAD_NC(GPP_H21, NONE), /* H22: Not Connected */ PAD_NC(GPP_H22, NONE), - /* H23: Not Connected */ + /* H23: Clock Request 5 */ PAD_NC(GPP_H23, NONE), /* S0: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index aba6dc8..8572b09 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -206,7 +206,7 @@ PAD_NC(GPP_D3, NONE), /* D4: Not Connected */ PAD_NC(GPP_D4, NONE), - /* D5: Not Connected */ + /* D5: Clock Request 0 */ PAD_NC(GPP_D5, NONE), /* D6: Clock Request 1 PCH M.2 SSD */ PAD_NC(GPP_D6, NONE), @@ -381,7 +381,7 @@ PAD_NC(GPP_H21, NONE), /* H22: Not Connected */ PAD_NC(GPP_H22, NONE), - /* H23: Not Connected */ + /* H23: Clock Request 5 */ PAD_NC(GPP_H23, NONE), /* S0: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f Gerrit-Change-Number: 81396 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"
by Felix Held (Code Review) 22 Mar '24

22 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81395?usp=email ) Change subject: Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride" ...................................................................... Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride" This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881. This was originally assumed to be an FSP/Descriptor/PMC mismatch but it turns out that the problem was coreboot incorrectly detecting ASPM support on devices. Revert so that a proper fix can be applied. Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/adl/romstage.c M src/mainboard/starlabs/starbook/variants/rpl/gpio.c M src/mainboard/starlabs/starbook/variants/rpl/romstage.c 4 files changed, 8 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index 988e6de..b7c9a8f 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -209,11 +209,11 @@ /* D5: Not Connected */ PAD_NC(GPP_D5, NONE), /* D6: Clock Request 1 PCH M.2 SSD */ -// PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D7: Clock Request 2 Wireless LAN */ -// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D8: Clock Request 3 LAN */ -// PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D8, NONE), /* D9: GSPI 2 FPS */ PAD_NC(GPP_D9, NONE), /* D10: GSPI 2 Clock */ @@ -374,7 +374,7 @@ /* H18: CPI C10 Gate */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* H19: Clock Request 4 CPU M.2 SSD */ -// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* H20: Not Connected */ PAD_NC(GPP_H20, NONE), /* H21: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c index 81f1ef3..17629b4 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c @@ -35,5 +35,4 @@ mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4); mupd->FspmConfig.DmiMaxLinkSpeed = 4; - mupd->FspmConfig.GpioOverride = 0; }; diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index 4b4f9ed..aba6dc8 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -209,11 +209,11 @@ /* D5: Not Connected */ PAD_NC(GPP_D5, NONE), /* D6: Clock Request 1 PCH M.2 SSD */ -// PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D6, NONE), /* D7: Clock Request 2 Wireless LAN */ -// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D8: Clock Request 3 LAN */ -// PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D8, NONE), /* D9: GSPI 2 FPS */ PAD_NC(GPP_D9, NONE), /* D10: GSPI 2 Clock */ @@ -374,7 +374,7 @@ /* H18: CPI C10 Gate */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* H19: Clock Request 4 CPU M.2 SSD */ -// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* H20: Not Connected */ PAD_NC(GPP_H20, NONE), /* H21: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c index 085dbfc..e7e1c6a 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c @@ -44,5 +44,4 @@ } mupd->FspmConfig.DmiMaxLinkSpeed = 4; - mupd->FspmConfig.GpioOverride = 0; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Gerrit-Change-Number: 81395 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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