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Change subject: soc/mediatek: Move `get_sdram_config` to common code
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80687/comment/c4a101a5_a060c1ef :
PS2, Line 9: Starting from MT8195
People would need to know the history of MediaTek platforms in order to understand what this means exactly. Therefore I'd prefer an explicit list of SoCs here (and in the code).
File src/soc/mediatek/common/memory.c:
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Attention is currently required from: Cliff Huang, Hannah Williams, Martin L Roth, Stefan Reinauer, Zhixing Ma.
Hello Hannah Williams, Martin L Roth, Stefan Reinauer, Wonkyu Kim, Zhixing Ma, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80726?usp=email
to look at the new patch set (#2).
Change subject: payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH
......................................................................
payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH
Move hard-coded repo and repo name to Kconfig as default value
DEPTHCHARGE_REPO default to:
https://chromium.googlesource.com/chromiumos/platform/depthcharge
DEPTHCHARGE_BRANCH default to:
origin/main
When DEPTHCHARGE_MASTER=y, DEPTHCHARGE_BRANCH can be used to point
out a particular branch.
This change enable to use mirrored internal depthcharge repo and
branch for early SOC development (before upstreaming SOC and
dephthcharge code).
TEST=Build coreboot and check the repo remote link from:
payloads/external/depthcharge/depthcharge
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Icca10aa770b7b7a6e010f58bcf1e4f0a3401681a
---
M payloads/external/Makefile.mk
M payloads/external/depthcharge/Kconfig
M payloads/external/depthcharge/Makefile
3 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/80726/2
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/80343/comment/5b7bd808_3851b190 :
PS8, Line 20: AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
> Yes, please bring the pin configurations back.
Sorry for the late reply. There was an issue with the verbs which turns out to be a bug (CB:80727).
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to look at the new patch set (#19).
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 723 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/19
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Change subject: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
......................................................................
Patch Set 3:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80693/comment/26291719_7444c010 :
PS2, Line 9: MRC_CACHE_USING_MRC_VERSION is by default selected when a platform
: uses EDK binding >= 202302 even the corresponding FSP doesn't provide
: the feature.
> remove this
Done
https://review.coreboot.org/c/coreboot/+/80693/comment/f38e7931_6849cd4a :
PS2, Line 11: as this
> ```for MRC_CACHE_USING_MRC_VERSION as```
Done
https://review.coreboot.org/c/coreboot/+/80693/comment/8651aea0_5753f864 :
PS2, Line 9: MRC_CACHE_USING_MRC_VERSION is by default selected when a platform
: uses EDK binding >= 202302 even the corresponding FSP doesn't provide
: the feature.
> remove this
Done
https://review.coreboot.org/c/coreboot/+/80693/comment/52dd1f2c_7163bd48 :
PS2, Line 11: as this
> ```for MRC_CACHE_USING_MRC_VERSION as```
Done
Patchset:
PS2:
> split this into two cl […]
Done on https://review.coreboot.org/c/coreboot/+/80728
PS2:
> split this into two cl […]
Done on https://review.coreboot.org/c/coreboot/+/80728
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 723 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/18
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Change subject: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
......................................................................
drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
EDK2 version binding is irrelevant for MRC_CACHE_USING_MRC_VERSION
as this is SoC FSP choice to enable/disable this feature. So deselect
the option and leave it to SoC codes to enable it depending on needs.
Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/drivers/mrc_cache/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80693/3
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