coreboot-gerrit February 2024

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[XS] Change in coreboot[main]: lib/rtc: Fix off-by-one error in February day count in leap year
by Michał Żygowski (Code Review) 29 Feb '24

29 Feb '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80790?usp=email ) Change subject: lib/rtc: Fix off-by-one error in February day count in leap year ...................................................................... lib/rtc: Fix off-by-one error in February day count in leap year The month argument passed to rtc_month_days is 0-based, not 1-based. This results in the RTC being reverted to the build date constantly on 29th February 2024. Change-Id: If451e3e3471fef0d429e255cf297050a525ca1a2 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/lib/rtc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/80790/1 diff --git a/src/lib/rtc.c b/src/lib/rtc.c index d151480..3eeac27 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -126,7 +126,7 @@ { int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; - return month_days[month] + (LEAP_YEAR(year) && month == 2); + return month_days[month] + (LEAP_YEAR(year) && month == 1); } int rtc_invalid(const struct rtc_time *tm) -- To view, visit https://review.coreboot.org/c/coreboot/+/80790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If451e3e3471fef0d429e255cf297050a525ca1a2 Gerrit-Change-Number: 80790 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Jamie Chen (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Eric Lai, Ivan Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Hello Derek Huang, Eric Lai, Ivan Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80769?usp=email to look at the new patch set (#5). Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing For TP_EN has a abnormal peek pull high before BL_EN. Because power sequence no meet spec, pre #comment36, it may have ghost touch. BUG=b:326337003 TEST=FW_NAME=omnigul emerge-brya coreboot and measurement of HW Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/gpio.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/80769/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Jamie Chen (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Eric Lai, Ivan Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Hello Derek Huang, Eric Lai, Ivan Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80769?usp=email to look at the new patch set (#4). Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing For TP_EN has a abnormal peek pull high before BL_EN. Because power sequence no meet spec， pre #comment36, it may have ghost touch. BUG=b:326337003 TEST=FW_NAME=omnigul emerge-brya coreboot and measurement of HW Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/gpio.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/80769/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Enable Wake on WLAN for SKU1
by Ashish Kumar Mishra (Code Review) 29 Feb '24

29 Feb '24

Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80780?usp=email ) Change subject: mb/google/brox: Enable Wake on WLAN for SKU1 ...................................................................... mb/google/brox: Enable Wake on WLAN for SKU1 For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/overridetree.cb 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/80780/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 337fde1..760c287 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -91,7 +91,7 @@ /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> VRALERT_L (NC) */ PAD_NC(GPP_B2, NONE), /* GPP_B3 : [NF1: PROC_GP2 NF4: ISH_GP4B NF6: USB_C_GPP_B3] ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index c41be4b..2be2aa6 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -270,6 +270,13 @@ .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI_BT WIFI_BT_PCIE + end + end chip soc/intel/common/block/pcie/rtd3 # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" -- To view, visit https://review.coreboot.org/c/coreboot/+/80780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Gerrit-Change-Number: 80780 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Add GPIO table
by Eric Lai (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shawn Ku. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80764?usp=email ) Change subject: mb/google/nissa/var/glassway: Add GPIO table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4 Gerrit-Change-Number: 80764 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 10:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Select drivers for gpio-keys and Genesy...
by Eric Lai (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80766?usp=email ) Change subject: mb/google/nissa/var/glassway: Select drivers for gpio-keys and Genesys Logic GL9750 ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80766/comment/ea3cc643_43ae2ae8 : PS2, Line 7: Select drivers for gpio-keys and Genesys Logic GL9750 please shorten the title -- To view, visit https://review.coreboot.org/c/coreboot/+/80766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Gerrit-Change-Number: 80766 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 10:00:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
by Felix Singer (Code Review) 29 Feb '24

29 Feb '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80610?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake) ...................................................................... mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake) The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151 processors. M700 comes with B150 chipset, M900 comes with Q170 and is vPro capable. There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled in vendor FW, but for now it's not used here. LPSS UART for debugging is available on pins 17,18 on the underside of the mainboard, but it is not enabled by default. Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5 and Windows 11. Tested and working: - Serial port (via optional module) - Rear DisplayPort connectors - Graphics w/ libgfxinit - Ethernet - SATA - NVMe - Internal speaker, front combo jack, rear line-out - Discrete TPM 1.2 - USB ports (Port 1 untested, apparently broken on my unit) - M.2 2230 Wi-Fi slot (needs ASPM L1s disabled) - S3 suspend - ME disable via NVRAM setting Untested: - Front mic input - Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- A src/mainboard/lenovo/m900_tiny/Kconfig A src/mainboard/lenovo/m900_tiny/Kconfig.name A src/mainboard/lenovo/m900_tiny/Makefile.mk A src/mainboard/lenovo/m900_tiny/acpi/ec.asl A src/mainboard/lenovo/m900_tiny/acpi/superio.asl A src/mainboard/lenovo/m900_tiny/board_info.txt A src/mainboard/lenovo/m900_tiny/bootblock.c A src/mainboard/lenovo/m900_tiny/cmos.default A src/mainboard/lenovo/m900_tiny/cmos.layout A src/mainboard/lenovo/m900_tiny/data.vbt A src/mainboard/lenovo/m900_tiny/devicetree.cb A src/mainboard/lenovo/m900_tiny/dsdt.asl A src/mainboard/lenovo/m900_tiny/gma-mainboard.ads A src/mainboard/lenovo/m900_tiny/gpio.c A src/mainboard/lenovo/m900_tiny/gpio_early.c A src/mainboard/lenovo/m900_tiny/hda_verb.c A src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h A src/mainboard/lenovo/m900_tiny/ramstage.c A src/mainboard/lenovo/m900_tiny/romstage.c 19 files changed, 854 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig new file mode 100644 index 0000000..ffcf058 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_THINKCENTRE_M900_TINY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SUPERIO_NUVOTON_NCT6687D + +config UART_FOR_CONSOLE + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + +config MAINBOARD_DIR + default "lenovo/m900_tiny" + +config MAINBOARD_PART_NUMBER + default "ThinkCentre M700 / M900 Tiny" + +config PRERAM_CBMEM_CONSOLE_SIZE + default 0xd00 + +config DIMM_SPD_SIZE + default 512 #DDR4 + +# TODO: fix and enable +config DRIVER_LENOVO_SERIALS + default n + +endif diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig.name b/src/mainboard/lenovo/m900_tiny/Kconfig.name new file mode 100644 index 0000000..6727a9c --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_THINKCENTRE_M900_TINY + bool "ThinkCentre M700 / M900 Tiny" diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk new file mode 100644 index 0000000..44db091 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/m900_tiny/acpi/ec.asl b/src/mainboard/lenovo/m900_tiny/acpi/ec.asl new file mode 100644 index 0000000..479296c --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/acpi/ec.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ + +/* dummy */ diff --git a/src/mainboard/lenovo/m900_tiny/acpi/superio.asl b/src/mainboard/lenovo/m900_tiny/acpi/superio.asl new file mode 100644 index 0000000..13623c5 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/acpi/superio.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6687D_SHOW_SP1 +#define NCT6687D_SHOW_EC + +#include <superio/nuvoton/nct6687d/acpi/superio.asl> diff --git a/src/mainboard/lenovo/m900_tiny/board_info.txt b/src/mainboard/lenovo/m900_tiny/board_info.txt new file mode 100644 index 0000000..db7669c --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://psref.lenovo.com/Product/ThinkCentre_M900_Tiny +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/lenovo/m900_tiny/bootblock.c b/src/mainboard/lenovo/m900_tiny/bootblock.c new file mode 100644 index 0000000..ab5f402 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/bootblock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP1) +#define POWER_DEV PNP_DEV(0x2e, NCT6687D_SLEEP_PWR) + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); + + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x13, 0x0c); + pnp_write_config(SERIAL_DEV, 0x1d, 0x08); + pnp_write_config(SERIAL_DEV, 0x1f, 0xf0); + pnp_write_config(SERIAL_DEV, 0x22, 0xbc); + pnp_write_config(SERIAL_DEV, 0x23, 0xdf); + pnp_write_config(SERIAL_DEV, 0x24, 0x81); + pnp_write_config(SERIAL_DEV, 0x25, 0xff); + pnp_write_config(SERIAL_DEV, 0x29, 0x6d); + pnp_write_config(SERIAL_DEV, 0x2a, 0x8f); + + /* Configure pin for PECI */ + pnp_set_logical_device(POWER_DEV); + pnp_write_config(POWER_DEV, 0xf3, 0x0c); + + nuvoton_pnp_exit_conf_state(POWER_DEV); + + /* Enable serial */ + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/m900_tiny/cmos.default b/src/mainboard/lenovo/m900_tiny/cmos.default new file mode 100644 index 0000000..84236aa --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/lenovo/m900_tiny/cmos.layout b/src/mainboard/lenovo/m900_tiny/cmos.layout new file mode 100644 index 0000000..322fa7d --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/cmos.layout @@ -0,0 +1,60 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: cpu +400 1 e 1 hyper_threading + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: ME +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/lenovo/m900_tiny/data.vbt b/src/mainboard/lenovo/m900_tiny/data.vbt new file mode 100644 index 0000000..7e6fe3d --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb new file mode 100644 index 0000000..e9f15d6 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -0,0 +1,223 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + # Enable deep Sx states + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # PL2 override 65W + register "power_limits_config" = "{ + .tdp_pl2_override = 65, + }" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART + }" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 11A | 66A | 48A | 48A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 3.9 | 2.1 | 3.1 | 3.1 | + #| DcLoadline | 3.9 | 2.1 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(11), + .voltage_limit = 1520, + .ac_loadline = 390, + .dc_loadline = 390, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(66), + .voltage_limit = 1520, + .ac_loadline = 210, + .dc_loadline = 210, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(48), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(48), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x17aa 0x30d0 inherit + device ref igpu on + register "PrimaryDisplay" = "Display_iGFX" + end + device ref sa_thermal on end + device ref gmm on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // Front Port 1 + [1] = USB2_PORT_MID(OC0), // Front Port 2 + [2] = USB2_PORT_MID(OC1), // Rear Port 3 + [3] = USB2_PORT_MID(OC2), // Rear Port 4 + [4] = USB2_PORT_MID(OC3), // Rear Port 5 + [5] = USB2_PORT_MID(OC4), // Rear Port 6 + [6] = USB2_PORT_MID(OC1), // Internal header + [8] = USB2_PORT_SHORT(OC_SKIP), // M.2 2230 + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Front Port 1 + [1] = USB3_PORT_DEFAULT(OC0), // Front Port 2 + [2] = USB3_PORT_DEFAULT(OC3), // Rear Port 3 + [3] = USB3_PORT_DEFAULT(OC3), // Rear Port 4 + [4] = USB3_PORT_DEFAULT(OC1), // Rear Port 5 + [5] = USB3_PORT_DEFAULT(OC1), // Rear Port 6 + }" + end + device ref thermal on end + device ref heci1 on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + }" + register "SataPortsHotPlug" = "{ + [0] = 1, + [1] = 1, + }" + end + device ref pcie_rp17 on # M.2 2280 / 2242 - SSD + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "1" + register "PcieRpAdvancedErrorReporting[16]" = "1" + register "PcieRpLtrEnable[16]" = "1" + register "PcieRpClkSrcNumber[16]" = "7" + register "PcieRpHotPlug[16]" = "1" + end + device ref pcie_rp7 on # M.2 2230 - WLAN + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "11" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "1" + register "PcieRpHotPlug[6]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_PCI_EXP" + device generic 0 on end + end + end + device ref lpc_espi on + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/nuvoton/nct6687d + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 - optional module + io 0x60 = 0x3f8 + irq 0x70 = 3 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO0-7 + device pnp 2e.8 off end # P80 UART + device pnp 2e.9 off end # GPIO8-9, GPIO1-8 AF + device pnp 2e.a on # ACPI + io 0x60 = 0xa10 + end + device pnp 2e.b on # EC + io 0x60 = 0xa20 + end + device pnp 2e.c off end # RTC + device pnp 2e.d off end # Deep Sleep + device pnp 2e.e on # TACH/PWM assignment + irq 0xe4 = 0x10 + irq 0xe5 = 0x09 + end + device pnp 2e.f off end # Function register + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref hda on end + device ref smbus on end + device ref gbe on end + end +end diff --git a/src/mainboard/lenovo/m900_tiny/dsdt.asl b/src/mainboard/lenovo/m900_tiny/dsdt.asl new file mode 100644 index 0000000..4a91cd5 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/m900_tiny/gma-mainboard.ads b/src/mainboard/lenovo/m900_tiny/gma-mainboard.ads new file mode 100644 index 0000000..fc6b6dd --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/gma-mainboard.ads @@ -0,0 +1,20 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + -- Two onboard DP++, one header for optional DP, HDMI or VGA port + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c new file mode 100644 index 0000000..65c9cbf --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/gpio.c @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_NC(GPP_A16, NONE), + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + PAD_NC(GPP_A18, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_A19, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_A23, 1, PLTRST), + + /* ------- GPIO Group GPP_B ------- */ + + PAD_CFG_GPO(GPP_B0, 0, DEEP), + PAD_CFG_GPO(GPP_B1, 0, DEEP), + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_B5, NONE), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B22, 0, PLTRST), + PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C5, NONE, PLTRST, NF1), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_C14, NONE), + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_C22, NONE), + PAD_CFG_GPO(GPP_C23, 0, PLTRST), + + /* ------- GPIO Group GPP_D ------- */ + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + PAD_CFG_GPO(GPP_D10, 1, PLTRST), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_F ------- */ + + PAD_NC(GPP_F0, NONE), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, RSMRST, OFF, ACPI), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_APIC_HIGH(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_CFG_NF(GPP_G8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G11, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_G18, 0, PLTRST), + PAD_CFG_GPI_SCI(GPP_G19, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPP_G20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_H10, NONE), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + + PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PWROK, OFF, ACPI), + PAD_CFG_NF(GPD2, DN_20K, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_GPI_SMI(GPP_I3, NONE, PLTRST, EDGE_SINGLE, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/m900_tiny/gpio_early.c b/src/mainboard/lenovo/m900_tiny/gpio_early.c new file mode 100644 index 0000000..0f46cda --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Early pad configuration */ +static const struct pad_config uart_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ +}; + +void mainboard_configure_early_gpios(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(uart_gpio_table, ARRAY_SIZE(uart_gpio_table)); +} diff --git a/src/mainboard/lenovo/m900_tiny/hda_verb.c b/src/mainboard/lenovo/m900_tiny/hda_verb.c new file mode 100644 index 0000000..b545df4 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0233, /* Codec Vendor / Device ID: Realtek ALC233 */ + 0x17aa30d0, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x17aa30d0), + AZALIA_PIN_CFG(1, 0x12, 0x40000000), + AZALIA_PIN_CFG(1, 0x14, 0x90170110), + AZALIA_PIN_CFG(1, 0x17, 0x411111f0), + AZALIA_PIN_CFG(1, 0x18, 0x411111f0), + AZALIA_PIN_CFG(1, 0x19, 0x02a11030), + AZALIA_PIN_CFG(1, 0x1a, 0x02a11040), + AZALIA_PIN_CFG(1, 0x1b, 0x01011020), + AZALIA_PIN_CFG(1, 0x1d, 0x40400001), + AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(1, 0x21, 0x0221101f), + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h b/src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c new file mode 100644 index 0000000..47add6f --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <gpio.h> +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> + +static void print_board_id(void) +{ + gpio_t id_gpios[] = { + GPP_G14, + GPP_G13, + GPP_G12, + }; + + printk(BIOS_INFO, "Board ID: "); + + switch (gpio_base2_value(id_gpios, ARRAY_SIZE(id_gpios))) { + case 0: + printk(BIOS_INFO, "ThinkCentre M900 Tiny\n"); + break; + case 2: + case 3: + case 4: + printk(BIOS_INFO, "ThinkCentre M700 Tiny\n"); + break; + default: + printk(BIOS_INFO, "Unknown!\n"); + break; + } + + printk(BIOS_INFO, "Serial header %spopulated\n", !gpio_get(GPP_A22) ? "" : "un"); + + printk(BIOS_INFO, "PS/2 header %spopulated\n", !gpio_get(GPP_D14) ? "" : "un"); + + printk(BIOS_INFO, "USB header %spopulated\n", !gpio_get(GPP_C19) ? "" : "un"); + + printk(BIOS_INFO, "DisplayPort header %spopulated\n", !gpio_get(GPP_B15) ? "" : "un"); + + printk(BIOS_INFO, "PCIe / SATA header %spopulated\n", !gpio_get(GPP_B21) ? "" : "un"); +} + +static void mainboard_enable(struct device *dev) +{ + mainboard_configure_gpios(); + print_board_id(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/m900_tiny/romstage.c b/src/mainboard/lenovo/m900_tiny/romstage.c new file mode 100644 index 0000000..9dfbfe2 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <stdint.h> +#include <string.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = { 121, 75, 100 }; + + const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Gerrit-Change-Number: 80610 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
by Felix Singer (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Alexander Couzens, Arthur Heymans, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Nicholas Sudsgaard, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80610?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake) ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/mainboard/lenovo/m900_tiny/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80610/comment/2e09a8d6_61b922fa : PS7, Line 192: #register "gen4_dec" = "0x000c0081" > Yes, I got these from vendor firmware and kept them for reference, I can remove them, it's no proble […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Gerrit-Change-Number: 80610 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 29 Feb 2024 09:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Patrick Rudolph (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Nico Huber, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Tested on IBM/SBP1. Boots to ubuntu 22.04 using `pci_domain_fill_ssdt` -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 09:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Jamie Chen (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Eric Lai, Ivan Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80769?usp=email ) Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > OK~I know,thanks. @matt.devillier@gmail.com https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 08:38:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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