coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: device/pci_ids: Rename Meteor Lake Intel Touch Controller PCI IDs
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85644?usp=email ) Change subject: device/pci_ids: Rename Meteor Lake Intel Touch Controller PCI IDs ...................................................................... Patch Set 2: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/85644/comment/43c52637_97382b92?us… : PS1, Line 4948: #define PCI_DID_INTEL_MTL_THC0_INTEL 0x7e48 : #define PCI_DID_INTEL_MTL_THC0_SPI 0x7e49 : #define PCI_DID_INTEL_MTL_THC1_INTEL 0x7e4a : #define PCI_DID_INTEL_MTL_THC1_SPI 0x7e4b > can you please split this CL into two ? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6 Gerrit-Change-Number: 85644 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 19:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Jérémy Compostella has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85814?usp=email ) Change subject: device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs ...................................................................... device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs The IDs comes from document #815002 Panther Lake External Design Specification volume 1. Change-Id: I23927631b165ded552860acf44dc8b67d41951c7 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85814/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23927631b165ded552860acf44dc8b67d41951c7 Gerrit-Change-Number: 85814 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85814?usp=email ) Change subject: device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs ...................................................................... device/pci_ids: Add Panther Lake Intel Touch Controller PCI IDs The IDs comes from document #815002 Panther Lake External Design Specification vol. 1 Change-Id: I23927631b165ded552860acf44dc8b67d41951c7 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85814/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 553d855..4279588 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4949,6 +4949,14 @@ #define PCI_DID_INTEL_MTL_THC0_SPI 0x7e49 #define PCI_DID_INTEL_MTL_THC1_INTEL 0x7e4a #define PCI_DID_INTEL_MTL_THC1_SPI 0x7e4b +#define PCI_DID_INTEL_PTL_U_H_THC0_I2C 0xe348 +#define PCI_DID_INTEL_PTL_U_H_THC0_SPI 0xe349 +#define PCI_DID_INTEL_PTL_U_H_THC1_I2C 0xe34a +#define PCI_DID_INTEL_PTL_U_H_THC1_SPI 0xe34b +#define PCI_DID_INTEL_PTL_H_THC0_I2C 0xe448 +#define PCI_DID_INTEL_PTL_H_THC0_SPI 0xe449 +#define PCI_DID_INTEL_PTL_H_THC1_I2C 0xe44a +#define PCI_DID_INTEL_PTL_H_THC1_SPI 0xe44b #define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 -- To view, visit https://review.coreboot.org/c/coreboot/+/85814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23927631b165ded552860acf44dc8b67d41951c7 Gerrit-Change-Number: 85814 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: device/pci_ids: Rename Meteor Lake Intel Touch Controller PCI IDs
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jérémy Compostella. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85644?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pci_ids: Rename Meteor Lake Intel Touch Controller PCI IDs ...................................................................... device/pci_ids: Rename Meteor Lake Intel Touch Controller PCI IDs This commit renames the Meteor lake Touch Controller device IDs to include the supported bus/protocol for clarity. The IDs comes from document #640228 - Meteor Lake External Design Specification volume 1. Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85644/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6 Gerrit-Change-Number: 85644 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: drivers/intel/touch: Add Intel Touch Controller driver
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kyoung Il Kim, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#7) to the change originally created by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85198?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/touch: Add Intel Touch Controller driver ...................................................................... drivers/intel/touch: Add Intel Touch Controller driver THC is a hardware component that interfaces between a touch sensor and the system's SPI or I2C bus. This driver publishes data into the Secondary System Descriptor Table (SSDT). This driver generates the following ACPI objects: - Device Specific Method (_DSM) - Current Resource Settings (_CRS) - Power resource with Status (_STA), _ON, and _OFF methods - Device Specific Data (_DSD) for THC-I2C - Device Reset (_RST) for THC-SPI Template device configuration for the following supported devices: - Wacom: THC-SPI touchscreen only - Elan: both THC-SPI and THC-I2C touchscreen - Hynitron: THC-I2C touchpad only BUG=none Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf --- A src/drivers/intel/touch/Kconfig A src/drivers/intel/touch/Makefile.mk A src/drivers/intel/touch/chip.h A src/drivers/intel/touch/elan.h A src/drivers/intel/touch/hynitron.h A src/drivers/intel/touch/touch.c A src/drivers/intel/touch/wacom.h 7 files changed, 1,025 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85198/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf Gerrit-Change-Number: 85198 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Document #813032 Panther Lake H I/O RegistersLink Capabilities (LCAP) – Offset 4c does not provide much information on the encoding of the port number field (see extract below). > **Port Number (PN)** > Indicates the port number for the root port. This value is different for each implemented port: > Port # Value of PN field > 1 01h > 2 02h > 3 03h > > > > X 0Xh > > **Note**: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly. The final note provides a clue to why it may start with a shift. I determined the value of 0x15 through empirical experiments and verified its consistency across different Panther Lake SKUs. I could not find the specification of the TBT Link Capabilities register for Meteor Lake, but according to [81841 soc/intel/mtl: Fixed TBT PCIe devtree remapping](https://review.coreboot.org/c/coreboot/+/81841), port numbers start at 0x10 on Meteor Lake. I added some information to the commit message. The fact that we used a non-specified value on Meteor Lake, in my opinion, is an endorsement to submit this CL. However, I would like to know if there is a way to determine this value through a hardware specification and, in particular, for the following SoC generations. -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 18:26:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Jérémy Compostella (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85781?usp=email to look at the new patch set (#2). Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 On Panther Lake, the Thunderbolt port index exposed by the LCAP registers begins at 0x15. The previous offset of 0x10 caused an issue that resulted in: - Temporary deactivation of Thunderbolt PCI devices during ramstage - Failure to generate critical ACPI SSDT power management data for the port This error led to instability in PCIe tunneling during power state transitions. The offset of 0x15 in Thunderbolt port number was determined through empirical experiments and verified across different SKUs. Document Panther Lake H I/O Registers (#813032) - Link Capabilities (LCAP) - Offset 4c does not provide such information. However, it indicates that the encoding of this register will be scaled according to the number of root ports supported by the platform. Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/emulation/spike-riscv: Define default DRAM_SIZE to avoid crash
by Maximilian Brune (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Joel Bueno, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change by Joel Bueno. ( https://review.coreboot.org/c/coreboot/+/85800?usp=email ) Change subject: mb/emulation/spike-riscv: Define default DRAM_SIZE to avoid crash ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85800/comment/0555af95_b87deb8f?us… : PS3, Line 16: his does not happen on qemu because, for that target, we parse the : FDT instead of manually probing memory. I am not really familiar with spike, but I guess we can also parse an FDT from SPIKE? It would like avoid probing ram if I can. https://review.coreboot.org/c/coreboot/+/85800/comment/43f21bd9_d38a9eb1?us… : PS3, Line 19: TEST=boot verified on SPIKE-RISCV Could you also add the cmdline of spike that you tested with? (makes it easier to reproduce). -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 3 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 18:14:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: arch/x86/mmu: Port armv8 MMU to x86_64
by Julius Werner (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Christian Walter, Felix Held, Patrick Rudolph, Subrata Banik. Julius Werner has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79161?usp=email ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79161/comment/78b9db9e_4568d537?us… : PS11, Line 16: DRAM and MMIO even beyond 4GiB. > On SPR I need to access a BAR in high MMIO at `0x200ffff90000`. That would increase pt1G. […] They have a BAR at 8 terrabytes in the linear address space!? And you can't modify that to be anywhere more reasonable? Wow... `0x2000'0000'0000` would actually be a different PML4 than the start of memory (each PML4 goes up to `0x7f'ffff'ffff`, and pt1G currently only adds the first one). So we don't need to add page directories for the entire space between `0` and `0x2000'0000'0000`, we just need to add them for those two PML4s. So we just need to come up with a clever Kconfig scheme to have the assembly output exactly the PML4s that you need. Maybe something like this could work: ``` .global PML4 .align 4096 PML4: .quad _GEN_DIR(PDPT0) .ifne CONFIG_PML4_1 .zero (CONFIG_PML4_1 - 1) * 8 .quad _GEN_DIR(PDPT1) .ifne CONFIG_PML4_2 .zero (CONFIG_PML4_2 - CONFIG_PML4_1 - 1) * 8 .quad _GEN_DIR(PDPT2) .ifne CONFIG_PML4_3 .zero (CONFIG_PML4_3 - CONFIG_PML4_2 - 1) * 8 .quad _GEN_DIR(PDPT3) .endif .endif .endif .zero PML4 + 4096 - . PDPT0: .rept 512 .quad _GEN_PAGE(0x40000000 * ((. - PDPT0) >> 3)) .ifne CONFIG_PML4_1 PDPT1: .rept 512 .quad _GEN_PAGE(CONFIG_PML4_1 << 39 + 0x40000000 * ((. - PDPT1) >> 3)) .ifne CONFIG_PML4_2 PDPT2: .rept 512 .quad _GEN_PAGE(CONFIG_PML4_2 << 39 + 0x40000000 * ((. - PDPT2) >> 3)) .ifne CONFIG_PML4_3 PDPT3: .rept 512 .quad _GEN_PAGE(CONFIG_PML4_3 << 39 + 0x40000000 * ((. - PDPT3) >> 3)) .endif .endif .endif ``` That should give you the ability to designate 3 (can be expanded as needed) PML4s that should be mapped for all your crazy high BAR needs, while only adding 4K (uncompressed) per PML4 you actually use to your ramstage .rodata. -- To view, visit https://review.coreboot.org/c/coreboot/+/79161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 79161 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Dec 2024 17:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: ec/google/chromeec/acpi: Add support for generic LPC memory range
by Kapil Porwal (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85811?usp=email ) Change subject: ec/google/chromeec/acpi: Add support for generic LPC memory range ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85811?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7 Gerrit-Change-Number: 85811 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 17:40:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024