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Change subject: soc/intel/cannonlake,skylake: Fix locking SMRAM
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
are other cpu generations affected too?
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Change subject: sconfig: Move config_of_soc from device.h to static.h
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
i like where this is going
only semi-related to this patch and more something for when all patches from this patch topic have landed, but it would make things a bit clearer when static.[c,h] would get renamed to static_devicetree.[c,h] to clarify that those are autogenerated from the devicetree files
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Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
......................................................................
drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
Add AOLD Method, which simply returns an integer based
on whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`, and add
second control in the USB ACPI `chip.h` which takes
precedence if used.
Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/usb/acpi/chip.h
M src/drivers/usb/acpi/usb_acpi.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
5 files changed, 85 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/84134/23
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Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
......................................................................
Patch Set 22:
(1 comment)
File src/drivers/usb/acpi/usb_acpi.c:
https://review.coreboot.org/c/coreboot/+/84134/comment/392d61b8_4883fb64?us… :
PS22, Line 247: Zero // Audio Offload Enabled
> Yup - add comment?
that works
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Change subject: arch/x86/bootblock.ld: Simplify the linker script
......................................................................
Patch Set 28:
(1 comment)
File src/arch/x86/bootblock.ld:
https://review.coreboot.org/c/coreboot/+/84045/comment/94587a6e_409594c9?us… :
PS27, Line 32: 0xfffff000
> The only thing I don't really like with this patch is that `0xfffff000` is used twice as a value whi […]
Done
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Change subject: arch/x86/bootblock.ld: Simplify the linker script
......................................................................
arch/x86/bootblock.ld: Simplify the linker script
To avoid complex arithmetic operations that optimize for a few bytes,
most sections in the linker script are now hardcoded. This
simplification may slightly increase the program size.
The primary motivation for this change is to accommodate clang LTO,
which requires LLD. LLD does not support the arithmetic operations used
to align code at the top in the original linker script.
TESTED: GCC and clang continue to function correctly with qemu.
Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/bootblock.ld
1 file changed, 28 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/84045/29
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Change subject: soc/mt6366: Workaround GCC LTO build issue
......................................................................
soc/mt6366: Workaround GCC LTO build issue
GCC incorrectly handles __builtin_constant_p() in LTO builds, leading to
false positives in switch-case functions where certain cases should
never be reached. To mitigate this, the feature is disabled temporarily
due to the greater impact of false positives on developers.
Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e
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---
M src/include/assert.h
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/84208/10
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Change subject: payloads/edk2: configure capsule updates
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
Patchset:
PS6:
I don't think we should have build options that aren't upstreamed in coreboot, especially as we have EDK2_CUSTOM_BUILD_PARAMSd.
Matt's branch is the exception as it's has been the default in coreboot for ages.
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Change subject: soc/intel/alderlake: Hook up PCIe Power Management to option API
......................................................................
soc/intel/alderlake: Hook up PCIe Power Management to option API
Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the
option API.
This provides users an easy way to disable power saving options
that can limit performance.
Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956
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---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81906/11
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