coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

1 participants
2622 discussions

[M] Change in coreboot[main]: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84134?usp=email ) Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth ...................................................................... Patch Set 22: (1 comment) File src/drivers/usb/acpi/usb_acpi.c: https://review.coreboot.org/c/coreboot/+/84134/comment/5b835963_884115ac?us… : PS22, Line 247: Zero // Audio Offload Enabled > assume is this 0 = disabled, 1 = enabled? Yup - add comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/84134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Gerrit-Change-Number: 84134 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 18:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[L] Change in coreboot[main]: soc/amd/glinda: ACPI support for dgpu prime funtionality
by Ana Carolina Cabral (Code Review) 02 Oct '24

02 Oct '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84644?usp=email ) Change subject: soc/amd/glinda: ACPI support for dgpu prime funtionality ...................................................................... soc/amd/glinda: ACPI support for dgpu prime funtionality Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Change-Id: Ib2351f819e175f9a939547bead7d651fd3084643 --- A src/soc/amd/glinda/acpi/dgpu_boco.asl M src/soc/amd/glinda/acpi/globalnvs.asl M src/soc/amd/glinda/acpi/soc.asl M src/soc/amd/glinda/include/soc/nvs.h 4 files changed, 584 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84644/1 diff --git a/src/soc/amd/glinda/acpi/dgpu_boco.asl b/src/soc/amd/glinda/acpi/dgpu_boco.asl new file mode 100644 index 0000000..e481887 --- /dev/null +++ b/src/soc/amd/glinda/acpi/dgpu_boco.asl @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + Scope (PCI0) + { + Device (PBR0) + { + Name (_ADR, 0x0000000000010001) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_DSD, Package () { + ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), + Package () { + Package () {"HotPlugSupportInD3", 1} + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) + { + Return (Package (0x04) + { + Package (0x04) + { + 0x0000FFFF, + 0x00, + 0x00, + 0x00000018 + }, + + Package (0x04) + { + 0x0000FFFF, + 0x01, + 0x00, + 0x00000019 + }, + + Package (0x04) + { + 0x0000FFFF, + 0x02, + 0x00, + 0x0000001A + }, + + Package (0x04) + { + 0x0000FFFF, + 0x03, + 0x00, + 0x0000001B + } + }) + } + Else + { + Return (Package (0x04) + { + Package (0x04) + { + 0x0000FFFF, + 0x00, + \_SB.INTA, + 0x00000000 + }, + + Package (0x04) + { + 0x0000FFFF, + 0x01, + \_SB.INTB, + 0x00000000 + }, + + Package (0x04) + { + 0x0000FFFF, + 0x02, + \_SB.INTC, + 0x00000000 + }, + + Package (0x04) + { + 0x0000FFFF, + 0x03, + \_SB.INTD, + 0x00000000 + } + }) + } + } + OperationRegion (PCFG, PCI_Config, Zero, 0x0100) + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + PC04, 16, + Offset (0x18), + PC18, 32, + PC1C, 16, + Offset (0x20), + PC20, 32, + PC24, 32, + PC28, 32, + PC2C, 32, + Offset (0x54), + PC54, 32, + Offset (0x68), + PC68, 16, + PC6A, 16, + PC6C, 32, + PC70, 16, + PC72, 16 + } + } + } + + Scope (\_SB.PCI0.PBR0) + { + Mutex (EEBC, 0x00) + Method (GPWR, 1, NotSerialized) + { + Acquire (EEBC, 0xFFFF) + \_SB.PCI0.PBR0.PC70 &= 0xFFF7 + \_SB.PCI0.PBR0.PC72 |= 0x0008 + Local0 = \_SB.GTXS (0x8C) + If ((Arg0 == One) && (Local0 == 0 || \HOTD == 1)) + { + \_SB.CTXS (0x8C) + \_SB.STXS (0x8D) + Sleep (0x96) + \_SB.STXS (0x8C) + Sleep (0x64) + \_SB.PCI0.PBR0.PC68 &= 0xFFEF + Sleep (0x18) + \_SB.PCI0.PBR0.PC68 &= 0xFFDF + \_SB.PCI0.PBR0.PC68 |= 0x0020 + Local1 = 0x1388 + While ((Local1 > Zero)) + { + Local0 = \_SB.PCI0.PBR0.PC6A + Local0 &= 0x2800 + If ((Local0 == 0x2000)) + { + Break + } + + Stall (0x64) + Local1-- + } + + Local7 = \_SB.PCI0.PBR0.PC54 + \_SB.PCI0.PBR0.PC54 &= 0xFFFF7FFC + Sleep (One) + Local1 = 0x28 + While ((Local1 > Zero)) + { + Local0 = \_SB.PCI0.PBR0.SWUS.PC00 + If ((Local0 == 0x1002)) + { + Break + } + + Sleep (0x19) + Local1-- + } + + \_SB.PCI0.PBR0.SWUS.RSTR () + \_SB.PCI0.PBR0.SWUS.SWDS.RSTR () + \_SB.PCI0.PBR0.SWUS.SWDS.DGPU.RSTR () + Local7 &= 0xFFFF7FFF + \_SB.PCI0.PBR0.PC54 = Local7 + \HOTD = 1 + } + ElseIf ((Arg0 == Zero) && Local0 == 1) + { + \_SB.PCI0.PBR0.SWUS.SAVE () + \_SB.PCI0.PBR0.SWUS.SWDS.SAVE () + \_SB.PCI0.PBR0.SWUS.SWDS.DGPU.SAVE () + + Local1 = \_SB.PCI0.PBR0.SWUS.PC00 + Local0 = \_SB.PCI0.PBR0.PC54 + \_SB.PCI0.PBR0.PC54 &= 0xFFFF7FFC + Sleep (One) + /* check dgpu upstream bridge presence before accessing ctl register */ + If (Local1 == 0x1002) + { + \_SB.PCI0.PBR0.SWUS.LCTL &= 0xFFFC + } + Local0 &= 0xFFFF7FFF + \_SB.PCI0.PBR0.PC54 = Local0 + + \_SB.PCI0.PBR0.PC68 |= 0x0010 + Sleep (0x18) + \_SB.STXS (0x8C) + Sleep (Zero) + \_SB.CTXS (0x8D) + Sleep (0x14) + \_SB.PCI0.PBR0.PC70 &= 0xFFF7 + \_SB.PCI0.PBR0.PC72 |= 0x0008 + Local0 = \_SB.PCI0.PBR0.PC04 + Sleep (0x0A) + } + + Release (EEBC) + } + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + PRIC + }) + Name (_PR2, Package (0x01) // _PR2: Power Resources for D2 + { + PRIC + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + PRIC + }) + PowerResource (PRIC, 0x00, 0x0000) + { + Name (FLAG, One) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (FLAG) /* \_SB_.PCI0.PBR0.PRIC.FLAG */ + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + If ((FLAG == Zero)) + { + GPWR (One) + } + + FLAG = One + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + If ((FLAG == One)) + { + GPWR (Zero) + } + + FLAG = Zero + } + } + + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + Device (SWUS) + { + Name (_ADR, 0x0000000000000000) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + OperationRegion (PCFG, PCI_Config, Zero, 0x0100) + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x00), + PC00, 16, + PC02, 16, + PC04, 16, + Offset (0x18), + PC18, 8, + PC19, 8, + PC1A, 8, + PC1B, 8, + Offset (0x20), + PC20, 32, + PC24, 32, + PC28, 32, + PC2C, 32 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x68), + LCTL, 16 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x6A), + LSTA, 16 + } + + Name (SV04, Zero) + Name (SV18, Zero) + Name (SV19, Zero) + Name (SV1A, Zero) + Name (SV1B, Zero) + Name (SV20, Zero) + Name (SV24, Zero) + Name (SV28, Zero) + Name (SV2C, Zero) + Method (SAVE, 0, Serialized) + { + SV04 = PC04 /* \_SB_.PCI0.PBR0.SWUS.PC04 */ + SV18 = PC18 /* \_SB_.PCI0.PBR0.SWUS.PC18 */ + SV19 = PC19 /* \_SB_.PCI0.PBR0.SWUS.PC19 */ + SV1A = PC1A /* \_SB_.PCI0.PBR0.SWUS.PC1A */ + SV1B = PC1B /* \_SB_.PCI0.PBR0.SWUS.PC1B */ + SV20 = PC20 /* \_SB_.PCI0.PBR0.SWUS.PC20 */ + SV24 = PC24 /* \_SB_.PCI0.PBR0.SWUS.PC24 */ + SV28 = PC28 /* \_SB_.PCI0.PBR0.SWUS.PC28 */ + SV2C = PC2C /* \_SB_.PCI0.PBR0.SWUS.PC2C */ + } + + Method (RSTR, 0, Serialized) + { + PC04 = SV04 /* \_SB_.PCI0.PBR0.SWUS.SV04 */ + PC18 = SV18 /* \_SB_.PCI0.PBR0.SWUS.SV18 */ + PC19 = SV19 /* \_SB_.PCI0.PBR0.SWUS.SV19 */ + PC1A = SV1A /* \_SB_.PCI0.PBR0.SWUS.SV1A */ + PC1B = SV1B /* \_SB_.PCI0.PBR0.SWUS.SV1B */ + PC20 = SV20 /* \_SB_.PCI0.PBR0.SWUS.SV20 */ + PC24 = SV24 /* \_SB_.PCI0.PBR0.SWUS.SV24 */ + PC28 = SV28 /* \_SB_.PCI0.PBR0.SWUS.SV28 */ + PC2C = SV2C /* \_SB_.PCI0.PBR0.SWUS.SV2C */ + } + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + PRIC + }) + Name (_PR2, Package (0x01) // _PR2: Power Resources for D2 + { + PRIC + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + PRIC + }) + PowerResource (PRIC, 0x00, 0x0000) + { + Name (FLAG, One) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (FLAG) /* \_SB_.PCI0.PBR0.SWUS.PRIC.FLAG */ + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + FLAG = One + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + FLAG = Zero + } + } + + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + } + } + + Scope (\_SB.PCI0.PBR0.SWUS) + { + Device (SWDS) + { + Name (_ADR, 0x0000000000000000) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + OperationRegion (PCFG, PCI_Config, Zero, 0x0100) + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x00), + PC00, 16, + PC02, 16, + PC04, 16, + Offset (0x18), + PC18, 8, + PC19, 8, + PC1A, 8, + PC1B, 8, + Offset (0x20), + PC20, 32, + PC24, 32, + PC28, 32, + PC2C, 32 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x68), + LCTL, 16 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x6A), + LSTA, 16 + } + + Name (SV04, Zero) + Name (SV18, Zero) + Name (SV19, Zero) + Name (SV1A, Zero) + Name (SV1B, Zero) + Name (SV20, Zero) + Name (SV24, Zero) + Name (SV28, Zero) + Name (SV2C, Zero) + + Method (SAVE, 0, Serialized) + { + SV04 = PC04 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC04 */ + SV18 = PC18 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC18 */ + SV19 = PC19 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC19 */ + SV1A = PC1A /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC1A */ + SV1B = PC1B /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC1B */ + SV20 = PC20 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC20 */ + SV24 = PC24 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC24 */ + SV28 = PC28 /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC28 */ + SV2C = PC2C /* \_SB_.PCI0.PBR0.SWUS.SWDS.PC2C */ + } + + Method (RSTR, 0, Serialized) + { + PC04 = SV04 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV04 */ + PC18 = SV18 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV18 */ + PC19 = SV19 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV19 */ + PC1A = SV1A /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV1A */ + PC1B = SV1B /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV1B */ + PC20 = SV20 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV20 */ + PC24 = SV24 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV24 */ + PC28 = SV28 /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV28 */ + PC2C = SV2C /* \_SB_.PCI0.PBR0.SWUS.SWDS.SV2C */ + } + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + PRIC + }) + Name (_PR2, Package (0x01) // _PR2: Power Resources for D2 + { + PRIC + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + PRIC + }) + PowerResource (PRIC, 0x00, 0x0000) + { + Name (FLAG, One) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (FLAG) /* \_SB_.PCI0.PBR0.SWUS.SWDS.PRIC.FLAG */ + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + FLAG = One + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + FLAG = Zero + } + } + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + } + } + + Scope (\_SB.PCI0.PBR0.SWUS.SWDS) + { + Device (DGPU) + { + Name (_ADR, 0x0000000000000000) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + OperationRegion (PCFG, PCI_Config, Zero, 0x0100) + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x00), + PC00, 16, + PC02, 16, + PC04, 16, + Offset (0x10), + PC10, 32, + PC14, 32, + PC18, 32, + PC1C, 32, + PC20, 32, + PC24, 32 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x74), + LCTL, 16 + } + + Field (PCFG, AnyAcc, NoLock, Preserve) + { + Offset (0x76), + LSTA, 16 + } + + Name (SV04, Zero) + Name (SV10, Zero) + Name (SV14, Zero) + Name (SV18, Zero) + Name (SV1C, Zero) + Name (SV20, Zero) + Name (SV24, Zero) + Method (SAVE, 0, Serialized) + { + SV04 = PC04 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC04 */ + SV10 = PC10 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC10 */ + SV14 = PC14 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC14 */ + SV18 = PC18 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC18 */ + SV1C = PC1C /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC1C */ + SV20 = PC20 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC20 */ + SV24 = PC24 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.PC24 */ + } + + Method (RSTR, 0, Serialized) + { + PC04 = SV04 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV04 */ + PC10 = SV10 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV10 */ + PC14 = SV14 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV14 */ + PC18 = SV18 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV18 */ + PC1C = SV1C /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV1C */ + PC20 = SV20 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV20 */ + PC24 = SV24 /* \_SB_.PCI0.PBR0.SWUS.SWDS.DGPU.SV24 */ + } + } + } + + Scope (\_SB.PCI0.PBR0.SWUS.SWDS.DGPU) + { + Method (ATPX, 2, Serialized) + { + If ((Arg0 == Zero)) + { + Return (PX00 ()) + } + + If ((Arg0 == One)) + { + Return (PX01 ()) + } + + Return (Buffer (0x08) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........ + }) + } + + Method (PX00, 0, NotSerialized) + { + Return (Buffer (0x08) + { + 0x08, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + } + Method (PX01, 0, NotSerialized) + { + Return (Buffer (0x0A) + { + /* 0000 */ 0x0A, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x40, // ...@...@ + /* 0008 */ 0x00, 0x00 // .. + }) + } + } diff --git a/src/soc/amd/glinda/acpi/globalnvs.asl b/src/soc/amd/glinda/acpi/globalnvs.asl index 6a3d04e..b63314c 100644 --- a/src/soc/amd/glinda/acpi/globalnvs.asl +++ b/src/soc/amd/glinda/acpi/globalnvs.asl @@ -10,4 +10,5 @@ /* Miscellaneous */ PM1I, 64, // 0x00 - 0x07 - System Wake Source - PM1 Index GPEI, 64, // 0x08 - 0x0f - GPE Wake Source + HOTD, 8, // 0x20 - Hot Add detected } diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl index 5d1edb7..2bbee22 100644 --- a/src/soc/amd/glinda/acpi/soc.asl +++ b/src/soc/amd/glinda/acpi/soc.asl @@ -7,6 +7,11 @@ Scope(\_SB) { /* global utility methods expected within the \_SB scope */ + ROOT_BRIDGE(PCI0) + Scope(PCI0){ + #include "dgpu_boco.asl" + } + #include <arch/x86/acpi/globutil.asl> #include <soc/amd/common/acpi/gpio_bank_lib.asl> @@ -21,8 +26,6 @@ #include "spi.asl" - ROOT_BRIDGE(PCI0) - Scope(PCI0) { #include <soc/amd/common/acpi/lpc.asl> } /* End PCI0 scope */ diff --git a/src/soc/amd/glinda/include/soc/nvs.h b/src/soc/amd/glinda/include/soc/nvs.h index efe5dde..34282bd 100644 --- a/src/soc/amd/glinda/include/soc/nvs.h +++ b/src/soc/amd/glinda/include/soc/nvs.h @@ -15,6 +15,7 @@ /* Miscellaneous */ uint64_t pm1i; /* 0x00 - 0x07 - System Wake Source - PM1 Index */ uint64_t gpei; /* 0x08 - 0x0f - GPE Wake Source */ + uint8_t hotd; }; #endif /* AMD_GLINDA_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2351f819e175f9a939547bead7d651fd3084643 Gerrit-Change-Number: 84644 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

1 0

[M] Change in coreboot[main]: soc/amd/glinda: SPI DEV entries missing in coreboot and UEFI BIOS
by Ana Carolina Cabral (Code Review) 02 Oct '24

02 Oct '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84643?usp=email ) Change subject: soc/amd/glinda: SPI DEV entries missing in coreboot and UEFI BIOS ...................................................................... soc/amd/glinda: SPI DEV entries missing in coreboot and UEFI BIOS Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Change-Id: I2d9a2b54602ef963f4753a4b62211969151a9412 --- M src/soc/amd/glinda/acpi/soc.asl A src/soc/amd/glinda/acpi/spi.asl 2 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/84643/1 diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl index 964cad9..5d1edb7 100644 --- a/src/soc/amd/glinda/acpi/soc.asl +++ b/src/soc/amd/glinda/acpi/soc.asl @@ -19,6 +19,8 @@ #include "mmio.asl" + #include "spi.asl" + ROOT_BRIDGE(PCI0) Scope(PCI0) { diff --git a/src/soc/amd/glinda/acpi/spi.asl b/src/soc/amd/glinda/acpi/spi.asl new file mode 100644 index 0000000..f96fab8 --- /dev/null +++ b/src/soc/amd/glinda/acpi/spi.asl @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for Glinda */ + + + + Mutex (ASM1, 0) //Amd Spi1 Semaphore Mutex + Name (SVBF, Buffer (0x100) {0}) + CreateWordField(SVBF, 0x014, RG22) + CreateDWordField(SVBF, 0x018, SAR2) + +Device(SPI1) { // SPI controller + Name(_HID, "AMDI0062") + Name(_UID, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } // end of Method _STA + OperationRegion(SPIM, SystemMemory, 0xFEC10000, 0x100) // SPI Mmio Register + Field(SPIM, AnyAcc, NoLock, Preserve) { + Offset (0x1D), + ASCE,2, // AltSpiCsEn + Offset (0x22), + SSSC, 16, // SPIx22 SPI100 Speed Config + Offset (0xFC), + STRN,1, // Spi TuRN + , 2, + BOWS,1, //Bios OWnerShip + DOWS,1, //Driver OWnerShip + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed(ReadWrite, 0xFEC10000, 0x100) + }) // End of Name (RBUF + Return (RBUF) + } // End of Method _CRS + + Method(ASSC, 2, Serialized) //Amd Spi Semaphore Control Arg0:Request ID Arg1:Timeout in Micro Second + { + Acquire (ASM1, 0xFFFF) + Store (Arg1, Local0) //save timeout + Switch (ToInteger(Arg0)) + { + Case (3) //Driver Acquire Spi Bus + { + store (one, DOWS) + store (one, STRN) + while (LAnd(BOWS,STRN)) { + if (Arg1) { + stall (1) + Subtract (Local0, one, Local0) + if (LEqual(Local0, zero)) { Break } + } + } + //store (RAR2, SAR2) //TODO SPI_ENTRY + //store (zero,RAR2) //TODO SPI_ENTRY + store (2, ASCE) + store (SSSC, RG22) + } + Case (4) //Driver Release Spi Bus + { + store (RG22, SSSC) + store (zero, ASCE) + //store (SAR2, RAR2)//TODO SPI_ENTRY + store (one, Local0) + store (zero, DOWS) + } + } + Release (ASM1) + Return (Local0) + } + } // End Device SPI1 \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/84643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d9a2b54602ef963f4753a4b62211969151a9412 Gerrit-Change-Number: 84643 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

1 0

[L] Change in coreboot[main]: mb/amd/birman*: I2C slave detection fix
by Ana Carolina Cabral (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk. Hello Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84600?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amd/birman*: I2C slave detection fix ...................................................................... mb/amd/birman*: I2C slave detection fix Change-Id: I24d236c82e6ede2c2311eb1e76499e5a29766133 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman/early_gpio.c M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/birman_plus/early_gpio.c M src/mainboard/amd/birman_plus/gpio.c M src/mainboard/amd/birman_plus/mainboard.c 6 files changed, 87 insertions(+), 307 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84600/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24d236c82e6ede2c2311eb1e76499e5a29766133 Gerrit-Change-Number: 84600 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Jérémy Compostella (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Anil Kumar K, Ashish Kumar Mishra, Cliff Huang, Felix Held, Paul Menzel, Pranava Y N, Saurabh Mishra, Subrata Banik. Jérémy Compostella has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 200: (3 comments) File src/mainboard/google/fatcat/Kconfig: https://review.coreboot.org/c/coreboot/+/83419/comment/ef7911b7_c0c37af7?us… : PS199, Line 20: PMC_IPC_ACPI_INTERFACE > why are we dropping this now ? It got dropped on September 13 and I do not know the reason. Restoring. https://review.coreboot.org/c/coreboot/+/83419/comment/93cbb1af_3db98d96?us… : PS199, Line 23: SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 > why are we dropping this now ? It got dropped on September 13 and I do not know the reason. Restoring. https://review.coreboot.org/c/coreboot/+/83419/comment/ff389c64_575b32d1?us… : PS199, Line 106: config OVERRIDE_DEVICETREE : default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" > why are we dropping this now ? […] It got removed on September 18 and moved to the overrride patch which is only making sense as this is the point we are adding the first override. Restoring. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 200 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Oct 2024 18:28:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Jérémy Compostella (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Anil Kumar K, Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Pranava Y N, Saurabh Mishra, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#200) to the change originally created by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Pranava Y N, Code-Review-1 by Subrata Banik Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... mb/google/fatcat: Add Panther Lake SOC support - This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/dsdt.asl M src/mainboard/google/fatcat/mainboard.c M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h 5 files changed, 117 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/200 -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 200 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/9f2ce4ca_3c56ae48?us… : PS11, Line 683: efi_uintn_t logo, blt_size; : uint32_t logo_size; : : fsp_convert_bmp_to_gop_blt(&logo, &logo_size, : &supd->FspsConfig.BltBufferAddress, : &blt_size, : &supd->FspsConfig.LogoPixelHeight, : &supd->FspsConfig.LogoPixelWidth); > We already verified it with the FSP team and also verified it works a few weeks ago. **This is not a hack.** Most of those UPD are not necessary anymore and therefore do exist anymore. I'm glad that Intel FSP is able to fix the problem that we have highlighted during MTL (details: https://b.corp.google.com/issues/282362963#comment5). As you can see, we don't have a complete view of each code change in FSP between MTL and PTL. So I'll keep providing feedback on why the code looks different from MTL (please bear with me on this). My feedback is based on our experience with the previous program. According to the MTL code, we can't see the display without passing logoptr/logosize. That's why I wanted to use `BltBufferAddress` to make it more meaningful. -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 15 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 17:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Jérémy Compostella (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/b7961cc8_97e89f42?us… : PS11, Line 301: max_port = get_max_tcss_port(); : for (i = 0; i < max_port; i++) > can you please explain why this is "completely ridiculous" ? (ideally I would like to avoid making use of such a word while communicating to someone) I agree, negligible or insignificant is more appropriate. > Have you compared the assembly instruction between below codes (code 1 and code 2)? I did. I personally think that making wrong claims on gerrit is counter-productive, hurt people and the project, so I ran some quick numbers yesterday before I reply to you. I did not think you would need them so I did not share. 1. The `.text` section of romstage is about 18771 instruction long bytes long (not taking into account of course the unfold of the loops which obviously is what we should do when talking performance impact). 2. 3 instruction are added to `fill_fsps_tcss_params()` (And no there is no need to push anything on the stack). 3. `get_max_tcss_port()` is 2 instruction longs. Since this is one a time event, the cost is at much 5 / 18771 = 0.026% and of course this is a very high estimate the reality is likely way lower considering we are not taking into account loops, cost of IO of many instructions … A rule of thumb is usually to look a algorithms first when it comes to optimization. My point was I don't think the question of performance here should even been raised as it is more a question of code quality that we should look at. -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 15 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 17:16:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: acpi_gic: Add helper for platform gicc
by Arthur Heymans (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Angel Pons, Naresh Solanki, Paul Menzel, Tim Wawrzynczak. Arthur Heymans has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/79973?usp=email ) Change subject: acpi_gic: Add helper for platform gicc ...................................................................... Patch Set 3: (1 comment) File src/acpi/acpi_gic.c: https://review.coreboot.org/c/coreboot/+/79973/comment/55e7f531_adae7d03?us… : PS2, Line 37: platform_gicc(gicc); > Done Oh so it's the same for all the entries. maybe add functions like platform_get_gicd_base() that return the value? platform_get_gicd_base() is already used I see in that platform hook? The trbe_interrupt seems dependent on the entry? maybe add that to the path of the path.gicc_v3 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/79973?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2 Gerrit-Change-Number: 79973 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 17:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

1 0

[XS] Change in coreboot[main]: mb/google/byra/var/kinox: Add/update VBT files
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Matt DeVillier. Subrata Banik has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83996?usp=email ) Change subject: mb/google/byra/var/kinox: Add/update VBT files ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I don't feel strongly about where they live, just that they are included. Would be nice if that solution helped simplify things downstream for Google as well, so that they could directly contribute the VBTs rather than me having to add them after the fact. what I have shared previously "Looks like VBT is Intel's access control, released through their RDC portal. Adding VBT blobs to the coreboot repository could potentially violate the agreement between coreboot and other closed-source binary distributions." is what we're following Intel's binary distribution guidelines, which means we can't redistribute the VBT binary we download from their restricted kit and upload it to the coreboot repo. I'll discuss this further with the FSP leads and get back to you. But as it stands, I don't think Googlers can upload VBT files to the coreboot project. -- To view, visit https://review.coreboot.org/c/coreboot/+/83996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce Gerrit-Change-Number: 83996 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 16:43:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2024