January 2024 - coreboot-gerrit

[S] Change in coreboot[main]: soc/amd/common/data_fabric/domain: use unsigned long for resource index
by Paul Menzel (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80266?usp=email ) Change subject: soc/amd/common/data_fabric/domain: use unsigned long for resource index ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60ac0e30627001698565b7256421780f9a94bf65 Gerrit-Change-Number: 80266 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 17:19:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/common/block/noncar: Merge romstage into bootblock
by Paul Menzel (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Marvin Drees, Matt DeVillier, Raul Rangel. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64950?usp=email ) Change subject: soc/amd/common/block/noncar: Merge romstage into bootblock ...................................................................... Patch Set 29: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd5affdb7f40cbd3bd4e599c3a5cb79984fea68 Gerrit-Change-Number: 64950 Gerrit-PatchSet: 29 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 17:19:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
by Lean Sheng Tan (Code Review) Jan. 31, 2024

Jan. 31, 2024

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80092?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID ...................................................................... soc/intel/xeon_sp: Find VTD devices by PCI DEV ID Instead of manually crafting S:B:D:F numbers for every VTD device loop over the entire devicetree by PCI DEV IDs. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80092 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 10 insertions(+), 26 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index a9236a9..8fe21e8 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -4,6 +4,7 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> #include <cpu/x86/smm.h> #include <soc/soc_util.h> #include <soc/pci_devs.h> @@ -53,7 +54,6 @@ #if !defined(__SIMPLE_DEVICE__) union dpr_register txt_get_chipset_dpr(void) { - const IIO_UDS *hob = get_iio_uds(); union dpr_register dpr; struct device *dev = VTD_DEV(0); @@ -66,31 +66,15 @@ dpr.raw = pci_read_config32(dev, VTD_LTDPR); - /* Compare the LTDPR register on all iio stacks */ - for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - iio++; - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - if (ri->VtdBarAddress == 0) - continue; - uint8_t bus = ri->BusBase; - dev = VTD_DEV(bus); - - if (!dev) { - printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus); - dpr.raw = 0; - return dpr; - } - - union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; - if (dpr.raw != test_dpr.raw) { - printk(BIOS_ERR, "LTDPR not the same on all IIO's"); - dpr.raw = 0; - return dpr; - } + dev = NULL; + /* Look for VTD devices on all sockets */ + while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID, dev))) { + /* Compare the LTDPR register on all iio stacks */ + union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.raw != test_dpr.raw) { + printk(BIOS_ERR, "LTDPR not the same on all IIO's"); + dpr.raw = 0; + return dpr; } } return dpr; -- To view, visit https://review.coreboot.org/c/coreboot/+/80092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96 Gerrit-Change-Number: 80092 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach UBOX stacks
by Lean Sheng Tan (Code Review) Jan. 31, 2024

Jan. 31, 2024

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Attach UBOX stacks ...................................................................... soc/intel/xeon_sp: Attach UBOX stacks Attach UBOX stacks on newer generation Xeon-SP. In order to use PCI drivers for UBOX devices, locating UBOX devices by vendor and device IDs and replacing device access by specifying S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the PCI enumerator index all devices. Since there are no PCI BARs on the UBOX bus the PCI locator doesn't have to assign resources on those buses. Once all PCI devices on the UBOX stack can be located without knowing their UBOX bus number and PCI segment the Xeon-SP code can fully enable the multi PCI segment group support. Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID. Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80091 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c 5 files changed, 91 insertions(+), 13 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, but someone else must approve build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 144dba1..08d723b 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -92,7 +92,51 @@ .scan_bus = iio_pci_domain_scan_bus, }; -/* Attach IIO stack as domains */ +/* + * Used by UBOX stacks. Those contain multiple PCI host bridges, each having + * only one bus with UBOX devices. UBOX devices have no resources. + */ +static struct device_operations ubox_pcie_domain_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +/* + * On the first Xeon-SP generations there are no separate UBOX stacks, + * and the UBOX devices reside on the first and second IIO. Starting + * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. + */ +static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, + const unsigned int bus_base, const unsigned int bus_limit) +{ + union xeon_domain_path new_path = { + .domain_path = dp.domain_path + }; + + for (int i = bus_base; i <= bus_limit; i++) { + new_path.bus = i; + + struct device_path path = { + .type = DEVICE_PATH_DOMAIN, + .domain = { + .domain = new_path.domain_path, + }, + }; + struct device *const domain = alloc_dev(upstream, &path); + if (!domain) + die("%s: out of memory.\n", __func__); + + domain->ops = &ubox_pcie_domain_ops; + + struct bus *const bus = alloc_bus(domain); + bus->secondary = i; + bus->subordinate = bus->secondary; + bus->max_subordinate = bus->secondary; + } +} + +/* Attach stack as domains */ void attach_iio_stacks(struct device *dev) { const IIO_UDS *hob = get_iio_uds(); @@ -114,19 +158,19 @@ dn.stack = x; dn.bus = ri->BusBase; - if (!is_pcie_iio_stack_res(ri)) { - if (CONFIG(HAVE_IOAT_DOMAINS)) - soc_create_ioat_domains(dn, dev->upstream, ri); - continue; - } + if (is_ubox_stack_res(ri)) { + soc_create_ubox_domains(dn, dev->upstream, ri->BusBase, ri->BusLimit); + } else if (is_pcie_iio_stack_res(ri)) { + struct device_path path; + path.type = DEVICE_PATH_DOMAIN; + path.domain.domain = dn.domain_path; + struct device *iio_domain = alloc_dev(dev->upstream, &path); + if (iio_domain == NULL) + die("%s: out of memory.\n", __func__); - struct device_path path; - path.type = DEVICE_PATH_DOMAIN; - path.domain.domain = dn.domain_path; - struct device *iio_domain = alloc_dev(dev->upstream, &path); - if (iio_domain == NULL) - die("%s: out of memory.\n", __func__); - iio_domain->ops = &iio_pcie_domain_ops; + iio_domain->ops = &iio_pcie_domain_ops; + } else if (CONFIG(HAVE_IOAT_DOMAINS)) + soc_create_ioat_domains(dn, dev->upstream, ri); } } } diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 7a7e295..836cd0c 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -30,6 +30,11 @@ return res->Personality == TYPE_UBOX_IIO; } +bool is_ubox_stack_res(const STACK_RES *res) +{ + return res->Personality == TYPE_UBOX; +} + uint8_t get_stack_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index fb9b138..89cc501 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -24,6 +24,7 @@ void get_iiostack_info(struct iiostack_resource *info); bool is_pcie_iio_stack_res(const STACK_RES *res); +bool is_ubox_stack_res(const STACK_RES *res); void bios_done_msr(void *unused); #endif diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index a5db8fd..3e02999 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -59,6 +59,29 @@ return res->BusBase < res->BusLimit; } +bool is_ubox_stack_res(const STACK_RES *res) +{ + /* + * Unlike on later platforms there's no separate "UBOX" stack. + * + * The UBOX devices can always be found on the first bus on the stack IIO0 (CSTACK). + * This bus is also referred to as uncore bus 0 or B(30). + * It has at a fixed address the UBOX: + * B(30):8.0 8086:2014 + * B(30):8.1 8086:2015 + * B(30):8.2 8086:2016 + * + * The PCU devices can always be on the first bus of the stack IIO1 (PSTACK). + * This bus is also referred to as uncore bus 1 or B(31). + * It has at a fixed address the PCU: + * B(31):30.0 8086:2080 + * B(31):30.1 8086:2081 + * B(31):30.2 8086:2082 + */ + + return false; +} + uint8_t get_stack_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 9c1a691..fb87611 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -73,6 +73,11 @@ return res->Personality == TYPE_UBOX_IIO; } +bool is_ubox_stack_res(const STACK_RES *res) +{ + return res->Personality == TYPE_UBOX; +} + /* * Given a stack resource, figure out whether the corresponding stack has * CXL device. -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: vendorcode/eltan: Fix building without separate romstage
by Arthur Heymans (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Erik van den Bogaert, Frans Hendriks. Hello Erik van den Bogaert, Frans Hendriks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78933?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/eltan: Fix building without separate romstage ...................................................................... vendorcode/eltan: Fix building without separate romstage - Make sure build.h is there by adding it as a dependency for all stages - Specify the vboot key location - Remove obsolete CPU_MICROCODE_CBFS_LOC symbol from config Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ibb077f5a2ebcdbaff537d82564f5245e45009fc9 --- M configs/config.facebook_fbg1701.mboot_vboot M src/mainboard/facebook/fbg1701/Kconfig M src/vendorcode/eltan/security/mboot/Makefile.mk 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78933/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb077f5a2ebcdbaff537d82564f5245e45009fc9 Gerrit-Change-Number: 78933 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Makefile.inc: Also add -libs to bootblock when !SEPARATE_ROMSTAGE
by Arthur Heymans (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79575?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Makefile.inc: Also add -libs to bootblock when !SEPARATE_ROMSTAGE ...................................................................... Makefile.inc: Also add -libs to bootblock when !SEPARATE_ROMSTAGE Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357 --- M Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/79575/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357 Gerrit-Change-Number: 79575 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vendorcode/amd/opensil: Add CPP args to all stages
by Arthur Heymans (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Felix Held. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79576?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/amd/opensil: Add CPP args to all stages ...................................................................... vendorcode/amd/opensil: Add CPP args to all stages It does not hurt to do this and makes it possible to link romstage sources into bootblock. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8 --- M src/vendorcode/amd/opensil/genoa_poc/Makefile.mk 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79576/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8 Gerrit-Change-Number: 79576 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: lib: Move IP checksum to commonlib
by Hung-Te Lin (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Angel Pons, Jakub Czapiga, Julius Werner, Jérémy Compostella, Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80251?usp=email ) Change subject: lib: Move IP checksum to commonlib ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: ok for the arm/mtk related files. but you need to solve the conflict? -- To view, visit https://review.coreboot.org/c/coreboot/+/80251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Gerrit-Change-Number: 80251 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 16:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach UBOX stacks
by Patrick Rudolph (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email ) Change subject: soc/intel/xeon_sp: Attach UBOX stacks ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80091/comment/f7fb379c_c39bc93a : PS7, Line 7: Attach more stacks > Should this be more descriptive, like attach UBOX stacks? Done https://review.coreboot.org/c/coreboot/+/80091/comment/28e9f39f_b1ceaef5 : PS7, Line 10: attack > attach? Please dont attack the stacks :D Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 16:44:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach UBOX stacks
by Patrick Rudolph (Code Review) Jan. 31, 2024

Jan. 31, 2024

Attention is currently required from: Christian Walter, Johnny Lin, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80091?usp=email to look at the new patch set (#8). Change subject: soc/intel/xeon_sp: Attach UBOX stacks ...................................................................... soc/intel/xeon_sp: Attach UBOX stacks Attach UBOX stacks on newer generation Xeon-SP. In order to use PCI drivers for UBOX devices, locating UBOX devices by vendor and device IDs and replacing device access by specifying S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the PCI enumerator index all devices. Since there are no PCI BARs on the UBOX bus the PCI locator doesn't have to assign resources on those buses. Once all PCI devices on the UBOX stack can be located without knowing their UBOX bus number and PCI segment the Xeon-SP code can fully enable the multi PCI segment group support. Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID. Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c 5 files changed, 91 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80091/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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