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Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.4 support
Intel Firmware Support Package 2.4 specification brings some
significant changes compared to version 2.3 (cf. documents 736809 and
644852 respectively):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It supports 64-bits FSP:
- FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
- The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
A few notes:
- `PLATFORM_USES_FSP2_X86_32' is set to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.
- Similarly to what is done for silicon initialization, timestamps and
post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
M util/cbfstool/eventlog.c
12 files changed, 133 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/4
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Patch Set 14:
(1 comment)
File src/include/mtcl.h:
https://review.coreboot.org/c/coreboot/+/80170/comment/f0fa82fd_a3bbe939 :
PS8, Line 21: __packed
> I think I'll leave it as packed only because it's used to do a cast from an array. […]
Added a comment about the struct and how it's meant to be used, as well as why it's explicitly packed. Please reopen if you disagree.
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Add MTCL function to ACPI SSDT tables
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT for MediaTek WiFi chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets.
Change Summary:
* Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related
to MTCL
* Add write_mtcl_aml function to convert the byte data into the format
expected by the MTCL functionality in the Linux kernel.
* Add validate_mtcl function to validate that the byte data read in
from a file is in the expected format.
* Add write_mtcl_function function to read a binary file called
"wifi_mtcl".hex" from cbfs, then call validate_mtcl to verify that
it is in an expected format, and if so write the aml via acpigen
* Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order
to include MediaTek WiFi specific functionality
* Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and
enables including the specific ACPI function defined in SSDT
* Add config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on
DRIVERS_MTK_WIFI which enables configuring the file to add as
"wifi_mtcl.hex"
* Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c
to include the MTCL function in SSDT for MTK WiFi devices when
USE_MTCL is enabled.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.mk
M src/drivers/wifi/generic/acpi.c
A src/drivers/wifi/generic/mtcl.c
M src/include/device/pci_ids.h
A src/include/mtcl.h
6 files changed, 226 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/14
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Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> some more generic feedback,
>
> FSPM_ARCH2_UPD should need a EDK2 uprev. Please submit that as well as base CL.
>
> Until things are not in place, I suggest to mark this CL as WIP
`FSPM_ARCH2_UPD` and `FSPS_ARCH2_UPD` are already available in src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h.
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Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
Patch Set 3:
(6 comments)
Patchset:
PS3:
> quick feedback
> 1. This CL doesn't mentioned the test vehicle used to verify
Test vehicle is not public. Considering the 2.4 specification is public, we can provide the implementation.
> 2. specify the FSP 2.4 spec link
I gave the document number but I did not add the link as links can change.
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80275/comment/c9b78efb_ee6bc4c9 :
PS3, Line 58: default n if PLATFORM_USES_FSP2_4
> ideally this config can be only select if `depends on !PLATFORM_USES_FSP2_4`
2.4 also supports 32-bits.
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/80275/comment/a30afcba_e976d340 :
PS3, Line 32: void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index)
> nit: […]
The idea was to reuse the same hook. The risk is that if we have a converged romstage and ramstage image then this would break... I'll separate those.
https://review.coreboot.org/c/coreboot/+/80275/comment/bbbc2147_ff2092c6 :
PS3, Line 282: error_handler
> nit: […]
Considering we are in memory_init.c and this is static function I don't see the benefit of surcharging the function name with unnecessary prefix.
https://review.coreboot.org/c/coreboot/+/80275/comment/e5ed38f3_310e5125 :
PS3, Line 297: multi_phase_init
> nit: multi_phase_mem_init
Considering we are in memory_init.c and this is static function I don't see the benefit of surcharging the function name with unnecessary prefix.
https://review.coreboot.org/c/coreboot/+/80275/comment/6794e6f0_8d9fe00f :
PS3, Line 437: if (hdr->fsp_multi_phase_mem_init_entry_offset)
> why not like this ? […]
Wouldn't it be dangerous to look outside after the limit of the data structure ? These fields are added with 2.4.
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Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
Patch Set 3:
(7 comments)
Patchset:
PS3:
some more generic feedback,
FSPM_ARCH2_UPD should need a EDK2 uprev. Please submit that as well as base CL.
Until things are not in place, I suggest to mark this CL as WIP
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/80275/comment/2168fd69_3e20357e :
PS3, Line 32: void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index)
nit:
platform_fsp_multi_phase_mem_init_cb
https://review.coreboot.org/c/coreboot/+/80275/comment/01d3d332_2dba7f2e :
PS3, Line 282: error_handler
nit:
fsp_memory_init_error_handler
https://review.coreboot.org/c/coreboot/+/80275/comment/e9908f37_501195f9 :
PS3, Line 295:
: #if CONFIG(PLATFORM_USES_FSP2_4)
i don't believe u need this. we don't see this inside silicon_init.c
https://review.coreboot.org/c/coreboot/+/80275/comment/ff0cbc1d_e7f970df :
PS3, Line 297: multi_phase_init
nit: multi_phase_mem_init
https://review.coreboot.org/c/coreboot/+/80275/comment/42273947_dc46d6fb :
PS3, Line 437: if (hdr->fsp_multi_phase_mem_init_entry_offset)
why not like this ?
```
....
/* Implementing multi_phase_mem_init() is optional till < FSP 2.4 spec */
if (hdr->fsp_multi_phase_mem_init_entry_offset == NULL)
return;
multi_phase_mem_init(hdr);
....
```
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/80275/comment/d30e3cfe_533c148d :
PS3, Line 25: platform_fsp_multi_phase_init_cb
nit:
platform_fsp_multi_phase_si_init_cb
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Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
quick feedback
1. This CL doesn't mentioned the test vehicle used to verify
2. specify the FSP 2.4 spec link
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80275/comment/05ef0e81_1a274994 :
PS3, Line 58: default n if PLATFORM_USES_FSP2_4
ideally this config can be only select if `depends on !PLATFORM_USES_FSP2_4`
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Hello Andrey Petrov, Bora Guvendik, Ronak Kanabar, Wonkyu Kim,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.4 support
Intel Firmware Support Package 2.4 specification brings some
significant changes compared to version 2.3 (cf. documents 736809 and
644852 respectively):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It supports 64-bits FSP:
- FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
- The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
A few notes:
- `PLATFORM_USES_FSP2_X86_32' is set to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.
- Similarly to what is done for silicon initialization, timestamps and
post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M util/cbfstool/eventlog.c
8 files changed, 126 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/3
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Hello Andrey Petrov, Ronak Kanabar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80275?usp=email
to look at the new patch set (#2).
Change subject: drivers/intel/fsp2_0: Add FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.4 support
Intel Firmware Support Package 2.4 specification brings some
significant changes compared to version 2.3 (cf. documents 736809 and
644852 respectively):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It supports 64-bits FSP:
- FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
- The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
A few notes:
- `PLATFORM_USES_FSP2_X86_32' is set to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.
- Similarly to what is done for silicon initialization, timestamps and
post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M util/cbfstool/eventlog.c
8 files changed, 126 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/2
--
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Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Gerrit-Change-Number: 80275
Gerrit-PatchSet: 2
Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
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