coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Documentation: Bring back abuild documentation
by Martin L Roth (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Keith Hui, Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76775?usp=email ) Change subject: Documentation: Bring back abuild documentation ...................................................................... Patch Set 3: (7 comments) Patchset: PS3: Awesome write-up. Thanks! File Documentation/util/abuild/index.md: https://review.coreboot.org/c/coreboot/+/76775/comment/c025afdf_f388e776 : PS3, Line 4: This utility is a great tool to check whether your coreboot tree compiles for one or all targets. The documentation guidelines request that the text be wrapped at 72 characters. https://doc.coreboot.org/getting_started/writing_documentation.html#basic-a… Well, what it actually says is "Running text should have a visible width of about 72 chars." which is hard to do automatically, so I just recommend using a tool to wrap it at 72 characters. Personally, I think that's too short, but that's the current standard. https://review.coreboot.org/c/coreboot/+/76775/comment/b7bda734_591cccaf : PS3, Line 18: end up in the coreboot-builds/ Maybe "will by default end up in your current folder under the coreboot-builds directory." It's probably implied, and I'm the only one thinking this way. :) https://review.coreboot.org/c/coreboot/+/76775/comment/b8027e17_82ce5ca3 : PS3, Line 41: Extra whitespace https://review.coreboot.org/c/coreboot/+/76775/comment/81e5bf69_babc3a8e : PS3, Line 48: fully working image I'd be careful with this. While it's our stated goal for this to be true, it's unfortunately not true much of the time. This is only true if the default config is the booting config. Many platforms leave out pieces that need to be added to the build in one spot or another. https://review.coreboot.org/c/coreboot/+/76775/comment/b7c4bee9_40386bdf : PS3, Line 116: ### Build non-default configurations This might be a good spot to give the usage of the -K argument. If you created a file called "myconfig" with just the line: ``` # CONFIG_USE_NATIVE_RAMINIT is not set ``` and ran `abuild -K myconfig`, you'd get that setting applied to anything that abuild builds. https://review.coreboot.org/c/coreboot/+/76775/comment/9e553995_dcd465a3 : PS3, Line 190: Note that you must replace all hyphens in the variant name with underscores for this to : work. There is a [patch](https://review.coreboot.org/c/coreboot/+/41918) submitted that : attempts to correct this behaviour. I just gave this patch a +2. Sorry, I hadn't noticed it before. -- To view, visit https://review.coreboot.org/c/coreboot/+/76775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69701eaeef616828bc30736aba2f617e844a3148 Gerrit-Change-Number: 76775 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:42:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: doc/forums: Add a section for local groups and meetups
by Felix Singer (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: David Hendricks, Martin L Roth, Stefan Reinauer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76937?usp=email ) Change subject: doc/forums: Add a section for local groups and meetups ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi everyone. As discussed on the meeting on May 17th, I would like to add a section for local groups. I tried to make clear that these groups are not related to the project itself. Also, not sure if we want a table (or another format) for each entry. I decided for the simplest format since this way don't have problems with non-aligned columns. -- To view, visit https://review.coreboot.org/c/coreboot/+/76937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib814ce34b24cd199e5a0a623bffde4b7d93deff0 Gerrit-Change-Number: 76937 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:31:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
by Mike Banon (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Balázs Vinarz, Martin L Roth, Paul Menzel, Vlado Ilic, awokd(a)danwin1210.me. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76832?usp=email ) Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > I still have the Phoronix page on my browser, which mentioned the fact of the removal. […] Thank you ;-) Btw plenty of these git reverts could be avoided if the changes to the "dropped code" are allowed: i.e. instead of git reverting the four patches numbered 497-500 at the script above, one could simply add a single " #define SPEEDSTEP_APIC_MAGIC 0xACAC " somewhere. Therefore the real number of "bad commits" (which either remove our boards or break the things for us) isn't that great and the opensource AGESA boards really can be brought back to coreboot with a bunch of ifdef's etc. Please let me know if you're interested in such a quest PS1: Thank you ;-) Btw plenty of these git reverts could be avoided if the changes to the "dropped code" are allowed: i.e. instead of git reverting the four patches numbered 497-500 at the script above, one could simply add a single " #define SPEEDSTEP_APIC_MAGIC 0xACAC " somewhere. Therefore the real number of "bad commits" (which either remove our boards or break the things for us) isn't that great and the opensource AGESA boards really can be brought back to coreboot with a bunch of ifdef's etc. Please let me know if you're interested in such a quest -- To view, visit https://review.coreboot.org/c/coreboot/+/76832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4658dcaf4ff6fbac36070529284f2c982ed73c3 Gerrit-Change-Number: 76832 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Vlado Ilic <kakonema(a)gmail.com> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: awokd(a)danwin1210.me Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-Attention: Vlado Ilic <kakonema(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:27:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONS
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76685?usp=email ) Change subject: soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONS ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 10 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176449 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176447 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176446 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176445 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176444 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176443 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176442 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176441 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/176440 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176439 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/176438 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176437 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176436 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176435 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176434 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176433 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Gerrit-Change-Number: 76685 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:26:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: doc/forums: Add a section for local groups and meetups
by Felix Singer (Code Review) 03 Aug '23

03 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76937?usp=email ) Change subject: doc/forums: Add a section for local groups and meetups ...................................................................... doc/forums: Add a section for local groups and meetups Add a section for local groups which meet on a regular basis. Initially, add a local group meeting at CCC Darmstadt. Change-Id: Ib814ce34b24cd199e5a0a623bffde4b7d93deff0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/community/forums.md 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/76937/1 diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md index 14c108a..f3463c5 100644 --- a/Documentation/community/forums.md +++ b/Documentation/community/forums.md @@ -37,3 +37,16 @@ the document require a Google account to participate, although editing access to the document is limited to adding comments - any desired agenda item added that way will be approved in time before the meeting. + +## Local groups and meetups + +Local groups and meetups are not organized by the coreboot project but +by affiliated individuals from the community. These events take place on +a regular basis. + +Listings should include date, location and a contact. + +* [CCC Darmstadt](https://www.chaos-darmstadt.de) + * Bi-weekly on Monday in even weeks, 19:00 + * Location: Wilhelminenstr. 17, 64283 Darmstadt, Germany + * Contact: Felix Singer (flx) -- To view, visit https://review.coreboot.org/c/coreboot/+/76937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib814ce34b24cd199e5a0a623bffde4b7d93deff0 Gerrit-Change-Number: 76937 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: tint: upgrade the tint payload to 0.07 version
by Mike Banon (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Martin L Roth. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76820?usp=email ) Change subject: tint: upgrade the tint payload to 0.07 version ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Stefan, thank you so much for your +2 ! 😊 If you have a moment of free time, please take a look at this change's parent CB:76819 - it fixes the tint build system for the new buildgcc script versions and is required to build tint successfully -- To view, visit https://review.coreboot.org/c/coreboot/+/76820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f6de3d0410e6d838fe49330d98620c877a0d2c7 Gerrit-Change-Number: 76820 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:16:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
by Name of user not set (Code Review) 03 Aug '23

03 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \ ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) evaluates FALSE. According to Coverity, this could result in cases where RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment up a line so it gets initialized regardless. Tested on Lenovo G505s. Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1370599 --- M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c index 991667b..d21c246 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -504,8 +504,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index 1446f3e..7ea7c56 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -505,8 +505,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); -- To view, visit https://review.coreboot.org/c/coreboot/+/38495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Gerrit-Change-Number: 38495 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Mike Banon (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Iman Bingi, Martin L Roth, Patrick Rudolph. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76913?usp=email ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Martin, I'm sorry but your redirect link at the bottom of previous CB:23586 change links to itself instead of this CB:76913 (and I can't add a correct "redirect comment") -- To view, visit https://review.coreboot.org/c/coreboot/+/76913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533d247cd92341c3f91cc6927b875d6d2c460bd7 Gerrit-Change-Number: 76913 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:07:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONS
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76683?usp=email ) Change subject: soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONS ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 8 / 14 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176432 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176430 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176429 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176428 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176427 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176426 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176425 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176424 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176422 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176420 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176419 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176418 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176417 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176416 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Gerrit-Change-Number: 76683 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 22:04:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2023