Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76189?usp=email )
Change subject: mb/google/rex: Reduce camera NVM size to 8KB
......................................................................
mb/google/rex: Reduce camera NVM size to 8KB
The actual NVM size of camera module is 64KB; however, only 8KB is in
use to store data. This reduces the size of both NVM0 and NVM1 to 8KB
to minimize the time taken to read NVM and launch Camera preview.
BUG=NONE
TEST=Launch camera and check the time taken to read eeprom and show
camera preview. It takes 2 to 3 seconds to show camera preview while it
takes 4 to 5 seconds without the change.
Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/76189/1
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 4f74ea4..793a46d 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -535,10 +535,10 @@
register "nvm_compat" = ""atmel,24c64""
- register "nvm_size" = "0x10000"
+ register "nvm_size" = "0x2000"
register "nvm_pagesize" = "0x01"
register "nvm_readonly" = "0x01"
- register "nvm_width" = "0x0E"
+ register "nvm_width" = "0x10"
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
@@ -656,7 +656,7 @@
register "chip_name" = ""ST M24C64X""
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
- register "nvm_size" = "0x10000"
+ register "nvm_size" = "0x2000"
register "nvm_pagesize" = "1"
register "nvm_readonly" = "1"
register "nvm_width" = "0x10"
--
To view, visit https://review.coreboot.org/c/coreboot/+/76189?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Gerrit-Change-Number: 76189
Gerrit-PatchSet: 1
Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-MessageType: newchange
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76199?usp=email )
Change subject: nb/intel/haswell: Correct PCI bus range at runtime
......................................................................
nb/intel/haswell: Correct PCI bus range at runtime
ECAM_MMCONF_BUS_NUMBER defaults to 64 for Haswell, but the ASL code
sets the maximum of 256 buses. Patch the resource so that the actual
number as set in Kconfig is used.
Change-Id: I492c5a4336dcd0e7e4964f3f5e2bb53ffe05721f
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/northbridge/intel/haswell/acpi/hostbridge.asl
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/76199/1
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 513e960..22b8f1c 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -140,6 +140,12 @@
Method (_CRS, 0, Serialized)
{
+ /* Set highest PCI bus and length */
+ CreateWordField(MCRS, ^PB00._MAX, BMAX)
+ CreateWordField(MCRS, ^PB00._LEN, BLEN)
+ BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
+ BMAX = BLEN - 1
+
// Find PCI resource area in MCRS
CreateDwordField (MCRS, ^PM01._MIN, PMIN)
CreateDwordField (MCRS, ^PM01._MAX, PMAX)
--
To view, visit https://review.coreboot.org/c/coreboot/+/76199?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I492c5a4336dcd0e7e4964f3f5e2bb53ffe05721f
Gerrit-Change-Number: 76199
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange