coreboot-gerrit June 2023

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[M] Change in coreboot[master]: soc|vc/amd/phoenix: Prepare for PSP verstage
by Karthik Ramasubramanian (Code Review) 01 Jun '23

01 Jun '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75584?usp=email ) Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage ...................................................................... soc|vc/amd/phoenix: Prepare for PSP verstage Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/phoenix/psp_verstage/Makefile.inc M src/soc/amd/phoenix/psp_verstage/chipset.c M src/soc/amd/phoenix/psp_verstage/svc.c M src/soc/amd/phoenix/psp_verstage/svc.h A src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_errorcodes_public.h M src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h 6 files changed, 154 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75584/1 diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.inc b/src/soc/amd/phoenix/psp_verstage/Makefile.inc index 6ff447c..4ab7bfc 100644 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.inc +++ b/src/soc/amd/phoenix/psp_verstage/Makefile.inc @@ -1,10 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) subdirs-y += ../../common/psp_verstage -verstage-generic-ccopts += -I$(src)/soc/amd/phoenix/psp_verstage/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include diff --git a/src/soc/amd/phoenix/psp_verstage/chipset.c b/src/soc/amd/phoenix/psp_verstage/chipset.c index 3f3a7cf..acbd559 100644 --- a/src/soc/amd/phoenix/psp_verstage/chipset.c +++ b/src/soc/amd/phoenix/psp_verstage/chipset.c @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - +#include "2api.h" +#include <arch/hlt.h> +#include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> +#include <boot_device.h> #include <cbfs.h> #include <console/console.h> #include <psp_verstage.h> +#include <security/vboot/misc.h> +#include <security/vboot/vbnv.h> /* * We can't pass pointer to hash table in the SPI. @@ -20,7 +24,8 @@ void update_psp_fw_hash_table(const char *fname) { - uint8_t *spi_ptr = (uint8_t *)cbfs_map(fname, NULL); + void *hash_file = cbfs_map(fname, NULL); + uint8_t *spi_ptr = (uint8_t *)hash_file; uint32_t len; if (!spi_ptr) { @@ -39,6 +44,8 @@ printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); return; } @@ -47,6 +54,8 @@ printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); return; } @@ -62,6 +71,8 @@ memcpy(hash_384, spi_ptr, len); svc_set_fw_hash_table(&hash_table); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); } uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) @@ -94,16 +105,6 @@ return 0; } - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} - void platform_report_mode(int developer_mode_enabled) { printk(BIOS_INFO, "Reporting %s mode\n", @@ -113,3 +114,36 @@ else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); } + +void report_prev_boot_status_to_vboot(void) +{ + uint32_t boot_status = 0; + int ret; + struct vb2_context *ctx = vboot_get_context(); + + /* Already in recovery mode. No need to report previous boot status. */ + if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) + return; + + ret = svc_get_prev_boot_status(&boot_status); + if (ret != BL_OK || boot_status) { + printk(BIOS_ERR, "PSPFW failure in previous boot: %d:%#8x\n", ret, boot_status); + vbnv_init(); + vb2api_previous_boot_fail(ctx, VB2_RECOVERY_FW_VENDOR_BLOB, + boot_status ? (int)boot_status : ret); + } +} + +void report_hsp_secure_state(void) +{ + uint32_t hsp_secure_state; + int ret; + + ret = svc_get_hsp_secure_state(&hsp_secure_state); + if (ret != BL_OK) { + printk(BIOS_ERR, "Error reading HSP Secure state: %d\n", ret); + hlt(); + } + + printk(BIOS_INFO, "HSP Secure state: %#8x\n", hsp_secure_state); +} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.c b/src/soc/amd/phoenix/psp_verstage/svc.c index becfcb0..c88f759 100644 --- a/src/soc/amd/phoenix/psp_verstage/svc.c +++ b/src/soc/amd/phoenix/psp_verstage/svc.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #include "svc.h" #include <assert.h> @@ -217,3 +215,32 @@ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_FW_HASH_TABLE, (void *)&param, retval); return retval; } + +uint32_t svc_get_prev_boot_status(uint32_t *boot_status) +{ + uint32_t retval = 0; + struct cmd_param_get_prev_boot_status param = { + .ptr_boot_status = boot_status, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_PREV_BOOT_STATUS, (void *)&param, retval); + return retval; +} + +uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state) +{ + uint32_t retval = 0; + struct cmd_param_get_hsp_secure_state param; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_HSP_SECURE_STATE, (void *)&param, retval); + *hsp_secure_state = param.hsp_secure_state; + return retval; +} + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + struct cmd_param_postcode param = { + .postcode = postcode, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_WRITE_POSTCODE, (void *)&param, retval); + return retval; +} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.h b/src/soc/amd/phoenix/psp_verstage/svc.h index 3c59a1c..c3e6475 100644 --- a/src/soc/amd/phoenix/psp_verstage/svc.h +++ b/src/soc/amd/phoenix/psp_verstage/svc.h @@ -95,4 +95,16 @@ struct psp_fw_hash_table *ptr_psp_fw_hash_table; }; +struct cmd_param_get_prev_boot_status { + unsigned int *ptr_boot_status; +}; + +struct cmd_param_get_hsp_secure_state { + unsigned int hsp_secure_state; +}; + +struct cmd_param_postcode { + uint32_t postcode; +}; + #endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_errorcodes_public.h new file mode 100644 index 0000000..6c6fa4d --- /dev/null +++ b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_errorcodes_public.h @@ -0,0 +1,37 @@ +/***************************************************************************** + * + * Copyright (c) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef BL_ERRORCODES_PUBLIC_H +#define BL_ERRORCODES_PUBLIC_H + +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code + +#endif /* BL_ERRORCODES_PUBLIC_H */ diff --git a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h index 30ea49f..623762a 100644 --- a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h @@ -57,6 +57,9 @@ CMD_CCP_DMA, CMD_SET_PLATFORM_BOOT_MODE, CMD_SET_FW_HASH_TABLE, + CMD_GET_PREV_BOOT_STATUS, + CMD_GET_HSP_SECURE_STATE, + CMD_WRITE_POSTCODE, }; struct mod_exp_params { @@ -94,6 +97,7 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; @@ -105,6 +109,12 @@ FCH_I2C_CONTROLLER_ID_MAX, }; +enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + struct spirom_info { void *SpiBiosSysHubBase; void *SpiBiosSmnBase; @@ -371,6 +381,24 @@ */ uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table); +/* Get the previous boot status. + * + * Parameters: + * - boot_status - Address where the boot status is read into + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_prev_boot_status(uint32_t *boot_status); + +/* Get HSP Secure state + * + * Parameters: + * - hsp_secure_state - Address where the state info is read into + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/75584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Gerrit-Change-Number: 75584 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/myst: Add PCIe shutdown workaround
by Tim Van Patten (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Eric Lai, Jon Murphy, Karthik Ramasubramanian, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75583?usp=email ) Change subject: mb/google/myst: Add PCIe shutdown workaround ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/75583/comment/6869edfb_3c7a8633 : PS2, Line 56: .turn_off_unused_lanes = true, > This is a workaround and it's working. We have a bug to track getting it fixed. […] What are the differences between the two in terms of unintended side effects? My preference would be to make changes that are as specific as possible, to reduce introducing unrelated behavior changes that could take additional time to debug. -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 21:19:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/myst: Add PCIe shutdown workaround
by Jon Murphy (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75583?usp=email ) Change subject: mb/google/myst: Add PCIe shutdown workaround ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/75583/comment/0d4e6a07_848d79ca : PS2, Line 56: .turn_off_unused_lanes = true, > Can we toggle this to `false` instead, assuming that also fixes it? It seems like a more direct appr […] This is a workaround and it's working. We have a bug to track getting it fixed. I think this is fine as is. https://review.coreboot.org/c/coreboot/+/75583/comment/5b5a0b9f_56cbd4cd : PS2, Line 57: /284213391 > nit: b/284213391 (missing the 'b'), for both of these Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 21:10:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/myst: Add PCIe shutdown workaround
by Jon Murphy (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Eric Lai, Jon Murphy, Karthik Ramasubramanian, Martin Roth. Hello Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75583?usp=email to look at the new patch set (#3). Change subject: mb/google/myst: Add PCIe shutdown workaround ...................................................................... mb/google/myst: Add PCIe shutdown workaround On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe --- M src/mainboard/google/myst/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/75583/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/myst: Add PCIe shutdown workaround
by Tim Van Patten (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Eric Lai, Jon Murphy, Karthik Ramasubramanian, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75583?usp=email ) Change subject: mb/google/myst: Add PCIe shutdown workaround ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/75583/comment/b8d61c2f_39fd8315 : PS2, Line 56: .turn_off_unused_lanes = true, Can we toggle this to `false` instead, assuming that also fixes it? It seems like a more direct approach to what you're trying to achieve here, based on the description: https://source.corp.google.com/chromeos_public/src/third_party/coreboot/src… ``` uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present ``` https://review.coreboot.org/c/coreboot/+/75583/comment/74c0d345_346d57f3 : PS2, Line 57: /284213391 nit: b/284213391 (missing the 'b'), for both of these -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 20:58:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix
by Tim Van Patten (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Bao Zheng, Fred Reitberger, Martin L Roth, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74971?usp=email ) Change subject: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Gerrit-Change-Number: 74971 Gerrit-PatchSet: 6 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 20:53:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/myst: Add PCIe shutdown workaround
by Jon Murphy (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten. Hello Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75583?usp=email to look at the new patch set (#2). Change subject: mb/google/myst: Add PCIe shutdown workaround ...................................................................... mb/google/myst: Add PCIe shutdown workaround On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe --- M src/mainboard/google/myst/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/75583/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: myst: Add PCIe shutdown workaround
by Jon Murphy (Code Review) 01 Jun '23

01 Jun '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75583?usp=email ) Change subject: myst: Add PCIe shutdown workaround ...................................................................... myst: Add PCIe shutdown workaround On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe --- M src/mainboard/google/myst/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/75583/1 diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 6d0d0d6..12eba57 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -54,6 +54,8 @@ .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, + /* TODO(/284213391): Fix PCIe shutdown */ + .link_hotplug = 3, .clk_req = CLK_REQ3, }; @@ -66,6 +68,8 @@ .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, + /* TODO(/284213391): Fix PCIe shutdown */ + .link_hotplug = 3, .clk_req = CLK_REQ3, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/75583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Gerrit-Change-Number: 75583 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix
by Jon Murphy (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Bao Zheng, Fred Reitberger, Martin L Roth, Martin Roth, Tim Van Patten. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74971?usp=email ) Change subject: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Gerrit-Change-Number: 74971 Gerrit-PatchSet: 6 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 20:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix
by Fred Reitberger (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Bao Zheng, Jon Murphy, Martin L Roth, Martin Roth, Tim Van Patten. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74971?usp=email ) Change subject: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix ...................................................................... Patch Set 6: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/74971/comment/66404b2f_9ac750c2 : PS4, Line 927: /* TODO: Figure out why */ > Please add the bug number tracking this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Gerrit-Change-Number: 74971 Gerrit-PatchSet: 6 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 20:43:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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