coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75596?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc --- M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/soc.asl 3 files changed, 5 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/75596/1 diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c47b7b7..af62abd 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -3,8 +3,6 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ /* Describe the Northbridge devices */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index a4903e9..08f7a31 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -7,21 +7,6 @@ /* System Bus */ /* _SB.PCI0 */ -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - /* Describe the Southbridge devices */ /* 0:14.0 - SMBUS */ diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index b411c20..47d5992 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/75596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Gerrit-Change-Number: 75596 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/glinda/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75595?usp=email ) Change subject: soc/amd/glinda/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/glinda/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 --- D src/soc/amd/glinda/acpi/pci0.asl M src/soc/amd/glinda/acpi/soc.asl 2 files changed, 7 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/75595/1 diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl deleted file mode 100644 index 3f29c33..0000000 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl index b810a2b..ae104c6 100644 --- a/src/soc/amd/glinda/acpi/soc.asl +++ b/src/soc/amd/glinda/acpi/soc.asl @@ -18,7 +18,13 @@ #include "mmio.asl" - #include "pci0.asl" + #include <soc/amd/common/acpi/pci_root.asl> + + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 Gerrit-Change-Number: 75595 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75594?usp=email ) Change subject: soc/amd/phoenix/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/phoenix/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 --- D src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/phoenix/acpi/soc.asl 2 files changed, 7 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/75594/1 diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl deleted file mode 100644 index 6039a5aa..0000000 --- a/src/soc/amd/phoenix/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Phoenix */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/phoenix/acpi/soc.asl b/src/soc/amd/phoenix/acpi/soc.asl index 4df7835..ce9638b 100644 --- a/src/soc/amd/phoenix/acpi/soc.asl +++ b/src/soc/amd/phoenix/acpi/soc.asl @@ -18,7 +18,13 @@ #include "mmio.asl" - #include "pci0.asl" + #include <soc/amd/common/acpi/pci_root.asl> + + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 Gerrit-Change-Number: 75594 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75593?usp=email ) Change subject: soc/amd/mendocino/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/mendocino/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 --- D src/soc/amd/mendocino/acpi/pci0.asl M src/soc/amd/mendocino/acpi/soc.asl 2 files changed, 7 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/75593/1 diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl deleted file mode 100644 index 3aa2aa8..0000000 --- a/src/soc/amd/mendocino/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl index 7e9e2e8..4bdc1ac 100644 --- a/src/soc/amd/mendocino/acpi/soc.asl +++ b/src/soc/amd/mendocino/acpi/soc.asl @@ -18,7 +18,13 @@ #include "mmio.asl" - #include "pci0.asl" + #include <soc/amd/common/acpi/pci_root.asl> + + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Gerrit-Change-Number: 75593 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75592?usp=email ) Change subject: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/cezanne/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 --- D src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/acpi/soc.asl 2 files changed, 7 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/75592/1 diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl deleted file mode 100644 index c778578..0000000 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index f8f7a8a..5d0d50f 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -16,7 +16,13 @@ #include "mmio.asl" - #include "pci0.asl" + #include <soc/amd/common/acpi/pci_root.asl> + + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Gerrit-Change-Number: 75592 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75591?usp=email ) Change subject: soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl ...................................................................... soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Picasso ACPI code a bit more in line with the ACPI code of the newer SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa --- R src/soc/amd/picasso/acpi/mmio.asl M src/soc/amd/picasso/acpi/soc.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/75591/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/mmio.asl similarity index 100% rename from src/soc/amd/picasso/acpi/sb_fch.asl rename to src/soc/amd/picasso/acpi/mmio.asl diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 0b520e4..a958570 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -19,8 +19,8 @@ /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> -/* Describe the devices in the Southbridge */ -#include "sb_fch.asl" +/* Describe the MMIO devices in the FCH */ +#include "mmio.asl" /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa Gerrit-Change-Number: 75591 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75569?usp=email ) Change subject: soc/amd/picasso/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/picasso/acpi: use ROOT_BRIDGE macro Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. TEST=Both Ubuntu 2022.4 and Windows 10 still boot successfully and don't show any new ACPI-related error. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f --- M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/soc.asl 3 files changed, 5 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/75569/1 diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 14c793e..bec9b46 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,9 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Note: Only need HID on Primary Bus */ -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - /* Describe the Northbridge devices */ /* PCI Routing Table */ diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 898914c..ead676d 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -3,21 +3,6 @@ /* System Bus */ /* _SB.PCI0 */ -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> #include <soc/amd/common/acpi/platform.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index f44f873..82c2766 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/75569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f Gerrit-Change-Number: 75569 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/75568?usp=email to review the following change. Change subject: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro ...................................................................... soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro When instantiated in the DSDT, this macro will expand to the static part of the PCIe root bridge device. This macro allows both to deduplicate parts of the DSDT code, but also allows adding more than one PCIe root bride device in the DSDT. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 --- A src/soc/amd/common/acpi/pci_root.asl 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/75568/1 diff --git a/src/soc/amd/common/acpi/pci_root.asl b/src/soc/amd/common/acpi/pci_root.asl new file mode 100644 index 0000000..46d15b7 --- /dev/null +++ b/src/soc/amd/common/acpi/pci_root.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ROOT_BRIDGE(acpi_name) \ + Device(acpi_name) { \ + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ \ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ \ + Method (_OSC, 4, NotSerialized) { \ + /* Check for proper PCI/PCIe UUID */ \ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) \ + { \ + /* Let OS control everything */ \ + Return(Arg3) \ + } Else { \ + CreateDWordField(Arg3, 0, CDW1) \ + CDW1 = CDW1 | 4 /* Unrecognized UUID, so set bit 2 to 1 */ \ + Return(Arg3) \ + } \ + } \ + } -- To view, visit https://review.coreboot.org/c/coreboot/+/75568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Gerrit-Change-Number: 75568 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Add PSP verstage callbacks
by Karthik Ramasubramanian (Code Review) 01 Jun '23

01 Jun '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75585?usp=email ) Change subject: mb/google/myst: Add PSP verstage callbacks ...................................................................... mb/google/myst: Add PSP verstage callbacks Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/myst/Makefile.inc M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/verstage.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75585/1 diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 54d4f30..9a8f8d8 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -9,6 +9,8 @@ ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c + subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index 3ef89ca..74839fa 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -8,5 +8,6 @@ romstage-y += tpm_tis.c verstage-y += tpm_tis.c +verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/google/myst/verstage.c b/src/mainboard/google/myst/verstage.c new file mode 100644 index 0000000..2320106 --- /dev/null +++ b/src/mainboard/google/myst/verstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio.h> +#include <arch/io.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <psp_verstage.h> +#include <security/vboot/vboot_common.h> +#include <soc/espi.h> +#include <soc/southbridge.h> + +void verstage_mainboard_early_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_early_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_espi_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); + + espi_switch_to_spi1_pads(); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_tpm_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Gerrit-Change-Number: 75585 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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