coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/google/rex: Enable ISH support
by Subrata Banik (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Bernardo Perez Priego, Boris Mittelberg, Caveh Jalali, Gwendal Grignou, Harsha B R, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Paul Menzel, Tarun Tuli, Vijay P Hiremath, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75039?usp=email ) Change subject: mb/google/rex: Enable ISH support ...................................................................... Patch Set 15: (2 comments) Patchset: PS11: > can u please take care of the gpio.c changes as well (meant for ISH) […] Acknowledged File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75039/comment/64d7bd9a_9c23b2ca : PS11, Line 37: ish_enable_pads > ``` […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Gerrit-Change-Number: 75039 Gerrit-PatchSet: 15 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)gmail.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 07:14:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable ISH support
by Subrata Banik (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Bernardo Perez Priego, Boris Mittelberg, Caveh Jalali, Gwendal Grignou, Harsha B R, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Paul Menzel, Tarun Tuli, Vijay P Hiremath, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75039?usp=email ) Change subject: mb/google/rex: Enable ISH support ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Gerrit-Change-Number: 75039 Gerrit-PatchSet: 15 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)gmail.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 07:14:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsEnable
by Mario Scheithauer (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Felix Singer, Himanshu Sahdev, Jan Samek, Maxim Polyakov, Nico Huber, Sean Rhodes, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75553?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75553/comment/d349ecc8_19e7a41a : PS3, Line 9: > from pascal case Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Gerrit-Change-Number: 75553 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 06:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsEnable
by Mario Scheithauer (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Felix Singer, Jan Samek, Mario Scheithauer, Maxim Polyakov, Nico Huber, Sean Rhodes, Werner Zeh. Hello Felix Singer, Jan Samek, Maxim Polyakov, Nico Huber, Sean Rhodes, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75553?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Jan Samek, Verified+1 by build bot (Jenkins) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable ...................................................................... soc/intel/apollolake: Switch to snake case for SataPortsEnable For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/up/squared/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 16 files changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/75553/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Gerrit-Change-Number: 75553 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: Add devicetree for support audio
by Kapil Porwal (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Rui Zhou, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75575?usp=email ) Change subject: mb/google/rex/var/screebo: Add devicetree for support audio ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213 Gerrit-Change-Number: 75575 Gerrit-PatchSet: 10 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 06:11:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected
by Krishna P Bhat D (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75603?usp=email ) Change subject: mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected ...................................................................... mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected When split CSE firmware update option is chosen, allow call to cse_fw_sync() in romstage. In romstage, the decision to switch to RW from RO is made. Change-Id: I68c706bd4d53a768d1a5011b9dff441fee8f9e1f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/75603/1 diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index b5351de..a6a281b 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -128,7 +128,8 @@ /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) + if (!s3wake && (CONFIG(SOC_INTEL_CSE_LITE_SKU) || + CONFIG(SOC_INTEL_CSE_LITE_SPLIT_FW_SYNC))) cse_fw_sync(); /* Update coreboot timestamp table with CSE timestamps */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68c706bd4d53a768d1a5011b9dff441fee8f9e1f Gerrit-Change-Number: 75603 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: common/block/cse: Add a field in CMOS to determine FW update required
by Krishna P Bhat D (Code Review) 02 Jun '23

02 Jun '23

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75602?usp=email ) Change subject: common/block/cse: Add a field in CMOS to determine FW update required ...................................................................... common/block/cse: Add a field in CMOS to determine FW update required This patch adds a field in CMOS to determine if CSE firmware update is required in cases where split CSE firmware option is chosen. CSE version check is performed in romstage to determine if firmware update is required. If an update is required, the field is set and update is deferred to ramstage. BUG=None BRANCH=None TEST=Verified CSE firmware upgrade/downgrade on ADL-N craask. Change-Id: I0d90f26747ea670cd0e5a74525ac585bad8ace9e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse_cmos.h 4 files changed, 51 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/75602/1 diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 679c4f7..3b73db2 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -7,7 +7,8 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) += cse_spec.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c -ramstage-$(CONFIG_SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) += cse_cmos.c +romstage-$(SOC_INTEL_STORE_CSE_VERSION_IN_CMOS) += cse_cmos.c +ramstage-$(SOC_INTEL_STORE_CSE_VERSION_IN_CMOS) += cse_cmos.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ifeq ($(CONFIG_STITCH_ME_BIN),y) diff --git a/src/soc/intel/common/block/cse/cse_cmos.c b/src/soc/intel/common/block/cse/cse_cmos.c index f4582fe..8bdcab7 100644 --- a/src/soc/intel/common/block/cse/cse_cmos.c +++ b/src/soc/intel/common/block/cse/cse_cmos.c @@ -42,6 +42,7 @@ uint32_t signature; struct fw_version cse_version; struct fw_version ish_version; + uint8_t fw_update_req; uint16_t checksum; } __packed; @@ -90,6 +91,7 @@ version->signature = PARTITION_FW_SIGNATURE; memset(&version->cse_version, 0, sizeof(struct fw_version)); memset(&version->ish_version, 0, sizeof(struct fw_version)); + memset(&version->fw_update_req, 0, sizeof(uint8_t)); version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) @@ -149,3 +151,30 @@ memcpy(&version.ish_version, ish_version, sizeof(struct fw_version)); write_cmos_partition_version(&version); } + +void set_cmos_fw_update_req(const uint8_t *fw_update_req) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(&version.fw_update_req, fw_update_req, sizeof(fw_update_req)); + write_cmos_partition_version(&version); +} + +void get_cmos_fw_update_req(uint8_t *fw_update_req) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(fw_update_req, &version.fw_update_req, sizeof(fw_update_req)); +} diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 348449f..e98f60d 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -808,6 +808,10 @@ error_exit: cbfs_unmap(cbfs_rw_hash); cbfs_unmap(cse_cbfs_rw); + if(CONFIG(CSE_LITE_SPLIT_FW_SYNC) && ENV_RAMSTAGE) { + uint8_t fw_update_req = 0; + set_cmos_fw_update_req(&fw_update_req); + } return rv; } @@ -1133,6 +1137,13 @@ return; } + if (CONFIG(CSE_LITE_SPLIT_FW_SYNC) && ENV_RAMSTAGE) { + uint8_t fw_update_req; + get_cmos_fw_update_req(&fw_update_req); + if(!fw_update_req) + return; + } + if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) { printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); @@ -1183,6 +1194,10 @@ cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_METADATA_NOT_FOUND); if (status != CSE_UPDATE_NOT_REQUIRED) { + if(CONFIG(CSE_LITE_SPLIT_FW_SYNC) && ENV_ROMSTAGE) { + uint8_t fw_update_req = 1; + set_cmos_fw_update_req(&fw_update_req); + } if(trigger_fw_update_prerequisite()) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); rv = cse_trigger_fw_update(&cse_bp_info.bp_info, status, &target_rdev); diff --git a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h index 6ecc3e7..656ca76 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h @@ -17,4 +17,9 @@ /* Function to update the ish version stored in CMOS memory */ void set_cmos_ish_version(const struct fw_version *ish_version); +/* Function to get the firmware update required field stored in CMOS memory */ +void get_cmos_fw_update_req(uint8_t *fw_update_req); + +/* Function to update the firmware update required field stored in CMOS memory */ +void set_cmos_fw_update_req(const uint8_t *fw_update_req); #endif /* SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d90f26747ea670cd0e5a74525ac585bad8ace9e Gerrit-Change-Number: 75602 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: common/block/cse: Add config option to store CSE version in CMOS
by Krishna P Bhat D (Code Review) 02 Jun '23

02 Jun '23

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75601?usp=email ) Change subject: common/block/cse: Add config option to store CSE version in CMOS ...................................................................... common/block/cse: Add config option to store CSE version in CMOS This patch adds an option to store CSE version in CMOS memory when split CSE firmware sync option is selected or store FPT partition version is selected. Change-Id: I95ecd7d576d83e639c590f9180e17554d5b6502e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/75601/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index ce11653..6b41d32 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -48,7 +48,7 @@ config SOC_INTEL_PARTITION_FW_CMOS_OFFSET int default 72 - depends on SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + depends on SOC_INTEL_STORE_CSE_VERSION_IN_CMOS help This configuration option stores the starting offset of firmware partition versions in CMOS memory. The offset should be byte aligned and must leave enough memory to store @@ -276,6 +276,13 @@ This config will enable CSE RW firmware update to be deferred to ramstage. Switch from CSE RO to RW will still be performed in romstage. +config SOC_INTEL_STORE_CSE_VERSION_IN_CMOS + bool + default y if SOC_INTEL_CSE_LITE_SPLIT_FW_SYNC || SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + depends on SOC_INTEL_CSE_LITE_SKU + help + This configuration option stores the CSE firmware version in CMOS memory. + config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT bool depends on SOC_INTEL_COMMON_BLOCK_CSE -- To view, visit https://review.coreboot.org/c/coreboot/+/75601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95ecd7d576d83e639c590f9180e17554d5b6502e Gerrit-Change-Number: 75601 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya/var/redrix: Add new GFX device with custom _PLD
by Won Chung (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Subrata Banik, Tarun Tuli. Won Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75509?usp=email ) Change subject: mb/google/brya/var/redrix: Add new GFX device with custom _PLD ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: @subratabanik@google.com Hey Subrata, Could I also have this patch reviewed too, so that I can cherrypick and request expedited fw qual for M116? (in discussion at http://b/278275865) -- To view, visit https://review.coreboot.org/c/coreboot/+/75509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Gerrit-Change-Number: 75509 Gerrit-PatchSet: 4 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 05:56:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: lib: Support localized text of memory_training_desc in ux_locales.c
by Hsuan-ting Chen (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Subrata Banik, Tarun Tuli. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75330?usp=email ) Change subject: lib: Support localized text of memory_training_desc in ux_locales.c ...................................................................... Patch Set 8: (1 comment) File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/75330/comment/5907923a_d2e414df : PS5, Line 408: romstage-y += ux_locales.c > > It might be better to have another feature enablement config, namely MAINBOARD_USE_EARLY_LIBGFXINI […] Sure I will do it seperately (after this CL?) Close this comment for now as it is not really related to this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Gerrit-Change-Number: 75330 Gerrit-PatchSet: 8 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 05:00:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Hsuan-ting Chen <roccochen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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