coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[XS] Change in coreboot[master]: util/docker/coreboot-sdk: Drop legacy libusb package
by Nico Huber (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Edward O'Callaghan, Felix Singer, Martin L Roth, Stefan Reinauer, Thomas Heijligen. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76083?usp=email ) Change subject: util/docker/coreboot-sdk: Drop legacy libusb package ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b7530e5b707e12fbf3f8058999456dc1f8dff4 Gerrit-Change-Number: 76083 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 30 Jun 2023 21:46:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: util/docker/coreboot-sdk: Drop legacy libftdi package
by Nico Huber (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Edward O'Callaghan, Felix Singer, Martin L Roth, Stefan Reinauer, Thomas Heijligen. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76084?usp=email ) Change subject: util/docker/coreboot-sdk: Drop legacy libftdi package ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b575bc9abfd192e93811a83d8615bed61eba0c Gerrit-Change-Number: 76084 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 30 Jun 2023 21:46:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: util/apcb: Add apcb edit tool for phoenix
by Karthik Ramasubramanian (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Martin L Roth, Raul Rangel, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76188?usp=email ) Change subject: util/apcb: Add apcb edit tool for phoenix ...................................................................... Patch Set 2: (1 comment) File util/apcb/apcb_v3a_edit.py: https://review.coreboot.org/c/coreboot/+/76188/comment/2b581c41_06dd56be : PS2, Line 35: parser.add_argument( : '--mem_type', : type=str, : default='lp5', : help='Memory type [lp5|lp5x]. Default = lp5') Not required. In previous versions of tool, we used it to choose the starting pattern for SPD and it varied based on memory technology. Here the starting pattern for SPD (SPD_ENTRY_MAGIC) is not related to memory technology. Hence can be removed. Also we are not using this option in the rest of the code. -- To view, visit https://review.coreboot.org/c/coreboot/+/76188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Gerrit-Change-Number: 76188 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 21:43:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: acpi/gnvs.c: Drop unused pointer to the cbmem console
by Kyösti Mälkki (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Kyösti Mälkki, Lance Zhao, Mariusz Szafrański, Marshall Dawson, Raul Rangel, Sumeet R Pawnikar, Suresh Bellampalli, Tim Wawrzynczak, Tim Wawrzynczak, Vanessa Eusebio. Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/64303?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Code-Review+2 by Raul Rangel, Code-Review+2 by Sumeet R Pawnikar, Code-Review+2 by Tim Wawrzynczak, Verified+1 by build bot (Jenkins) Change subject: acpi/gnvs.c: Drop unused pointer to the cbmem console ...................................................................... acpi/gnvs.c: Drop unused pointer to the cbmem console Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/gnvs.c M src/soc/amd/cezanne/acpi/globalnvs.asl M src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/glinda/acpi/globalnvs.asl M src/soc/amd/glinda/include/soc/nvs.h M src/soc/amd/mendocino/acpi/globalnvs.asl M src/soc/amd/mendocino/include/soc/nvs.h M src/soc/amd/phoenix/acpi/globalnvs.asl M src/soc/amd/phoenix/include/soc/nvs.h M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/include/soc/nvs.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/include/soc/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/include/soc/nvs.h 33 files changed, 32 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/64303/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Gerrit-Change-Number: 64303 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx(a)akumat.pl> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx(a)akumat.pl> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: [TESTME] haswell: Keep 32-bit allocations below ECAM
by Nico Huber (Code Review) 30 Jun '23

30 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76198?usp=email ) Change subject: [TESTME] haswell: Keep 32-bit allocations below ECAM ...................................................................... [TESTME] haswell: Keep 32-bit allocations below ECAM Hopefully works around boot issues on T440p. Change-Id: Ife0566779f7524ebc129f27636b5633dc5af99fd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/76198/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index d1c9ec2..7ae08a3 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -64,6 +64,14 @@ int default 64 +config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xf0000000 + help + Keep 32-bit allocations below ECAM, effectively reserving all + space between 0xf4000000 and 0xfe000000. This is also what we + do in ACPI, and trying to allocate in that range leads to un- + identified conflicts. + config DCACHE_RAM_BASE hex default 0xff7c0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/76198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife0566779f7524ebc129f27636b5633dc5af99fd Gerrit-Change-Number: 76198 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: util/apcb: Add apcb edit tool for phoenix
by Rob Barnes (Code Review) 30 Jun '23

30 Jun '23

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76188?usp=email ) Change subject: util/apcb: Add apcb edit tool for phoenix ...................................................................... util/apcb: Add apcb edit tool for phoenix Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into an APCB for phoenix platform. The tool makes several assumptions: * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero. * Each block is 64 bytes. * Dimm and socket are always 0 * Unused SPD entries are zero'd BUG=b:281983434 BRANCH=None TEST=build, flash, boot myst Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M Makefile.inc M src/mainboard/google/myst/Makefile.inc A util/apcb/apcb_v3a_edit.py 3 files changed, 159 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/76188/1 diff --git a/Makefile.inc b/Makefile.inc index b35ec86..a065094 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -613,6 +613,8 @@ APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py +APCB_V3A_EDIT_TOOL:=$(top)/util/apcb/apcb_v3a_edit.py + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage FUTILITY?=$(objutil)/futility/futility diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 54d4f30..d5a9c34 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -26,23 +26,23 @@ # Add the below section back in after the apcbtool is updated to handle the # Phoenix APCB SPD configuration. -#ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/Makefile.inc),) -# -#LIB_SPD_DEPS = $(SPD_SOURCES) -# -#APCB_SOURCES = $(obj)/$(APCB_NAME).gen -# -#$(obj)/$(APCB_NAME).gen: $(SPD_SOURCES) \ -# $(APCB_V3_EDIT_TOOL) \ -# $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin -# $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin \ -# $(obj)/$(APCB_NAME).gen \ -# --spd_sources $(SPD_SOURCES) \ -# --mem_type 'lp5' -#else -#$(info SPD sources not found. Skipping APCB.) -#files_added:: die_no_apcb -#endif +ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/Makefile.inc),) + +LIB_SPD_DEPS = $(SPD_SOURCES) + +APCB_SOURCES = $(obj)/$(APCB_NAME).gen + +$(obj)/$(APCB_NAME).gen: $(SPD_SOURCES) \ + $(APCB_V3A_EDIT_TOOL) \ + $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin + $(APCB_V3A_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin \ + $(obj)/$(APCB_NAME).gen \ + --spd_sources $(SPD_SOURCES) \ + --mem_type 'lp5' +else +$(info SPD sources not found. Skipping APCB.) +files_added:: die_no_apcb +endif else $(info APCB sources not found. Skipping APCB.) diff --git a/util/apcb/apcb_v3a_edit.py b/util/apcb/apcb_v3a_edit.py new file mode 100755 index 0000000..e437b95 --- /dev/null +++ b/util/apcb/apcb_v3a_edit.py @@ -0,0 +1,140 @@ +#!/usr/bin/env python3 + +# Script for editing APCB_v3a binaries, such as injecting SPDs. + +import re +import argparse +from collections import namedtuple +from struct import * + +APCB_CHECKSUM_OFFSET = 16 +SPD_ENTRY_MAGIC = bytes.fromhex('0200480000000000') +SPD_SIZE = 512 +EMPTY_SPD = b'\x00' * SPD_SIZE +ZERO_BLOCKS = (2, 4, 6, 7) +BLOCK_SIZE = 64 + +spd_block_header_fmt = '<HHHH' +spd_block_header = namedtuple( + 'spd_block_header', 'Type, Length, Key, Reserved') + +def parseargs(): + parser = argparse.ArgumentParser(description='Inject SPDs into APCB binaries') + parser.add_argument( + 'apcb_in', + type=str, + help='APCB input file') + parser.add_argument( + 'apcb_out', + type=str, + help='APCB output file') + parser.add_argument( + '--spd_sources', + nargs='+', + help='List of SPD sources') + parser.add_argument( + '--mem_type', + type=str, + default='lp5', + help='Memory type [lp5|lp5x]. Default = lp5') + return parser.parse_args() + + +def chksum(data): + sum = 0 + for b in data[:16] + data[17:]: + sum = (sum + b) & 0xff + return (0x100 - sum) & 0xff + + +def inject(orig, insert, offset): + return b''.join([orig[:offset], insert, orig[offset + len(insert):]]) + + +def main(): + args = parseargs() + + # Load input APCB + print(f'Reading input APCB from {args.apcb_in}') + with open(args.apcb_in, 'rb') as f: + apcb = f.read() + assert chksum(apcb) == apcb[APCB_CHECKSUM_OFFSET], 'Initial checksum is invalid' + orig_apcb_len = len(apcb) + + # Load SPDs + print(f'Using SPD Sources = {", ".join(args.spd_sources)}') + spds = [] + for spd_source in args.spd_sources: + with open(spd_source, 'rb') as f: + spd_data = bytes.fromhex(re.sub(r'\s+', '', f.read().decode())) + assert len(spd_data) == SPD_SIZE, f'{spd_source} is not {SPD_SIZE} bytes' + # Verify ZERO_BLOCKS are zero + for b in ZERO_BLOCKS: + assert all(v==0 for v in spd_data[b*BLOCK_SIZE:(b+1)*BLOCK_SIZE]), f'SPD block #{b} is not zero' + spds.append(spd_data) + assert len(spds) > 0, "No SPDs provided" + + # Inject SPDs into APCB + offset = 0 + spd_idx = 0 + while True: + offset = apcb.find(SPD_ENTRY_MAGIC, offset) + if offset < 0: + print(f'No more SPD entries found') + assert spd_idx >= len(spds), f'Not enough SPD entries in APCB. Need {len(spds)}, found {spd_idx}' + break + + if spd_idx < len(spds): + print(f'Injecting SPD instance {spd_idx}') + spd = spds[spd_idx] + else: + print(f'Injecting empty SPD for instance {spd_idx}') + spd = EMPTY_SPD + + # Inject SPD blocks + for b in range(int(SPD_SIZE/BLOCK_SIZE)): + if b in ZERO_BLOCKS: continue + header_size = calcsize(spd_block_header_fmt) + header_data = apcb[offset:offset + header_size] + header = spd_block_header._make(unpack(spd_block_header_fmt, header_data)) + socket = (header.Key >> 12) & 0xF + channel = (header.Key >> 8) & 0xF + dimm = (header.Key >> 4) & 0xF + block = (header.Key >> 0) & 0xF + + assert header.Type == 2 + assert header.Length == header_size + BLOCK_SIZE + assert socket == 0 + assert channel == 0 + assert block == b + assert dimm == 0 + assert header.Reserved == 0 + offset += header_size + + spd_block = spd[b*BLOCK_SIZE:(b+1)*BLOCK_SIZE] + assert len(spd_block) == BLOCK_SIZE + + # Verify that APCB size didn't change + apcb_len = len(apcb) + apcb = inject(apcb, spd_block, offset) + assert len(apcb) == apcb_len + + offset += BLOCK_SIZE + + spd_idx += 1 + + # Fix APCB checksum + print(f'Fixing APCB checksum') + apcb = inject(apcb, bytes([chksum(apcb)]), APCB_CHECKSUM_OFFSET) + assert chksum(apcb) == apcb[APCB_CHECKSUM_OFFSET], 'Final checksum is invalid' + assert orig_apcb_len == len(apcb), \ + 'The size of the APCB changed.' + + # Write APCB to file + print(f'Writing {len(apcb)} byte APCB to {args.apcb_out}') + with open(args.apcb_out, 'wb') as f: + f.write(apcb) + + +if __name__ == "__main__": + main() -- To view, visit https://review.coreboot.org/c/coreboot/+/76188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Gerrit-Change-Number: 76188 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATION
by Matt DeVillier (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76166?usp=email ) Change subject: soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATION ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id228399ba02708b97110d524ce12c2626588762d Gerrit-Change-Number: 76166 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 19:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/phoenix: Remove TODO after review
by Matt DeVillier (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76165?usp=email ) Change subject: soc/amd/phoenix: Remove TODO after review ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd2b53ff24776238190eb946db7b12827fcfc804 Gerrit-Change-Number: 76165 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 19:50:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/phoenix/Makefile.inc: Refactor repeated lines to a variable
by Matt DeVillier (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76197?usp=email ) Change subject: soc/amd/phoenix/Makefile.inc: Refactor repeated lines to a variable ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: tested? timeless? -- To view, visit https://review.coreboot.org/c/coreboot/+/76197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb262adb3bbda04add79b2e2b8bee9a609a1e5b Gerrit-Change-Number: 76197 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 19:50:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: amdfwtool: Allow bios table source addresses to select base
by Matt DeVillier (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Martin L Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76163?usp=email ) Change subject: amdfwtool: Allow bios table source addresses to select base ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45474600048a33ad186ba4d1baed7b5891ffdefe Gerrit-Change-Number: 76163 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 19:48:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023