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Change subject: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
......................................................................
soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
During a cold reboot, the CBMEM memory resets and loses the stored
firmware versions. This causes the firmware versions to be fetched again
from the CSE, which increases the boot time by about 200 ms. This patch
stores a backup of the firmware version in CMOS and updates the CBMEM
memory during a cold reboot.
BUG=b:280722061
Test=Verified the changes on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 54 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75755/10
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Hello Kapil Porwal, Sridhar Siricilla, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
This patch implements APIs to access the FW versions in CMOS. The get
API allows users to retrieve the current version from CMOS memory.
The set API allows users to set the version in CMOS memory.
BUG=b:280722061
TEST=APIs verified on nivviks and marasov board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/cse_lite_cmos.c
A src/soc/intel/common/block/include/intelblocks/cse_lite_cmos.h
4 files changed, 213 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74995/39
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 11: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/08de8758_af4943bf :
PS10, Line 251: size_t
> This isn't necessary, `sizeof` returns a value of type `size_t` anyway.
Done
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Change subject: doc/Makefile: Fix build dir setting
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75893/comment/b95021ff_daba6e5c :
PS4, Line 16: and make it writable.
> I assume this makes no difference, at least commit 4d8da8ed alone […]
I did some experimentation and it does seem to work even with `BUILDDIR = _build` instead of `BUILDDIR ?= _build`, which is what I assume Felix means by making it writable. The part that does seem to matter is that everything uses the same BUILDDIR name.
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Change subject: doc/Makefile: Fix build dir setting
......................................................................
Patch Set 4: -Code-Review
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75893/comment/08c8b6de_bcace405 :
PS4, Line 16: and make it writable.
> I assume this makes no difference, at least commit 4d8da8ed alone […]
Forgot that I can just read how it's called: In `makeSphinx.sh` we have
```
make sphinx BUILDDIR=/tmp/build
```
This `BUILDDIR=/tmp/build` got through even to the `Makefile.sphinx`.
What broke it is the different variable name. Because rn. we have
an explicit `BUILDDIR=` in the `Makefile` overriding the one from
the `makeSphinx.sh`.
Patchset:
PS4:
With the variable names the same, I don't understand the overall change
(before commit 4d8da8ed to after this one). The only effective difference
seems to be the added `mkdir -p`. Is this necessary?
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Change subject: doc/Makefile: Fix build dir setting
......................................................................
Patch Set 4: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75893/comment/e35de218_34d87273 :
PS4, Line 9: The commit 4d8da8ed ("Docs: Update sphinx targets with the build directory")
Line is too long.
https://review.coreboot.org/c/coreboot/+/75893/comment/6fc96413_0d9e3ec7 :
PS4, Line 10: an user
*a user*, because phonetically it starts with a consonant.
https://review.coreboot.org/c/coreboot/+/75893/comment/0fbf4ea3_c93f0d0a :
PS4, Line 10: intending
AFAICT, beings intend, a variable would be *intended*
https://review.coreboot.org/c/coreboot/+/75893/comment/11534295_5ebfb6b4 :
PS4, Line 12: outside
Technically it's possible on the make command line. What doesn't work
is setting it in the environment. That before commit 4d8da8ed the
`$(BUILDDIR)` in `Makefile.sphinx` was already overwritable shows this.
https://review.coreboot.org/c/coreboot/+/75893/comment/0099d8fd_8ae5dcd8 :
PS4, Line 16: and make it writable.
I assume this makes no difference, at least commit 4d8da8ed alone
wouldn't explain it.
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Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> If we do this at a bigger scale, I would prefer an enum. Then it could
> look as nice as
> ```
> register s0ix = enabled
> ```
I would just go with the true/false macros which we already have. That would be enough for me.
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> Use `%z` in `printf` instead of `%lx` for those arguments.
Thanks, done
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
---
M Makefile.inc
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/hsphy.c
M util/cbfstool/default-x86.fmd
5 files changed, 309 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/11
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> Tried with clang and got the error. […]
Use `%z` in `printf` instead of `%lx` for those arguments.
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