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Change subject: acpi/acpi.c: Split of ACPI table generation into separate files
......................................................................
Patch Set 1: Code-Review+1
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Change subject: acpi/acpigen.c: Be explicit about char sign
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/psp_verstage: move post codes to own header
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
Good idea!
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Change subject: mb/qemu/aarch64: Add PCI support
......................................................................
mb/qemu/aarch64: Add PCI support
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and
see that it gets found and picked up by the resource allocator.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/emulation/qemu-aarch64/Kconfig
M src/mainboard/emulation/qemu-aarch64/bootblock.c
M src/mainboard/emulation/qemu-aarch64/devicetree.cb
M src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
M src/mainboard/emulation/qemu-aarch64/mainboard.c
5 files changed, 61 insertions(+), 0 deletions(-)
Approvals:
Felix Singer: Looks good to me, but someone else must approve
Lean Sheng Tan: Looks good to me, approved
Nico Huber: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig
index 64d7d78..940b89d 100644
--- a/src/mainboard/emulation/qemu-aarch64/Kconfig
+++ b/src/mainboard/emulation/qemu-aarch64/Kconfig
@@ -21,6 +21,13 @@
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MISSING_BOARD_RESET
select ARM64_USE_ARM_TRUSTED_FIRMWARE
+ select PCI
+
+config ECAM_MMCONF_BASE_ADDRESS
+ default 0x4010000000
+
+config ECAM_MMCONF_BUS_NUMBER
+ default 256
config MEMLAYOUT_LD_FILE
string
diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c
index 45a9de4..5fe0888 100644
--- a/src/mainboard/emulation/qemu-aarch64/bootblock.c
+++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c
@@ -20,5 +20,8 @@
mmu_config_range(_bl31, REGION_SIZE(bl31), MA_MEM | MA_S | MA_RW);
+ mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
+ MA_DEV | MA_RW);
+
mmu_enable();
}
diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
index d887837..d6c76e1 100644
--- a/src/mainboard/emulation/qemu-aarch64/devicetree.cb
+++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
@@ -2,4 +2,8 @@
chip mainboard/emulation/qemu-aarch64
device cpu_cluster 0 on end
+
+ device domain 0 on ops qemu_aarch64_pci_domain_ops
+ device pci 00.0 on end
+ end
end
diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
index 50dd35e..70acac8 100644
--- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
@@ -28,3 +28,20 @@
#define VIRT_MMIO_BASE 0x0a000000
#define VIRT_PLATFORM_BUS_BASE 0x0c000000
#define VIRT_SECRAM_BASE 0xe000000
+#define VIRT_PCIE_LOW_MMIO_BASE 0x10000000
+#define VIRT_PCIE_LOW_MMIO_LIMIT 0x3efeffff
+/*
+ * From hw/arm/virt.c:
+ * Highmem IO Regions: This memory map is floating, located after the RAM.
+ * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
+ * top of the RAM, so that its base get the same alignment as the size,
+ * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
+ * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
+ * Note the extended_memmap is sized so that it eventually also includes the
+ * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
+ * index of base_memmap).
+ */
+#define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */
+#define VIRT_PCIE_ECAM_SIZE (256 * MiB)
+#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL
+#define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
index 181536c..09b983f 100644
--- a/src/mainboard/emulation/qemu-aarch64/mainboard.c
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -4,6 +4,7 @@
#include <symbols.h>
#include <device/device.h>
#include <bootmem.h>
+#include <mainboard/addressmap.h>
void bootmem_platform_add_ranges(void)
{
@@ -21,3 +22,32 @@
};
struct chip_operations mainboard_emulation_qemu_aarch64_ops = { };
+
+static void qemu_aarch64_domain_read_resources(struct device *dev)
+{
+ struct resource *res;
+ int index = 0;
+ /* Initialize the system-wide I/O space constraints. */
+ res = new_resource(dev, index++);
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system-wide memory resources constraints. */
+ res = new_resource(dev, index++);
+ res->base = VIRT_PCIE_LOW_MMIO_BASE;
+ res->limit = VIRT_PCIE_LOW_MMIO_LIMIT;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+ res = new_resource(dev, index++);
+ res->base = VIRT_PCIE_HIGH_MMIO_BASE;
+ res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+ mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
+}
+
+struct device_operations qemu_aarch64_pci_domain_ops = {
+ .read_resources = qemu_aarch64_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+};
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Change subject: util/qemu: Add config for AArch64
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/qemu/aarch64: Add PCI support
......................................................................
Patch Set 9: Code-Review+1
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Change subject: new port for Lenovo L420 laptop
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75992/comment/bc782cd5_ea5ebf58 :
PS7, Line 7: new port for Lenovo L420 laptop
Suggestion:
```
mb/lenovo: Add new port for L420
```
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Hello Arthur Heymans, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Rizwan Qureshi, Tarun Tuli, Wonkyu Kim, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#17).
Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
......................................................................
cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
The current design of the `ucode-<variant>.bin` file combines all
possible microcode per cpuid into a unified blob. This model increases
the microcode loading time from RW CBFS due to higher CBFS verification
time (the bigger the CBFS binary the longer the verification takes).
This patch creates a provision to pack individual microcodes (per CPUID)
into the CBFS (RO and RWs). Implementation logic introduces
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config which relies on converting
Intel CPU microcode INC file into the binary file as per format
specified as in `cpu_microcode_$(CPUID).bin`.
For example: Intel CPU microcode `m506e3.inc` to convert into
`cpu_microcode_506e3.bin` binary file for coreboot to integrate if
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled.
Another config named CPU_INTEL_UCODE_SPLIT_BINARIES is used to specify
the directory name (including path) that holds the split microcode
binary files per CPUID for each coreboot variants.
For example: if google/kunimitsu had built with Intel SkyLake processor
with CPUID `506e3` and `506e4` then CPU_INTEL_UCODE_SPLIT_BINARIES
refers to the directory path that holds the split microcode binary
files aka cpu_microcode_506e3.bin and cpu_microcode_506e4.bin.
Refer to the file representation below:
|---3rdparty
| |--- blobs
| | |--- mainboard
| | | |--- google
| | | | |--- kunimitsu
| | | | | |--- microcode_inputs
| | | | | | |--- kunimitsu
| | | | | | | |--- cpu_microcode_506e3.bin
| | | | | | | |--- cpu_microcode_506e4.bin
Users of this config option requires to manually place the microcode
binary files per CPUIDs as per the given format
(`cpu_microcode_$(CPUID).bin`) in a directory. Finally specify the
microcode binary directory path using CPU_UCODE_SPLIT_BINARIES config.
Additionally, modified the `find_cbfs_microcode()` logic to search
microcode from CBFS by CPUID. This change will improve the microcode
verification time from the CBFS, and will make it easier to update
individual microcodes.
BUG=b:242473942
TEST=emerge-rex sys-firmware/mtl-ucode-firmware-private
coreboot-private-files-baseboard-rex coreboot
Able to optimize ~10ms of boot time while loading microcode using
below configuration.
CONFIG_CPU_MICROCODE_CBFS_SPLIT_BINS=y
CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/
$(CONFIG_MAINBOARD_DIR)/microcode_inputs"
Without this patch:
10:start of ramstage 1,005,139 (44)
971:loading FSP-S 1,026,619 (21,479)
> RO/RW-A/RW-B CBFS contains unified cpu_microcode_blob.bin
Name Offset Type Size Comp
...
cpu_microcode_blob.bin 0x1f740 microcode 273408 none
intel_fit 0x623c0 intel_fit 80 none
...
...
bootblock 0x3ee200 bootblock 32192 none
With this patch:
10:start of ramstage 997,495 (43)
971:loading FSP-S 1,010,148 (12,653)
> RO/RW-A/B CBFS that stores split microcode files per CPUID
FMAP REGION: FW_MAIN_A
Name Offset Type Size Comp
fallback/romstage 0x0 stage 127632 none
cpu_microcode_a06a1.bin 0x1f340 microcode 137216 none
cpu_microcode_a06a2.bin 0x40bc0 microcode 136192 none
...
...
ecrw 0x181280 raw 327680 none
fallback/payload 0x1d1300 simple elf 127443 none
At reset, able to load the correct microcode using FIT table (RO CBFS)
[NOTE ] coreboot-coreboot-unknown.9999.3ad3153 Sat May 20 12:29:19
UTC 2023 x86_32 bootblock starting (log level: 8)...
[DEBUG] CPU: Genuine Intel(R) 0000
[DEBUG] CPU: ID a06a1, MeteorLake A0, ucode: 00000016
Able to find `cpu_microcode_a06a1.bin` on google/rex with ES1 CPU
stepping (w/ CPUID 0xA06A1) (from RW CBFS)
localhost ~ # cbmem -c -1 | grep microcode
[DEBUG] microcode: sig=0xa06a1 pf=0x80 revision=0x16
[INFO ] CBFS: Found 'cpu_microcode_a06a1.bin' @0x407c0 size 0x21800 in
mcache @0x75c0d0e0
[INFO ] microcode: Update skipped, already up-to-date
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012
---
M src/cpu/intel/microcode/Kconfig
M src/cpu/intel/microcode/Makefile.inc
M src/cpu/intel/microcode/microcode.c
3 files changed, 108 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/75357/17
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