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Change subject: soc/intel/meteorlake: Add support for crashlog
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS23:
> > I will send the log. […]
Log from my system
[DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400
[DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280
[DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa
[DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80
[DEBUG] Region[0x4].Tag=0x1 offset=0x780, size=0x280
[DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa
[DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e
[DEBUG] Region[0x7].Tag=0x0 offset=0x0, size=0x0
[DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400
[DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280
[DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa
[DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80
[DEBUG] Region[0x4].Tag=0x1 offset=0x780, size=0x280
[DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa
[DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e
>>make sense to use associated string rather using TAG ids for debug prints ?
I can add this in separate patch. For now, lets merge this patch
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Change subject: soc/intel/meteorlake: Rename shared SRAM aliases
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75999/comment/232b30f6_52dbfe08 :
PS2, Line 19: TEST=Able to build.
> I'd suggest at least using util/abuild tests on affected boards: `util/abuild/abuild -p none -t goog […]
Already made changes to all variants under google/rex
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Change subject: soc/intel/meteorlake: Rename shared SRAM aliases
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75999/comment/a342e0f7_235c66e8 :
PS2, Line 7: sram
> nit: `SRAM`. […]
Done
https://review.coreboot.org/c/coreboot/+/75999/comment/5567bd30_53af8735 :
PS2, Line 9: share
> share*d*?
Done
https://review.coreboot.org/c/coreboot/+/75999/comment/1ed6a00e_0b75fc31 :
PS2, Line 9: Rename share sram aliases for IOE and PMC to make them
: more readable.
> Fits in one line (72 characters).
Done
https://review.coreboot.org/c/coreboot/+/75999/comment/308288be_81399bee :
PS2, Line 11:
> Maybe explicitly list the old/new keywords: […]
Done
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Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75999?usp=email
to look at the new patch set (#3).
Change subject: soc/intel/meteorlake: Rename shared SRAM aliases
......................................................................
soc/intel/meteorlake: Rename shared SRAM aliases
Rename shared SRAM aliases for IOE and PMC to make them more readable.
pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram.
pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram.
Rename them in SOC code as well as mainboard to make sure the patch
builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
M src/soc/intel/meteorlake/chipset.cb
4 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75999/3
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Change subject: allocator_v4: Fix top-level allocations w/o IORESOURCE_ABOVE_4G
......................................................................
Patch Set 4: Code-Review+1
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Change subject: arch/x86,lib: Migrate SMBIOS implementation to common code
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75886/comment/ffec964b_01be6db8 :
PS3, Line 11: code define
> I think "having architecture-specific code define some functions" is equivalent to "requiring archit […]
I thought about it again. Let's leave it. Sorry for delaying.
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Change subject: allocator_v4: Fix top-level allocations w/o IORESOURCE_ABOVE_4G
......................................................................
Patch Set 4: Code-Review+2
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Hello Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Felix Singer, Kyösti Mälkki, Raul Rangel, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: allocator_v4: Fix top-level allocations w/o IORESOURCE_ABOVE_4G
......................................................................
allocator_v4: Fix top-level allocations w/o IORESOURCE_ABOVE_4G
When moving the code to allocate at the top level in commit 9260ea60bfa4
(allocator_v4: Use memranges only for toplevel), a call to restrict the
limit of the resource was dropped. Probably by accident in one of the
earliest rebases. Without this call to effective_limit(), 64-bit resour-
ces at the top level, i.e. PCI bus 0, were always placed above 4G. Even
when this was not requested with the IORESOURCE_ABOVE_4G flag.
Tested on kontron/ktqm77 where the issue could be reproduced with
x86_64. Without the fix, boot hangs when trying to access the GMA
MMIO registers of PCI 00:02.0, which were placed above 4G.
Change-Id: Ied3a0695ef5e91f092bf2d442c1c482057643483
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Found-by: 9elements QA
---
M src/device/resource_allocator_v4.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/76090/4
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41959 )
Change subject: [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource
......................................................................
[WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource
Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/resource_allocator_v4.5.c
1 file changed, 40 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41959/1
diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c
index 34e9fdd..96a6503 100644
--- a/src/device/resource_allocator_v4.5.c
+++ b/src/device/resource_allocator_v4.5.c
@@ -394,6 +394,43 @@
}
/*
+ * Pass 2 of the resource allocator at the bridge level loops through
+ * all the resources for the bridge and assigns all the base addresses
+ * of its children's resources of the same type. update_bridge_resource()
+ * of pass 1 pre-calculated the offsets of these bases inside the bridge
+ * resource. Now that the bridge resource is allocated, all we have to
+ * do is to add its final base to these offsets.
+ *
+ * Once allocation at the current bridge is complete, resource allocator
+ * continues walking down the downstream bridges until it hits the leaf
+ * devices.
+ */
+static void allocate_bridge_resources(const struct device *bridge, struct resource *bridge_res)
+{
+ void assign_resource_cb(void *param, struct device *dev, struct resource *res)
+ {
+ /* We have to filter the same resources as update_bridge_resource(). */
+ if (!res->size || !res->limit)
+ return;
+
+ assign_resource(res, *(const resource_t *)param + res->base, dev);
+
+ if (res->flags & IORESOURCE_BRIDGE)
+ allocate_bridge_resources(dev, res);
+ }
+
+ const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH;
+ const unsigned long type = bridge_res->flags & type_mask;
+ struct bus *const bus = bridge->link_list;
+
+ if (!bus)
+ return;
+
+ /* Run assign_resource_cb() for all downstream resources of the same type. */
+ search_bus_resources(bus, type_mask, type, assign_resource_cb, &bridge_res->base);
+}
+
+/*
* This is where the actual allocation of resources happens during
* pass 2. We construct a list of memory ranges corresponding to the
* resource of a given type, then look for the biggest unallocated
@@ -433,63 +470,15 @@
}
assign_resource(res, base, dev);
+
+ if (res->flags & IORESOURCE_BRIDGE)
+ allocate_bridge_resources(dev, res);
}
cleanup_resource_ranges(domain, &ranges, domain_res);
}
/*
- * Pass 2 of the resource allocator at the bridge level loops through
- * all the resources for the bridge and assigns all the base addresses
- * of its children's resources of the same type. update_bridge_resource()
- * of pass 1 pre-calculated the offsets of these bases inside the bridge
- * resource. Now that the bridge resource is allocated, all we have to
- * do is to add its final base to these offsets.
- *
- * Once allocation at the current bridge is complete, resource allocator
- * continues walking down the downstream bridges until it hits the leaf
- * devices.
- */
-static void allocate_bridge_resources(const struct device *bridge)
-{
- void assign_resource_cb(void *param, struct device *dev, struct resource *res)
- {
- /* We have to filter the same resources as update_bridge_resource(). */
- if (!res->size || !res->limit)
- return;
-
- assign_resource(res, *(const resource_t *)param + res->base, dev);
- }
-
- const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH;
- struct bus *const bus = bridge->link_list;
- struct resource *res;
- struct device *child;
-
- for (res = bridge->resource_list; res != NULL; res = res->next) {
- if (!res->size)
- continue;
-
- if (!(res->flags & IORESOURCE_BRIDGE))
- continue;
-
- if (!(res->flags & IORESOURCE_ASSIGNED))
- continue;
-
- /* Run assign_resource_cb() for all downstream resources of the same type. */
- search_bus_resources(bus, type_mask, res->flags & type_mask,
- assign_resource_cb, &res->base);
- }
-
- for (child = bus->children; child != NULL; child = child->sibling) {
- if (!dev_has_children(child))
- continue;
-
- allocate_bridge_resources(child);
- }
-}
-
-/*
* Pass 2 of resource allocator begins at the domain level. Every domain
* has two types of resources - io and mem. For each of these resources,
* this function creates a list of memory ranges that can be used for
@@ -504,8 +493,6 @@
*/
static void allocate_domain_resources(const struct device *domain)
{
- struct device *child;
-
/* Resource type I/O */
allocate_toplevel_resources(domain, IORESOURCE_IO);
@@ -516,14 +503,6 @@
* on the biggest resource requirement.
*/
allocate_toplevel_resources(domain, IORESOURCE_MEM);
-
- for (child = domain->link_list->children; child; child = child->sibling) {
- if (!dev_has_children(child))
- continue;
-
- /* Continue allocation for all downstream bridges. */
- allocate_bridge_resources(child);
- }
}
/*
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4
Gerrit-Change-Number: 41959
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange