coreboot-gerrit June 2023

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[M] Change in coreboot[master]: include/intel/post_code.h: Change post code prefix to POSTCODE
by Felix Singer (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Yuchen He. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76044?usp=email ) Change subject: include/intel/post_code.h: Change post code prefix to POSTCODE ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/include/cpu/intel/post_codes.h: PS2: The indentations need to be fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/76044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Gerrit-Change-Number: 76044 Gerrit-PatchSet: 2 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 22:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/skyrim/: Set system_configuration to 3 to avoid SMU call
by Tim Van Patten (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Paul Menzel. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76091?usp=email ) Change subject: mb/google/skyrim/: Set system_configuration to 3 to avoid SMU call ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626 Gerrit-Change-Number: 76091 Gerrit-PatchSet: 6 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 22:23:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/skyrim: Set system_configuration to 3 to avoid SMU call
by Tim Van Patten (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jason Glenesk, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76096?usp=email ) Change subject: mb/google/skyrim: Set system_configuration to 3 to avoid SMU call ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76096/comment/32337bd7_d21f6c17 : PS2, Line 7: mb/google/skyrim nit: mb/google/skyrim/var/winterhold -- To view, visit https://review.coreboot.org/c/coreboot/+/76096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522 Gerrit-Change-Number: 76096 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 22:22:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/system76/rpl: Add Oryx Pro 11 as a variant
by Tim Crawford (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73976?usp=email ) Change subject: mb/system76/rpl: Add Oryx Pro 11 as a variant ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/73976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e Gerrit-Change-Number: 73976 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 22:09:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_hpet struct
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76074?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_hpet struct ...................................................................... soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_hpet struct Zero-initialize the ivhd_hpet struct right at the beginning of the ivhd_describe_hpet function to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If4d3563c485eed4a7cb0526a62f7b6c80f763bfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76074 Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: Jason Glenesk: Looks good to me, approved build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 7afabf8..d2080e9 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -36,10 +36,9 @@ static unsigned long ivhd_describe_hpet(unsigned long current, uint8_t hndl, uint16_t src_devid) { ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; + memset(ivhd_hpet, 0, sizeof(*ivhd_hpet)); ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; - ivhd_hpet->reserved = 0x0000; - ivhd_hpet->dte_setting = 0x00; ivhd_hpet->handle = hndl; ivhd_hpet->source_dev_id = src_devid; /* function 0 of FCH PCI device */ ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; -- To view, visit https://review.coreboot.org/c/coreboot/+/76074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4d3563c485eed4a7cb0526a62f7b6c80f763bfd Gerrit-Change-Number: 76074 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/acpi/ivrs: add HID argument to ivhd_describe_f0_device
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76073?usp=email ) Change subject: soc/amd/common/acpi/ivrs: add HID argument to ivhd_describe_f0_device ...................................................................... soc/amd/common/acpi/ivrs: add HID argument to ivhd_describe_f0_device Allow the caller to specify the HID that gets written to the ivrs_ivhd_f0_entry_t struct. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I830f1fbbd535b100c88997ece10142a5d553950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76073 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 5 insertions(+), 10 deletions(-) Approvals: Fred Reitberger: Looks good to me, approved Jason Glenesk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 8d127e9..7afabf8 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -48,8 +48,8 @@ return current; } -static unsigned long ivhd_describe_f0_device(unsigned long current, - uint16_t dev_id, uint8_t datasetting) +static unsigned long ivhd_describe_f0_device(unsigned long current, uint16_t dev_id, + const char acpi_hid[8], uint8_t datasetting) { ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *)current; memset(ivhd_f0, 0, sizeof(*ivhd_f0)); @@ -57,14 +57,8 @@ ivhd_f0->type = IVHD_DEV_VARIABLE; ivhd_f0->dev_id = dev_id; ivhd_f0->dte_setting = datasetting; - ivhd_f0->hardware_id[0] = 'A'; - ivhd_f0->hardware_id[1] = 'M'; - ivhd_f0->hardware_id[2] = 'D'; - ivhd_f0->hardware_id[3] = 'I'; - ivhd_f0->hardware_id[4] = '0'; - ivhd_f0->hardware_id[5] = '0'; - ivhd_f0->hardware_id[6] = '4'; - ivhd_f0->hardware_id[7] = '0'; + + memcpy(ivhd_f0->hardware_id, acpi_hid, sizeof(ivhd_f0->hardware_id)); current += sizeof(ivrs_ivhd_f0_entry_t); return current; @@ -246,6 +240,7 @@ * reference code uses. Maybe to have a unique PCI device to put into * the field that doesn't collide with any existing device? */ current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), + "AMDI0040", IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); -- To view, visit https://review.coreboot.org/c/coreboot/+/76073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I830f1fbbd535b100c88997ece10142a5d553950f Gerrit-Change-Number: 76073 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_f0 struct
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76072?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_f0 struct ...................................................................... soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_f0 struct Zero-initialize the ivhd_f0 struct right at the beginning of the ivhd_describe_f0_device function to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6750b58dacb9b9192ed21128eb6e3a4495b96d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76072 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 1 insertion(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 79b4ff6..8d127e9 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -52,6 +52,7 @@ uint16_t dev_id, uint8_t datasetting) { ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *)current; + memset(ivhd_f0, 0, sizeof(*ivhd_f0)); ivhd_f0->type = IVHD_DEV_VARIABLE; ivhd_f0->dev_id = dev_id; @@ -65,11 +66,6 @@ ivhd_f0->hardware_id[6] = '4'; ivhd_f0->hardware_id[7] = '0'; - memset(ivhd_f0->compatible_id, 0, sizeof(ivhd_f0->compatible_id)); - - ivhd_f0->uuid_format = 0; - ivhd_f0->uuid_length = 0; - current += sizeof(ivrs_ivhd_f0_entry_t); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/76072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6750b58dacb9b9192ed21128eb6e3a4495b96d0 Gerrit-Change-Number: 76072 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75933?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry ...................................................................... soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry The eMMC entry in the IVRS table should only be generated if an eMMC controller is present in the SoC. Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO device and not a PCI device, but this is what the reference code does. My guess would be that it mainly needs to be a unique PCI device that won't collide with any existing PCI device in the SoC. Add a comment about this too. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 9 insertions(+), 4 deletions(-) Approvals: Fred Reitberger: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 7f1fe5d..79b4ff6 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -245,10 +245,15 @@ if (nb_dev->bus->secondary == 0) { /* Describe EMMC */ - current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), - IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); + if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) { + /* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the + * reference code uses. Maybe to have a unique PCI device to put into + * the field that doesn't collide with any existing device? */ + current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), + IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); + } } ivhd_40->length += (current - current_backup); -- To view, visit https://review.coreboot.org/c/coreboot/+/75933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd Gerrit-Change-Number: 75933 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6
by Felix Singer (Code Review) 23 Jun '23

23 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76080?usp=email ) Change subject: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6 ...................................................................... util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6 Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum 11 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/76080/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9f86995..25ddc86 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ BINUTILS_VERSION=2.40 IASL_VERSION=20230331 # CLANG version number -CLANG_VERSION=16.0.5 +CLANG_VERSION=16.0.6 CMAKE_VERSION=3.26.4 NASM_VERSION=2.16.01 diff --git a/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 04f2648..0000000 --- a/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ad47162ae20fdd85e2db27e1a00a989c88dcacbe tarballs/clang-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..1a4e21e --- /dev/null +++ b/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +f005e3b6d41cf92c083d2a16960aaeb1a6e3c76c tarballs/clang-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 8e5cd8c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -38f9ca678f40617f760b4da5795e92be0e6d573b tarballs/clang-tools-extra-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..939dda2 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +41c06d541cfcc126ddc344e7f162148f2ecf0461 tarballs/clang-tools-extra-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum deleted file mode 100644 index d78ef2d..0000000 --- a/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3330310405697793ec3d24a63233e22713e1c808 tarballs/cmake-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..a7aeb57 --- /dev/null +++ b/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +0de534cfef38697e115c3ae80634765f05e78e5b tarballs/cmake-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 72c7ae4..0000000 --- a/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6db2ebf9a345a8e42011888359de65aea37c75ba tarballs/compiler-rt-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..d79eab8 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +28ddc89aac54cbfa6d0a0cd07a14bbd3f3a01d5f tarballs/compiler-rt-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 84e1e56..0000000 --- a/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ce2c4a55b249a3076e89c31d920f06a65510c4dc tarballs/llvm-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..f8185f1 --- /dev/null +++ b/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +072d2fb4b10f95d06189de00eb7f7e9b35c54e9a tarballs/llvm-16.0.6.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/76080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Gerrit-Change-Number: 76080 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/system76/rpl: Add Galago Pro 7 as a variant
by Tim Crawford (Code Review) 23 Jun '23

23 Jun '23

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75277?usp=email ) Change subject: mb/system76/rpl: Add Galago Pro 7 as a variant ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/75277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a Gerrit-Change-Number: 75277 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Jun 2023 21:28:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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