coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/{cfl,cml,whl}: Use true/false macros for FastPkgCRampDisableGt dt ...
by Yuchen He (Code Review) 24 Jun '23

24 Jun '23

Yuchen He has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76024?usp=email ) Change subject: mb/{cfl,cml,whl}: Use true/false macros for FastPkgCRampDisableGt dt option ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/76024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie56967088c1aa955008d61d162eaf1a5ae135860 Gerrit-Change-Number: 76024 Gerrit-PatchSet: 2 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: [SKETCH] acpigen: Pipe data in acpigen_dsm_uuid_enum_functions()
by Tim Wawrzynczak (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Lance Zhao, Nico Huber. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76092?usp=email ) Change subject: [SKETCH] acpigen: Pipe data in acpigen_dsm_uuid_enum_functions() ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM if you're trying to get rid of alloca() -- To view, visit https://review.coreboot.org/c/coreboot/+/76092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad15af08c39d0ddb477216bc3e93bc799899bb0e Gerrit-Change-Number: 76092 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 24 Jun 2023 14:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86
by Tim Wawrzynczak (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Lance Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76070?usp=email ) Change subject: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76070/comment/3ad7056d_0855812f : PS1, Line 161: if (ENV_X86) > I'm fine with this, but one might consider moving this and the COMMON_MADT conditionals below over t […] ARM has GIC, so would need new MADT entry types anyway, and RISC-V has RINTC, APLIC, IMSIC, etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/76070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335 Gerrit-Change-Number: 76070 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 24 Jun 2023 14:34:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: acpi/Makefile.inc: Conditionally include X86 specific code
by Tim Wawrzynczak (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Arthur Heymans, Lance Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76009?usp=email ) Change subject: acpi/Makefile.inc: Conditionally include X86 specific code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63bbac225662377693ad5f29cc8911494c49b422 Gerrit-Change-Number: 76009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 24 Jun 2023 14:33:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: acpi/acpi.c: Split of ACPI table generation into separate files
by Tim Wawrzynczak (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kyösti Mälkki, Lance Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76008?usp=email ) Change subject: acpi/acpi.c: Split of ACPI table generation into separate files ...................................................................... Patch Set 1: (2 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76008/comment/c67facd7_046a0898 : PS1, Line 213: #if ENV_X86 > Easy enough to move later. seems reasonable to have arch-specific dirs in ACPI; for example DMAR is Intel specific File src/acpi/acpi_dmar.c: PS1: not related to this patch, but while we're talking about DMAR, is there any interest in switching to VIOT instead? It's the non-vendor-specific replacement for all of these vendor-specific IOMMU tables (https://lwn.net/Articles/859291/) -- To view, visit https://review.coreboot.org/c/coreboot/+/76008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af Gerrit-Change-Number: 76008 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 24 Jun 2023 14:32:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: acpi/acpigen.c: Ignore compiler warning about stack overflowing
by Tim Wawrzynczak (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Lance Zhao, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76007?usp=email ) Change subject: acpi/acpigen.c: Ignore compiler warning about stack overflowing ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/76007/comment/aca479ac_0deafa55 : PS1, Line 1769: #pragma GCC diagnostic ignored "-Wstack-usage=" another option could be to use the heap here; the memory will actually be returned to the heap if you call free() before the next malloc. This is definitely safe, but compilers aren't perfect yet -- To view, visit https://review.coreboot.org/c/coreboot/+/76007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d Gerrit-Change-Number: 76007 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 24 Jun 2023 14:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/skylake/chip.h: Use boolean type where applicable
by Felix Singer (Code Review) 24 Jun '23

24 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75880?usp=email ) Change subject: soc/intel/skylake/chip.h: Use boolean type where applicable ...................................................................... soc/intel/skylake/chip.h: Use boolean type where applicable Change-Id: Ic40917689092e8d897a3ba92ac767cdb3b595eb3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75880 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/chip.h 1 file changed, 41 insertions(+), 41 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index af6212e..5119037 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -60,13 +60,13 @@ bool s0ix_enable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable; /* Deep SX enables */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* * Deep Sx Configuration @@ -95,15 +95,15 @@ } SaGv; /* Enable/disable Rank Margin Tool */ - u8 RMT; + bool RMT; /* Disable Command TriState */ - u8 CmdTriStateDis; + bool CmdTriStateDis; /* Lan */ - u8 EnableLanLtr; - u8 EnableLanK1Off; - u8 LanClkReqSupported; + bool EnableLanLtr; + bool EnableLanK1Off; + bool LanClkReqSupported; u8 LanClkReqNumber; /* SATA related */ @@ -111,15 +111,15 @@ SATA_AHCI = 0, SATA_RAID = 1, } SataMode; - u8 SataSalpSupport; - u8 SataPortsEnable[8]; - u8 SataPortsDevSlp[8]; - u8 SataPortsSpinUp[8]; - u8 SataPortsHotPlug[8]; + bool SataSalpSupport; + bool SataPortsEnable[8]; + bool SataPortsDevSlp[8]; + bool SataPortsSpinUp[8]; + bool SataPortsHotPlug[8]; u8 SataSpeedLimit; /* Audio related */ - u8 DspEnable; + bool DspEnable; /* HDA Virtual Channel Type Select */ enum { @@ -140,7 +140,7 @@ u32 TraceHubMemReg1Size; /* DCI Enable/Disable */ - u8 PchDciEn; + bool PchDciEn; /* * PCIe Root Port configuration: @@ -175,14 +175,14 @@ * 0: Disable Root Port * 1: Enable Root Port */ - u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* * Enable/Disable Clk-req support for Root Port * 0: Disable Clk-Req * 1: Enable Clk-req */ - u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; /* * Clk-req source for Root Port @@ -199,17 +199,17 @@ * 0: Disable AER * 1: Enable AER */ - u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; /* * Enable/Disable Latency Tolerance Reporting for Root Port * 0: Disable LTR * 1: Enable LTR */ - u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ - u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* PCIE RP Max Payload, Max Payload Size supported */ enum { @@ -238,7 +238,7 @@ /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; - u8 SsicPortEnable; + bool SsicPortEnable; /* * SerialIO device mode selection: @@ -271,8 +271,8 @@ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* eMMC and SD */ - u8 ScsEmmcHs400Enabled; - u8 EmmcHs400DllNeed; + bool ScsEmmcHs400Enabled; + bool EmmcHs400DllNeed; u8 ScsEmmcHs400RxStrobeDll1; u8 ScsEmmcHs400TxDataDll; @@ -283,7 +283,7 @@ Display_Auto, Display_Switchable, } PrimaryDisplay; - u8 SkipExtGfxScan; + bool SkipExtGfxScan; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; @@ -291,34 +291,34 @@ u8 SciIrqSelect; /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ u8 TcoIrqSelect; - u8 TcoIrqEnable; + bool TcoIrqEnable; /* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.*/ - u8 LockDownConfigGlobalSmi; + bool LockDownConfigGlobalSmi; /* * Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh * in the upper and lower 128-byte bank of RTC RAM. */ - u8 LockDownConfigRtcLock; + bool LockDownConfigRtcLock; /* * Determine if WLAN wake from Sx, corresponds to the * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. */ - u8 PchPmWoWlanEnable; + bool PchPmWoWlanEnable; /* * Determine if WLAN wake from DeepSx, corresponds to * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. */ - u8 PchPmWoWlanDeepSxEnable; + bool PchPmWoWlanDeepSxEnable; /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register */ - u8 WakeConfigWolEnableOverride; + bool WakeConfigWolEnableOverride; /* Determine if enable PCIe to wake from deep Sx*/ - u8 WakeConfigPcieWakeFromDeepSx; + bool WakeConfigPcieWakeFromDeepSx; /* Deep Sx Policy. Values 0: PchDeepSxPolDisable, * 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, * 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn @@ -360,7 +360,7 @@ * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, * 1: Enabled */ - u8 PmConfigSlpStrchSusUp; + bool PmConfigSlpStrchSusUp; /* * PCH power button override period. * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s @@ -372,7 +372,7 @@ * Indicates platform supports VCCPrim_Core Voltage Margining * in SLP_S0# asserted state. */ - u8 PchPmSlpS0VmEnable; + bool PchPmSlpS0VmEnable; enum { RESET_POWER_CYCLE_DEFAULT = 0, @@ -407,7 +407,7 @@ u8 SendVrMbxCmd; /* Enable/Disable host reads to PMC XRAM registers */ - u8 PchPmPmcReadDisable; + bool PchPmPmcReadDisable; /* * Use SD card detect GPIO with default config: @@ -434,7 +434,7 @@ * 0b - Disable * 1b - Enable noise mitigation */ - u8 AcousticNoiseMitigation; + bool AcousticNoiseMitigation; /* * Disable Fast Package C-state ramping @@ -442,9 +442,9 @@ * 0b - Enabled * 1b - Disabled */ - u8 FastPkgCRampDisableIa; - u8 FastPkgCRampDisableGt; - u8 FastPkgCRampDisableSa; + bool FastPkgCRampDisableIa; + bool FastPkgCRampDisableGt; + bool FastPkgCRampDisableSa; /* * Adjust the VR slew rates @@ -462,7 +462,7 @@ * 1b - Enabled * 0b - Disabled */ - u8 eist_enable; + bool eist_enable; /* * Activates VR mailbox command for Intersil VR C-state issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/75880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic40917689092e8d897a3ba92ac767cdb3b595eb3 Gerrit-Change-Number: 75880 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/pineview/raminit.h: Clean sysinfo
by Elyes Haouas (Code Review) 24 Jun '23

24 Jun '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76098?usp=email ) Change subject: nb/intel/pineview/raminit.h: Clean sysinfo ...................................................................... nb/intel/pineview/raminit.h: Clean sysinfo Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/raminit.h 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/76098/1 diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h index 4a0547b..fb33976 100644 --- a/src/northbridge/intel/pineview/raminit.h +++ b/src/northbridge/intel/pineview/raminit.h @@ -95,19 +95,10 @@ u16 mediumphase; u16 readptrdelay; - int txt_enabled; - int cores; int boot_path; - int max_ddr2_mhz; - int max_ddr3_mt; - int max_fsb_mhz; - int max_render_mhz; - int enable_igd; - int enable_peg; u16 ggc; int dimm_config[2]; - int dimms_per_ch; int spd_type; int channel_capacity[2]; struct timings selected_timings; @@ -117,7 +108,6 @@ u8 nodll; u8 async; u8 dt0mode; - u8 mvco4x; /* 0 (8x) or 1 (4x) */ }; void sdram_initialize(int boot_path, const u8 *sdram_addresses); -- To view, visit https://review.coreboot.org/c/coreboot/+/76098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Gerrit-Change-Number: 76098 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6
by Elyes Haouas (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76080?usp=email ) Change subject: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Gerrit-Change-Number: 76080 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 24 Jun 2023 06:11:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/{skl,kbl}: Use true/false keywords for non-array dt options
by Elyes Haouas (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Angel Pons, Erik van den Bogaert, Felix Singer, Frans Hendriks, Jeremy Soller, Michał Żygowski, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75888?usp=email ) Change subject: mb/{skl,kbl}: Use true/false keywords for non-array dt options ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff063c37a093e597c6b73a583903ce5e4f698856 Gerrit-Change-Number: 75888 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sat, 24 Jun 2023 06:10:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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2014

2013

coreboot-gerrit June 2023