coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Branden Waldner (Code Review) 17 Apr '23

17 Apr '23

Branden Waldner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74316 ) Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I tested it on my asus p2b and p2-99 and they both had issues with linux erroring out trying to access the drives from the initramfs. I can post some serial logs (coreboot and linux console) on the mailing list, but I'm not sure if they would have any useful infomation in them. -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 23:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/tigerlake: Remove the SOC_INTEL_TIGERLAKE_S3 symbol
by Nico Huber (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74405 ) Change subject: soc/intel/tigerlake: Remove the SOC_INTEL_TIGERLAKE_S3 symbol ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/74405/comment/27c87ef9_608f97ef PS3, Line 254: SOC_INTEL_ALDERLAKE_S3 Missed a spot. Probably because it was name wrong in the first place :) -- To view, visit https://review.coreboot.org/c/coreboot/+/74405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Gerrit-Change-Number: 74405 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 22:48:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/tigerlake: Remove the SOC_INTEL_TIGERLAKE_S3 symbol
by Nico Huber (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74405 ) Change subject: soc/intel/tigerlake: Remove the SOC_INTEL_TIGERLAKE_S3 symbol ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Gerrit-Change-Number: 74405 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 22:38:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device: Move D3COLD_SUPPORT symbol
by Nico Huber (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74404 ) Change subject: device: Move D3COLD_SUPPORT symbol ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/74404/comment/6ec79962_fe3dd24e PS4, Line 1013: if any device does not : properly support the D3Cold state. This was dropped at the source. -- To view, visit https://review.coreboot.org/c/coreboot/+/74404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4 Gerrit-Change-Number: 74404 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 22:34:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
by Nico Huber (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Felix Singer, Sean Rhodes, Tarun Tuli, Subrata Banik, Christian Walter, Angel Pons, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74403 ) Change subject: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Gerrit-Change-Number: 74403 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 16 Apr 2023 22:31:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by Sridhar Siricilla (Code Review) 16 Apr '23

16 Apr '23

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 15:49:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 16 Apr '23

16 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/6ced9ab4_ac3ad100 PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { : timestamp_add_now(TS_CSE_FW_SYNC_START); : cse_fw_sync(); : timestamp_add_now(TS_CSE_FW_SYNC_END); : : if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) : store_cse_rw_fw_version(); : } : } > > > > The codeflow is quite confusing... Can't you add store_cse_rw_fw_version in the same function call? Those functions for SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE and SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE look close to identical > > > > > > why function call ? inside cse_fw_sync? > > > > *which > > the major dependency to store the cse fw version is cse_fw_sync, which has to be performed prior to the store operation hence, used different boot state machine callbacks > > for cse_fw_sync at romstage, we can store it any where post that stage (after cbmem is online). > > for cse_fw_sync at ramstage, i have stored immediately after performing the sync operation. @Arthur, would you mind to take a look into this cl and share your comments based on the above response. We are in a little time sensitive zone with this cl and would like to enable this feature ASAP. looking forward to get your support -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 17 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 16 Apr 2023 15:34:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs/config.raptor-cs-talos-2: add config for op-build
by build bot (Jenkins) (Code Review) 16 Apr '23

16 Apr '23

Attention is currently required from: Igor Bagnucki, Krystian Hebel, Sergii Dmytruk. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67070 ) Change subject: configs/config.raptor-cs-talos-2: add config for op-build ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49ad6094acaccf731ab6d6b45ac103d485a3179c Gerrit-Change-Number: 67070 Gerrit-PatchSet: 7 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sun, 16 Apr 2023 15:23:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Create screebo variant
by Lean Sheng Tan (Code Review) 16 Apr '23

16 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74391 ) Change subject: mb/google/rex: Create screebo variant ...................................................................... mb/google/rex: Create screebo variant Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/screebo/Makefile.inc A src/mainboard/google/rex/variants/screebo/gpio.c A src/mainboard/google/rex/variants/screebo/include/variant/ec.h A src/mainboard/google/rex/variants/screebo/include/variant/gpio.h A src/mainboard/google/rex/variants/screebo/memory/Makefile.inc A src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/screebo/overridetree.cb 10 files changed, 105 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 6cea7fc..62ece95 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -80,10 +80,12 @@ config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 + default "Screebo" if BOARD_GOOGLE_SCREEBO config VARIANT_DIR string default "rex0" if BOARD_GOOGLE_REX0 + default "screebo" if BOARD_GOOGLE_SCREEBO config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index ca63842..886a2f0 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -4,3 +4,7 @@ bool "-> Rex 0" select BOARD_GOOGLE_BASEBOARD_REX select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_SCREEBO + bool "-> Screebo" + select BOARD_GOOGLE_BASEBOARD_REX diff --git a/src/mainboard/google/rex/variants/screebo/Makefile.inc b/src/mainboard/google/rex/variants/screebo/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c new file mode 100644 index 0000000..b6e346f --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/ec.h b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb new file mode 100644 index 0000000..6c284b3 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/meteorlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/74391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Gerrit-Change-Number: 74391 Gerrit-PatchSet: 5 Gerrit-Owner: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/jasperlake: Hook up GMA ACPI brightness controls
by Lean Sheng Tan (Code Review) 16 Apr '23

16 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74324 ) Change subject: soc/intel/jasperlake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/jasperlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on google/magpie. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74324 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/graphics.c 4 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 338c467..660b24a 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -219,4 +219,16 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 + +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 endif diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index bd8dcd8..31ea865 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 2839148..3e47e00 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -5,6 +5,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> #include <intelblocks/pcie_rp.h> @@ -431,6 +432,9 @@ * false: Disabled (more wakes, higher power) */ bool cnvi_reduce_s0ix_pwr_usage; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c new file mode 100644 index 0000000..773f3c6 --- /dev/null +++ b/src/soc/intel/jasperlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_jasperlake_config *const chip = dev->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8 Gerrit-Change-Number: 74324 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

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