Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74530 )
Change subject: lib: Perform early initialization of FW config in ramstage
......................................................................
lib: Perform early initialization of FW config in ramstage
This patch moves the fw_config_init() function from `BS_DEV_INIT_CHIPS`
boot state to its prior state aka `BS_PRE_DEVICE`.
Without this patch the early ramstage code (running from BS_PRE_DEVICE
boot state) is unable to probe PCI devices using FW_CONFIG.
For example: below sample code is unable to give the correct state of
the UFS PCI device with FW_CONFIG `STORAGE_UFS = 0` at early ramstage
function:
device ref ufs on
probe STORAGE STORAGE_UFS
end
Without this patch: The results is UFS device is enable
With this patch: The results is UFS device is disable
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: If36e7c7d2edc74a2b7fcc192690af73651e87183
---
M src/lib/fw_config.c
1 file changed, 29 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/74530/1
diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c
index e1fbe74..d7d4484 100644
--- a/src/lib/fw_config.c
+++ b/src/lib/fw_config.c
@@ -175,5 +175,5 @@
cached_configs[probe_index(probe->mask)] = probe;
}
}
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, fw_config_init, NULL);
#endif
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Change subject: amdfwtool: Add --output-manifest option
......................................................................
Patch Set 3:
(4 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/74266/comment/8b9fdea3_855d88da
PS3, Line 853: fopen(
Recommend to use open system call to be consistent with the rest of the use-cases in this utility.
https://review.coreboot.org/c/coreboot/+/74266/comment/10c5743e_4270bdb5
PS3, Line 867: blob_fd = open(index->filename, O_RDONLY);
: read(blob_fd, &hdr, sizeof(hdr));
: fprintf(version_file, "type: 0x%02x ver:%02x.%02x.%02x.%02x\n",
: index->type, hdr.version[3], hdr.version[2],
: hdr.version[1], hdr.version[0]);
: close(blob_fd);
You can add a function pointer/callback and a human-readable name of the binary into amd_fw_entry.
```
typedef struct _amd_fw_entry {
amd_fw_type type;
...
amd_fw_entry_hash *hash_entries;
void (*output_manifest)(int manifest_fd, amd_fw_entry *fw_table);
char blob_acronym[MAX_BLOB_ACRONYM_LEN];
} amd_fw_entry;
```
Then you can move the part of dumping the firmware version into a separate function and register that function as a output_manifest callback for the required blobs along with the blob_acronym.
Then you can update this for-loop as:
```
for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
if (!index->filename || !index->output_manifest )
continue;
index->output_manifest(manifest_fd, index);
}
```
I feel this will help to scale well when you to dump the version for additional blobs in the future.
https://review.coreboot.org/c/coreboot/+/74266/comment/76c1e914_62544ea7
PS3, Line 1509: _SIG
_SIG suffix not required.
https://review.coreboot.org/c/coreboot/+/74266/comment/369125fa_72fac82c
PS3, Line 2145: if (manifest_file) {
: dump_blob_version(manifest_file, amd_psp_fw_table);
: }
This can be done before the amdfw_tool_cleanup. There is nothing in keeping it here. But it is too premature to dump the manifest file before the amdfw*.rom is ready.
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Change subject: mb/google/brya/var/crota: select SOC_INTEL_RAPTORLAKE
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74494/comment/21c005e1_5818b94e
PS2, Line 17: Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
This change needs the following Cq-Depend:
Cq-Depend: chromium:4430832
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Change subject: Docs: Add a debugging section to the tutorial
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Hi Felix, any feedback? I don't want this to take forever to review...
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74221
to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
......................................................................
soc/intel/meteorlake: Add VPU into the DMAR SATC table
This change adds the VPU into the DMAR SATC table in order to support
the VPU IO virtualization.
BUG=None
TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table
includeded the VPU entry.
Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/meteorlake/acpi.c
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74221/2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74075 )
Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
......................................................................
mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF),
hence update the correct bridge number in the device tree.
TEST: Builds and boots, the device enumerates.
[DEBUG] PCI: 00:02.4 [1022/14ee] enabled
[DEBUG] PCI: 01:00.0 [144d/a80a] enabled
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/mainboard/amd/mayan/devicetree_phoenix.cb
1 file changed, 21 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Fred Reitberger: Looks good to me, approved
diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb
index 9d1a4b3..697db12 100644
--- a/src/mainboard/amd/mayan/devicetree_phoenix.cb
+++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb
@@ -160,7 +160,7 @@
device ref iommu on end
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
- device ref gpp_bridge_2_3 on end # NVMe SSD
+ device ref gpp_bridge_2_4 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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Change subject: mb/google/corsola: Report SKU and panel ID for unprovisioned devices
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Please remove `Work in Progress`
Done, but this changed is not verified since I haven't got the starmie board yet..
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Change subject: mb/google/corsola: Report SKU and panel ID for unprovisioned devices
......................................................................
Patch Set 6:
(2 comments)
This change is ready for review.
File src/mainboard/google/corsola/boardid.c:
https://review.coreboot.org/c/coreboot/+/74135/comment/a53d6c12_fb957a14
PS5, Line 78: adc_voltages_table = adc_voltages_detachable;
: assert(channel < ARRAY_SIZE(adc_voltages_detachable));
> check the channel count before the assignment.
Done
https://review.coreboot.org/c/coreboot/+/74135/comment/71324f7a_4c6bf094
PS5, Line 98: /* Return the Panel ID. The ADC channel 5 used for panel id
: in starmie board.
: */
> /* Detachables use ADC channel 5 for panel ID */
Done
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74289 )
Change subject: crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
although i don't expect this to cause any trouble, i'd strongly prefer if the tooling was upgraded after a release and not 2 days before a release
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