coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/mediatek/mt8193: Fix set but unused variable
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Yidi Lin. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74554 ) Change subject: soc/mediatek/mt8193: Fix set but unused variable ...................................................................... soc/mediatek/mt8193: Fix set but unused variable This fixes a clang warning. Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/74554/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index c772885..ab49bee 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -2170,7 +2170,7 @@ u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1, vref_use = 0; u8 vref_scan_enable = 0, small_reg_value = 0xff; s16 dly_begin = 0, dly_end = 0, dly_step = 1; - u32 dummy_rd_bak_engine2 = 0, finish_bit, win_min_max = 0; + u32 dummy_rd_bak_engine2 = 0, win_min_max = 0; static u16 dq_precal_result[DQS_NUMBER]; struct vref_perbit_dly vref_dly; struct win_perbit_dly win_perbit[DQ_DATA_WIDTH]; @@ -2240,7 +2240,6 @@ vref_dly.max_win_sum = 0; for (vref = vref_begin; vref < vref_end; vref += vref_step) { small_reg_value = 0xff; - finish_bit = 0; if (type == TX_WIN_DQ_ONLY) vref_use = vref | (vref_range << 6); else -- To view, visit https://review.coreboot.org/c/coreboot/+/74554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Gerrit-Change-Number: 74554 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparison
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Yidi Lin. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74553 ) Change subject: soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparison ...................................................................... soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparison Comparing an unsigned int to be smaller than 0 has no impact. This fixes a clang warning. Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/mediatek/mt8195/apusys_devapc.c 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/74553/1 diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c index d5f8978..1f2b520 100644 --- a/src/soc/mediatek/mt8195/apusys_devapc.c +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -151,7 +151,7 @@ u32 apc_set_index; u32 *base; - if (perm >= PERM_NUM || perm < 0) { + if (perm >= PERM_NUM || perm != 0) { printk(BIOS_ERR, "[NOC_DAPC] permission type:%#x is not supported!\n", perm); return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; } @@ -192,7 +192,7 @@ u32 apc_set_index; u32 *base; - if (perm >= PERM_NUM || perm < 0) { + if (perm >= PERM_NUM || perm != 0) { printk(BIOS_ERR, "[APUAPC] perm type:%#x is not supported!\n", perm); return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Gerrit-Change-Number: 74553 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8195: More sure ucDoneFlg is initialized
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74552 ) Change subject: vendorcode/mediatek/mt8195: More sure ucDoneFlg is initialized ...................................................................... vendorcode/mediatek/mt8195: More sure ucDoneFlg is initialized One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/74552/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index 96de0ad..702c65a 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -3066,7 +3066,7 @@ //U8 *uiLPDDR_O1_Mapping = NULL; //U32 u4value = 0, u4dq_o1 = 0 u4value1 = 0, u4dq_o1_tmp[DQS_BYTE_NUMBER]; - U8 byte_i, rank_i, ucDoneFlg; + U8 byte_i, rank_i, ucDoneFlg = 0; //S32 iDelay, ClockDelayMax; //U8 ucStatus[DQS_BYTE_NUMBER], ucdq_o1[DQS_BYTE_NUMBER], ucdq_o1_shift[DQS_BYTE_NUMBER] //U8 ucHW_cmp_raw_data, uccmp_result[DQS_BYTE_NUMBER]; -- To view, visit https://review.coreboot.org/c/coreboot/+/74552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Gerrit-Change-Number: 74552 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8195: Make order of operators more explicit
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74551 ) Change subject: vendorcode/mediatek/mt8195: Make order of operators more explicit ...................................................................... vendorcode/mediatek/mt8195: Make order of operators more explicit Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/74551/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c index 6634e48..14ea0b3 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c @@ -116,7 +116,7 @@ LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); - MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR3 = (((!tr->DBI_WR) & 1)<<7) | (((!tr->DBI_RD) & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); LP4_MRS(p, 12, MR12 , rank); -- To view, visit https://review.coreboot.org/c/coreboot/+/74551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Gerrit-Change-Number: 74551 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8195: Fix superfluous brackets
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74550 ) Change subject: vendorcode/mediatek/mt8195: Fix superfluous brackets ...................................................................... vendorcode/mediatek/mt8195: Fix superfluous brackets Clang warns about this. Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74550/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index 6d80ae7..96de0ad 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -6512,7 +6512,7 @@ u2VrefEnd = 0; u2VrefStep = 1; - if ((u1UseTestEngine == PATTERN_TEST_ENGINE)) + if (u1UseTestEngine == PATTERN_TEST_ENGINE) { #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1)) diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 311939d..e885424 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -1440,7 +1440,7 @@ DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); #if TX_K_DQM_WITH_WDBI - if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) + if (p->DBI_W_onoff[p->dram_fsp]==DBI_ON) { //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n")); -- To view, visit https://review.coreboot.org/c/coreboot/+/74550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Gerrit-Change-Number: 74550 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8195: Fix casting enum of different types
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74549 ) Change subject: vendorcode/mediatek/mt8195: Fix casting enum of different types ...................................................................... vendorcode/mediatek/mt8195: Fix casting enum of different types Clang warns about this. Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c 1 file changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/74549/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index e6b9333..848523d 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -1497,8 +1497,8 @@ if (!u1IsLP4Family(dram_type) || read_offline_dram_mdl_data(&dram_info) < 0) { #endif - dram_mode = (u1IsLP4Family(dram_type))? - CBT_BYTE_MODE1 : CBT_NORMAL_MODE; + dram_mode = (DRAM_CBT_MODE_EXTERN_T)((u1IsLP4Family(dram_type))? + CBT_BYTE_MODE1 : CBT_NORMAL_MODE); #if defined(SLT) SLT_Test_Main_Flow(dram_type, dram_mode, &dram_info, SLT_USED); #endif @@ -2280,4 +2280,3 @@ } #endif - -- To view, visit https://review.coreboot.org/c/coreboot/+/74549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Gerrit-Change-Number: 74549 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vendorcode/mediatek/mt8195: Fix set but unused variables
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74548 ) Change subject: vendorcode/mediatek/mt8195: Fix set but unused variables ...................................................................... vendorcode/mediatek/mt8195: Fix set but unused variables The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8195/dramc/Hal_io.c M src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c M src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/emi.c M src/vendorcode/mediatek/mt8195/include/dramc_common.h M src/vendorcode/mediatek/mt8195/include/x_hal_io.h 8 files changed, 42 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74548/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c index db551fe..281c319 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c +++ b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c @@ -501,7 +501,6 @@ { U8 ii, u1AllCount; U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); - U8 u1BCSupport = TRUE; reg32 &= 0xffff; @@ -512,7 +511,6 @@ reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; - u1BCSupport = FALSE; } else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { @@ -551,7 +549,6 @@ U32 u4Val, u4RegTmp; U8 ii, u1AllCount; U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); - U8 u1BCSupport = TRUE; reg32 &= 0xffff; @@ -562,7 +559,6 @@ reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; - u1BCSupport = FALSE; } else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c index 5fa9bab..6d88374 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c @@ -131,7 +131,7 @@ U32 u4TxPipeline = 0, u4RxPipeline = 0; U32 u4Datlat_dsel = 0, u4Datlat_margin = 1, u4RDSEL_Offset = 2; U32 u4DQ_P2S_Ratio = A_D->DQ_P2S_RATIO, u4CA_p2s_ratio = 0, u4CKR = A_D->CKR; - U32 u4CAdefault_delay = 1, u4CS2RL_start = 0, u4tRPRE_toggle = 0; + U32 u4CAdefault_delay = 1, u4CS2RL_start = 0; U32 u4DQSIEN_ser_latency = 0, u4CA_ser_latency = 0; U32 u4DQ_ui_unit = 0, u4CA_ui_unit = 0, u4Dram_ui_ratio = 2, u4MCK_unit = 0; U32 u4RL[2] = {0}, u4RLMax = 0, u4DQ_2_1stDVI4CK = 0, u4CA_MCKIO_ui_unit = 0; @@ -144,7 +144,6 @@ if (u1IsLP4Family(p->dram_type)) { u4CS2RL_start = 7; - u4tRPRE_toggle = 0; u4tDQSCK_Max = 3500; u4RL[0] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_0], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); u4RL[1] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_1], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); @@ -181,6 +180,7 @@ u4MCK_unit = u4DQ_ui_unit * u4DQ_P2S_Ratio; u4CA_p2s_ratio = u4DQ_P2S_Ratio / u4CKR; u4DQSIEN_ser_latency = u1GetDQSIEN_p2s_latency(u4DQ_P2S_Ratio); + (void)u4DQSIEN_ser_latency; u4CA_ser_latency = u1GetDQ_CA_p2s_latency(u4CA_p2s_ratio, A_D->CA_FULL_RATE); u4CA_MCKIO_ui_unit = u4DQ_ui_unit * u4CKR / (A_D->CA_FULL_RATE + 1); u4RX_rdcmdout2rdcmdbus_by_ps = 3 * u4MCK_unit + u4CAdefault_delay * u4CA_ui_unit + u4CA_ser_latency * u4CA_MCKIO_ui_unit /*+ RX_C->ca_default_PI * RX_C->ca_MCKIO_ps / RX_C->ca_ui_pi_ratio*/ ; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c index 7341ae3..81f7fdf 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c @@ -1338,12 +1338,10 @@ #endif void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable) { - U32 val, fld; + U32 fld; fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx)); - val = (u1Enable) ? 1 : 0; - vIO32WriteFldAlign_All(u4Reg, u1Enable, fld); } diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index ff9fbdd..6d80ae7 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -2443,7 +2443,7 @@ //U32 uiCA, uiFinishCount, uiTemp; //S16 iDelay, pi_dly; //S32 iFirstPass_tmp[CATRAINING_NUM], iLastPass_tmp[CATRAINING_NUM]; - U32 uiCAWinSumMax; //uiCAWinSum, + //uiCAWinSum, U8 operating_fsp; U16 operation_frequency; //S32 iCA_PerBit_DelayLine[CATRAINING_NUM] = {0}, iCK_MIN = 1000 @@ -2466,9 +2466,8 @@ S16 pi_step; //, pi_step_bk; S16 pi_start, pi_end; - u32 ca_ui, ca_ui_default; //, ca_ui_tmp + u32 ca_ui; //, ca_ui_tmp u32 ca_mck; //Vca_mck_tmp, a_mck_default - u32 ca_cmd0; u8 ca_pin_num; u8 step_respi = AUTOK_RESPI_1; //u32 capi_max; @@ -2573,9 +2572,9 @@ #endif - ca_ui_default = ca_ui = get_ca_ui(p); + ca_ui = get_ca_ui(p); ca_mck = get_ca_mck(p); - ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); + u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); vAutoRefreshSwitch(p, DISABLE); @@ -2591,9 +2590,6 @@ vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); - - uiCAWinSumMax = 0; - operating_fsp = p->dram_fsp; operation_frequency = p->frequency; @@ -5628,6 +5624,7 @@ u1GatingErrorFlag=1; mcSHOW_ERR_MSG(("error, no all pass taps in DQS!,pass_byte_count=%d\n", pass_byte_count)); } + (void)u1GatingErrorFlag; #if (ENABLE_GATING_AUTOK_WA) @@ -6355,7 +6352,7 @@ //U32 u1vrefidx; //U8 ucbit_first, ucbit_last; //S16 iDelay = 0, S16DelayBegin = 0, u4DelayStep=1; - U16 u16DelayStep = 1; //u16DelayEnd = 0 + //u16DelayEnd = 0 //U32 uiFinishCount; //U32 u4err_value, u4fail_bit, u4value; PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; //WinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM] @@ -6365,10 +6362,9 @@ U16 u2FinalVref [DQS_BYTE_NUMBER]= {0xe, 0xe}; //u2VrefLevel U16 u2VrefBegin, u2VrefEnd, u2VrefStep; //U32 u4fail_bit_R, u4fail_bit_F; - U8 u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE),u1PrintCalibrationProc; + U8 u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE); //U16 u1min_bit_by_vref[DQS_BYTE_NUMBER], u1min_winsize_by_vref[DQS_BYTE_NUMBER]; //U16 u1min_bit[DQS_BYTE_NUMBER], u1min_winsize[DQS_BYTE_NUMBER]={0}; - U8 u1CalDQMNum = 0; //U32 u4PassFlags = 0xFFFF; U16 backup_RX_FinalVref_Value[DQS_BYTE_NUMBER]={0}; @@ -6411,14 +6407,12 @@ #if (FEATURE_RDDQC_K_DMI == TRUE) if (u1UseTestEngine == PATTERN_RDDQC) { - u1CalDQMNum = 2; iDQMDlyPerbyte[0] = -0xFFFFFF; iDQMDlyPerbyte[1] = -0xFFFFFF; } else #endif { - u1CalDQMNum = 0; iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); @@ -6528,8 +6522,6 @@ #endif } - u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL)); - #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) { @@ -6599,7 +6591,9 @@ else { u2VrefBegin = 0; + (void)u2VrefBegin; u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1; + (void)u2VrefEnd; //mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); } #endif @@ -6626,11 +6620,9 @@ u2VrefEnd = 0; u2VrefStep = 1; } + (void)u2VrefStep; - if (u1UseTestEngine == PATTERN_RDDQC) - u16DelayStep <<= 1; - #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) { @@ -7083,10 +7075,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) { //U8 ii, ucStartCalVal = 0; - U32 u4prv_register_080; //U32 u4err_value = 0xffffffff; - U8 ucfirst, ucbegin, ucsum, ucbest_step; //ucpipe_num = 0; - U16 u2DatlatBegin; + U8 ucbest_step; //ucpipe_num = 0; if (!p) @@ -7104,7 +7094,7 @@ mcSHOW_DBG_MSG(("[RxdatlatCal]\n")); - u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); + u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); @@ -7115,12 +7105,7 @@ //mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); - ucfirst = 0xff; - ucbegin = 0; - ucsum = 0; - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); - u2DatlatBegin = 0; #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) if (p->femmc_Ready == 1) @@ -9202,9 +9187,6 @@ //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff; //U8 ucdq_final_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_final_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0}; //DRAM_STATUS_T KResult; - U8 u1TxDQOEShift = 0; - - u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; //mcDUMP_REG_MSG(("\n[dumpRG] DramcTXOECalibration\n")); #if VENDER_JV_LOG @@ -9667,9 +9649,8 @@ U16 ucdqs_dly, fgcurrent_value, fginitial_value; U16 ucsearch_state = 0xffff; U32 u4sample_cnt, u4ones_cnt[DQS_BYTE_NUMBER]; - U8 check; - check = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), MISC_DUTYSCAN1_EYESCAN_DQS_OPT); + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), MISC_DUTYSCAN1_EYESCAN_DQS_OPT); for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) { diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index e3baf7b..311939d 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -151,6 +151,7 @@ //int ret; vio18 = vcore = vdram = vddq = vmddr = 0; + (void)vio18; #if __ETT__ hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c index 5a1f09d..6a9321cf 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/emi.c +++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c @@ -673,9 +673,6 @@ unsigned long long ch0_rank0_size, ch0_rank1_size; unsigned long long ch1_rank0_size, ch1_rank1_size; unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH); - unsigned long long dq_width; - - dq_width = 2; dram_rank_size[0] = 0; dram_rank_size[1] = 0; diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_common.h b/src/vendorcode/mediatek/mt8195/include/dramc_common.h index 0da3525..2d21b94 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_common.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_common.h @@ -73,6 +73,12 @@ /* mcSHOW_DBG_MSG3: Medium Low */ /* mcSHOW_DBG_MSG4: Low */ /**********************************************/ + +#define _print(...) \ + do { \ + printk(BIOS_NEVER, ##__VA_ARGS__); \ + } while (0) + #if __FLASH_TOOL_DA__ #define printf DBG_MSG #define print DBG_MSG @@ -81,7 +87,7 @@ #undef printf #define printf #undef print - #define print + #define print _print #endif #endif @@ -246,10 +252,10 @@ #define mcSHOW_TIME_MSG(_x_) #define mcSHOW_ERR_MSG(_x_) {print _x_;} #else - #define mcSHOW_DBG_MSG(_x_) - #define mcSHOW_DBG_MSG2(_x_) + #define mcSHOW_DBG_MSG(_x_) { print _x_; } + #define mcSHOW_DBG_MSG2(_x_) { print _x_; } #define mcSHOW_DBG_MSG3(_x_) - #define mcSHOW_DBG_MSG4(_x_) + #define mcSHOW_DBG_MSG4(_x_) { print _x_; } #define mcSHOW_DBG_MSG5(_x_) #define mcSHOW_DBG_MSG6(_x_) #define mcSHOW_JV_LOG_MSG(_x_) diff --git a/src/vendorcode/mediatek/mt8195/include/x_hal_io.h b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h index 5989ec8..184dd7a 100644 --- a/src/vendorcode/mediatek/mt8195/include/x_hal_io.h +++ b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h @@ -46,7 +46,7 @@ extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); // ========================= -// public Macro for general use. +// public Macro for general use. //========================== #define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32) #define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32) @@ -65,6 +65,7 @@ UINT16 upk = 1; \ INT32 msk = (INT32)(list); \ { upk = 0; \ + (void)upk; \ ((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \ } \ }/*lint -restore */ @@ -80,6 +81,7 @@ UINT16 upk = 1; \ INT32 msk = (INT32)(list); \ { upk = 0; \ + (void)upk; \ ((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \ } \ }/*lint -restore */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Gerrit-Change-Number: 74548 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/dptx.c: Remove set but unused variables
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Yidi Lin. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74547 ) Change subject: soc/mediatek/dptx.c: Remove set but unused variables ...................................................................... soc/mediatek/dptx.c: Remove set but unused variables This fixes clang warning about set but unused variables. Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/mediatek/common/dp/dptx.c 1 file changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/74547/1 diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx.c index 08d288a..c123f88 100644 --- a/src/soc/mediatek/common/dp/dptx.c +++ b/src/soc/mediatek/common/dp/dptx.c @@ -445,7 +445,7 @@ { u8 bpp; u16 sram_read_start = DPTX_TBC_BUF_READSTARTADRTHRD; - int tu_size, n_value, f_value, pixclk_mhz; + int tu_size, f_value, pixclk_mhz; bpp = dptx_hal_get_colorbpp(mtk_dp); pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; @@ -453,7 +453,6 @@ (mtk_dp->train_info.linkrate * 27 * mtk_dp->train_info.linklane_count * 8); - n_value = tu_size / 10; f_value = tu_size % 10; printk(BIOS_DEBUG, "TU_size %d, FValue %d\n", tu_size, f_value); @@ -950,7 +949,6 @@ static int dptx_set_trainingstart(struct mtk_dp *mtk_dp) { - int ret = DPTX_PASS; u8 lanecount; u8 linkrate; u8 buffer; @@ -1006,7 +1004,7 @@ mtk_dp->train_info.eq_done = false; dptx_training_changemode(mtk_dp); - ret = dptx_trainingflow(mtk_dp, linkrate, lanecount); + dptx_trainingflow(mtk_dp, linkrate, lanecount); if (!mtk_dp->train_info.cr_done) { /* CR fail and reduce link capability. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Gerrit-Change-Number: 74547 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Cast enum types
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Xi Chen. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74546 ) Change subject: vendorcode/mediatek/mt8192: Cast enum types ...................................................................... vendorcode/mediatek/mt8192: Cast enum types Clang warns about using the wrong enum types as arguments. Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c 1 file changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/74546/1 diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index 4a98d8d..e267154 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -153,6 +153,7 @@ unsigned int vio18, vcore, vdram, vddq, vmddr; vio18 = vcore = vdram = vddq = vmddr = 0; + (void)vio18; #if __ETT__ hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); @@ -1502,11 +1503,11 @@ #endif #if ((!defined(FIRST_BRING_UP)) || (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF)) && (!__FLASH_TOOL_DA__) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, p->pDFSTable->shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)p->pDFSTable->shuffleIdx); #if SUPPORT_SAVE_TIME_FOR_CALIBRATION DramcSave_Time_For_Cal_End(p); #endif - LoadShuffleSRAMtoDramc(p, p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, (DRAM_DFS_SHUFFLE_TYPE_T)p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) #if ENABLE_SRAM_DMA_WA DPHYSRAMShuWAToSHU1(p); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) #endif @@ -1534,7 +1535,7 @@ // ignore the calibration for shuffle which is not in allCaliShuIdx, just copy first cali shuffle data if (!(allCaliShuIdx & BIT(u1ShuIdx))) { // copy first calibration shuffle to this shuffle (if DVFS, need double confirm) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx].shuffleIdx); continue; } @@ -1554,10 +1555,10 @@ RunTime_Shmoo_update_parameters(p); } #endif - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx].shuffleIdx); #if (fcFOR_CHIP_ID == fcMargaux) && (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF) // @Darren, new chip need double confirm if ((p->DRAMPinmux == PINMUX_DSC) && (gFreqTbl[u1ShuIdx].shuffleIdx == SRAM_SHU1)) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx + 1].shuffleIdx); // Copy SRAM_SHU1 to SRAM_SHU0 + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx + 1].shuffleIdx); // Copy SRAM_SHU1 to SRAM_SHU0 #endif #if SUPPORT_SAVE_TIME_FOR_CALIBRATION @@ -2699,4 +2700,3 @@ #endif //SW_CHANGE_FOR_SIMULATION #endif // __A60868_TO_BE_PORTING__ ///TODO: wait for porting --- - -- To view, visit https://review.coreboot.org/c/coreboot/+/74546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Gerrit-Change-Number: 74546 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Add or remove brackets
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Xi Chen. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74545 ) Change subject: vendorcode/mediatek/mt8192: Add or remove brackets ...................................................................... vendorcode/mediatek/mt8192: Add or remove brackets This fixes clang compilation warnings about logic problems and superfluous brackets. Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/74545/1 diff --git a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c index 53fdb16..e98e5c2 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c @@ -118,7 +118,7 @@ LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); //reverse the DBI - MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR3 = (((!tr->DBI_WR) & 1)<<7) | (((!tr->DBI_RD) & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); LP4_MRS(p, 12, MR12 , rank); diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index c228c2c..4a98d8d 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -987,7 +987,7 @@ DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); #if TX_K_DQM_WITH_WDBI - if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) + if (p->DBI_W_onoff[p->dram_fsp]==DBI_ON) { // K DQM with DBI_ON, and check DQM window spec. //msg("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/74545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Gerrit-Change-Number: 74545 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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